JP2549454B2 - Neuron mimetic network and neuron mimicking unit - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a neural cell mimicking network such as a neural computer that imitates a neural network and a neural cell mimicking unit.

2. Description of the Related Art In recent years, in order to deal with the relatively difficult problems of conventional Neumann computers such as character recognition, associative memory, and motion control, research on neural computers that imitate the nervous system of the living body and enable parallel processing and learning Has been done and various models have been proposed. At the same time, various devices that implement the model with hardware are also being considered. Among them, an example realized by an electric circuit is as shown in FIG. This is disclosed in Japanese Patent Laid-Open No. 62-295188, and basically, a plurality of amplifiers 1 having an S-shaped transfer function, and the output of each amplifier 1 is input to the input of the amplifier of another layer. A resistive fieldback network 2 is provided which connects as shown by the dashed line. CR on the input side of each amplifier 1 with a grounded capacitor and a grounded resistor
The time constant circuits 3 are individually connected. The input currents I ₁ , I ₂ , ..., _IN are then supplied to the inputs of each amplifier 1 and the output is obtained from the set of output voltages of these amplifiers 1.

Here, the strength of the connection between the nerve cells depends on the resistance 4 (resistive feedback network 2
It is represented by the resistance value of the inside lattice point), and the nerve cell response function is represented by the transfer function of each amplifier 1. Further, as is well known, the coupling between nerve cells has excitability and inhibitory property, and is mathematically represented by the sign of the coupling coefficient. However, since it is difficult to realize positive and negative with a constant on the circuit, here, the output of the amplifier 1 is divided into two, and one output is inverted to generate two positive and negative signals. Is properly selected.

FIG. 13 shows the contents of the proposal of Japanese Patent Laid-Open No. 62-295188, which is an improvement of the one shown in FIG. This is a simplified circuit based on mathematical analysis.
Instead, a negative gain amplifier 5 having a single output is used, and instead of the resistive feedback network 2, a clipped T matrix circuit 6 is used.

In any case, these circuits are basically of analog type. That is, the input / output amount is represented by a current value or a voltage value, and the internal arithmetic processing is also performed in an analog manner.

However, in the case of the analog method, it is difficult to perform stable operation with high accuracy due to, for example, temperature characteristics of an amplifier or the like, drift after power-on, and the like. Particularly in the case of a neural network, the number of amplifiers is required to be at least several hundreds, and nonlinear operation is performed, so that the operation stability is important. Further, it is not easy to change the circuit constant such as the resistance value, and the versatility is poor.

For this reason, a digital representation of the neural network is reported, for example, in the Technical Report of the Institute of Electronics, Information and Communication Engineers, "Configuration of Completely Digital Neurochip" in ICD88-130. However, this is an emulation of the conventional analog type, and the circuit is slightly complicated, such as using an up-down counter.

Means for Solving the Problems In the invention according to claim 1, in a nerve cell mimicking network which comprises a plurality of nerve cell mimicking units and processes an input determined by a pulse density, each of the nerve cell mimicking units has a plurality of Input lines, memories for separately storing coupling coefficients determined by the pulse density for each input, reading means for sequentially reading the contents of these memories, and the contents of the read memory. And an arithmetic processing unit that digitally processes the input contents and outputs as binarized outputs determined by the pulse density, and outputs the output of a certain nerve cell mimicking unit to self or another nerve cell mimicking. It is connected to the input of the unit, and in particular, the arithmetic processing means is constituted by the logical operation processing means as in the invention of claim 2.

As a nerve cell mimicking unit for this purpose, in the invention according to claim 3, in the nerve cell mimicking unit for processing a plurality of input signals and outputting a nerve cell mimicking output signal representing the processing result, the signal amount based on the pulse density A plurality of input lines for receiving an input signal represented by, a memory for storing a coupling coefficient defined by a pulse density, the input signal received from the input line and the memory corresponding to the input line. A first logical operation means for calculating a logical product with a coupling coefficient to be read for each input line; a second logical operation means for inputting an excitatory signal from the first logical operation means to perform a logical operation; A nerve cell by synthesizing output signals of the third logical operation means for performing logical operation by inputting each of the suppression type signals from the first logical operation means, and the output signals of these second logical operation means and third logical operation means It was constructed by the fourth arithmetic logic means for outputting a 倣出 force signal.

Regarding the nerve cell mimicking network or the nerve cell mimicking unit, specifically, in the invention according to claim 4, each of the nerve cell mimicking units is provided with a plurality of input lines and is individually provided for each input and pulsed. A memory of at least 3 bits or more for storing a coupling coefficient determined by the density and 1-bit information for grouping, and a reading means for sequentially reading the contents of these memories excluding the 1-bit information for grouping. A logical product means for sequentially calculating the logical product of the read contents of the memory and the input contents, and a logical sum of the results of a plurality of logical products is divided by the 1-bit information for grouping in the memory. It is formed by a logical sum means for sequentially calculating by group and a logical operation means for performing logical operation processing of the operation results for each group and outputting.

As a nerve cell mimicking unit for this purpose, in the invention according to claim 5, a plurality of input lines for receiving an input signal, a first memory for storing a coupling coefficient corresponding to each input line, and A second memory for storing, for each input line, group information for indicating which of the excitatory group and the inhibitory group the input line corresponds to; and the input received from the input line First logical operation means for calculating a logical product of a signal and a coupling coefficient corresponding to this input line read from the first memory, and the group information read from the second memory Second logical operation means for calculating the logical product with the logical product output from the first logical operation means for each input line;
Third logical operation means for calculating, for each input line, the logical product of the inversion information of the group information read from the memory and the logical product output from the first logical operation means, and these second logical operation means. Fourth logical operation means for calculating the logical sum of the logical products output from each other, fifth logical operation means for calculating the logical sum of the logical products output from these third logical operation means, and the fifth logical operation means A neural cell mimic which comprises an inverter for inverting the logical sum output from the logical operation means, and a logical operation means for calculating the logical product or logical sum of the output of this inverter and the logical sum output from the fourth logical operation means. And an output means for outputting an output signal.

Further, regarding the nerve cell mimicking network, in the invention according to claim 6, each of the nerve cell mimicking units is provided with a plurality of input lines divided into two groups, and a pulse density is provided individually for each input. At least 2 bits or more storing the coupling coefficient defined in 1., reading means for sequentially reading the contents of these memories, and logical product for sequentially calculating the logical product of the read contents of the memory and the input contents. It is formed by means, a logical sum means for sequentially calculating the logical sum of the results of a plurality of logical products for each group, and a logical operation means for performing a logical operation processing on the operation results for each group and outputting them.

As a nerve cell mimicking unit for this purpose, in the invention according to claim 7, a plurality of first input lines for receiving a first input signal and a plurality of second input lines for receiving a second input signal.
An input line, a first memory for storing a coupling coefficient corresponding to each first input line, a second memory for storing a coupling coefficient corresponding to each second input line, and from the first input line First logical operation means for calculating, for each first input line, a logical product of the first input signal received and the coupling coefficient read from the first memory corresponding to the first input line; and the second input line. Second logical operation means for calculating, for each second input line, a logical product of the second input signal received from the second input signal and the coupling coefficient read from the second memory corresponding to the second input line, and the first logical operation means. Third logical operation means for calculating the logical sum of the logical products output from the logical operation means, and fourth logical operation means for calculating the logical sum of the logical products output from these second logical operation means. , Inverts the logical sum output from the fourth logical operation means And converter, formed by an output means for outputting the more become neurons mimic output signal and logic operation means for calculating a logical product or logical sum of the logical sum output and the inverter output from said third logic operation unit.

Further, as another nerve cell mimicking network, in the invention according to claim 8, at least a plurality of the respective neuronal cell mimicking units and two or more sets are individually provided for each input, and a pulse density is provided. Memories storing predetermined coupling coefficients, reading means for sequentially reading the contents of these memories, AND means for sequentially calculating a logical product of the read contents of the memory and the input contents, and a plurality of logics It is formed by a logical sum means for sequentially calculating a logical sum of product results for each group which is divided into groups of the memory, and a logical operation means for performing logical operation processing on the operation results for each group and outputting the result.

As a nerve cell mimicking unit for this purpose, a plurality of input lines for receiving an input signal, a first memory and a second memory for respectively storing a coupling coefficient corresponding to each input line, and a memory for receiving from the input line are provided. Corresponding to the first logical operation means for calculating the logical product of the input signal and the coupling coefficient read from the first memory corresponding to the input line for each input line, the input signal received from the input line and the input line. The second logical operation means for calculating the logical product with the coupling coefficient read from the second memory for each input line, and the third logical operation means for calculating the logical sum of the logical products output from these first logical operation means.
Logical operation means, fourth logical operation means for calculating the logical sum of the logical products output from the second logical operation means, and an inverter for inverting the logical sum output from the fourth logical operation means, The inverter output and the logical sum of the logical sum output from the third logical arithmetic means are used to calculate a logical product or a logical sum, and the output means outputs a neural cell mimicking output signal.

Here, regarding the nerve cell mimicking unit according to claim 5, 7 or 9, in the invention according to claim 10, the input signal and the coupling coefficient are represented by a signal amount based on a pulse density,
Further, in the invention according to claim 11, each coupling coefficient is defined by at least one of the number of first values and the number of second values randomly arranged within a predetermined time. The pulse density is used.

Further, regarding the nerve cell mimicking network, in the invention according to claim 12, the output of a plurality of nerve cell mimicking units forming a hierarchical structure having a plurality of layers and an arbitrary nerve cell mimicking unit of a layer having a hierarchical structure. And a plurality of signal lines for connecting to the input of any neuron mimicking unit of the other layer of the hierarchical structure, and forming a part of the neuron mimicking unit, processing a plurality of input signals and representing the processing result. A neuron mimicking unit according to claim 5, 7 or 9 for outputting a neuron mimicking output signal.

Action First, the coupling coefficient determined by the pulse density and stored in the memory is sequentially read out, and the arithmetic processing with the input determined by the pulse density, for example, logical arithmetic processing such as logical product is performed by the arithmetic processing means. The result of this operation, for example, the result of the logical product, has a function approximately similar to that of the analog coupling coefficient, and becomes an actual input to the actual neuron mimicking unit. Here, since one nerve cell mimicking unit has multiple inputs, there are a plurality of calculation results, that is, logical product results. Therefore, the logical sum means in the arithmetic processing means further performs the arithmetic processing, and the logical sums are obtained. The process of obtaining the logical sum corresponds to the sum calculation and the non-linear function processing part in the analog calculation.

In such a process, there are two types of coupling, excitatory coupling and inhibitory coupling.
Process in two groups. Here, in the inventions according to claims 6 and 7, depending on which connection the input is,
Processing is performed until each group is divided into two groups and the logical sum is obtained for each group. On the other hand, in the inventions of claims 4 and 5,
At the input stage, a memory is separately prepared for 1-bit information representing two types of combination without dividing into groups, and the logical product result is divided into two groups according to the contents of this memory, and the logical sum of each group is obtained. Is performed.
Further, in the invention according to claims 8 and 9, two or more sets of memories storing coupling coefficients of excitatory coupling and inhibitory coupling are prepared for each input, and a logical sum is obtained for each group divided. Processing up to is performed.

Finally, the arithmetic processing means outputs the output determined by the pulse density. Specifically, regarding the logical sum result of the two groups, "1" is output when only the logical sum result of the excitatory group is "1", and when only the logical sum result of the inhibitory group is "1". Is logically operated to output "0". When both groups are "1" or when both groups are "0", the output may be "1" or "0", and the probability is 1/2
You may make it output "1" by the degree. For example, when "0" is output when both groups are "0" or "1", one of the logical sums of the two types of coupling is inverted to a negative output, and the logical product of the two is obtained by the logical operation means. By taking the value, the result in which the excitatory connection and the inhibitory connection are added can be obtained. Further, when both groups output “1” when “0” or “1”, one of the logical sums of the two types of coupling is inverted to the negative output, and the logical sum of the two is obtained by the logical operation means. By taking the value, the result in which the excitatory connection and the inhibitory connection are added can be obtained.

As described above, since all the digital processing, particularly the signal processing by the pulse density expression, does not cause the inconvenience of the analog method such as the influence of the temperature characteristic of the amplifier. Further, since the coupling coefficient is also prepared in the memory, it can be rewritten and has versatility unlike the case of using a resistor or the like. In this way, it is possible to realize a neural network whose operation is stable and which has a simple circuit configuration such as a logic circuit and in which the number of nerve cell mimicking units with an extremely high calculation speed is on the order of several thousands.

Embodiment An embodiment of the present invention will be described with reference to FIGS. 1 to 11. 1 to 3 each show a single structure of one i-th nerve cell mimicking unit 11, and FIG. 1 is a nerve cell mimicking unit corresponding to the invention of claims 6 and 7, FIG. Shows an example of a nerve cell mimicking unit corresponding to the inventions of claims 4 and 5, and FIG. 3 shows an example of a nerve cell mimicking unit corresponding to the inventions of claims 8 and 9.

In the case of FIG. 1, the nerve cell mimicking unit 11 has a plurality of input lines (first and second input lines) 12a _j , 12b _j divided into two groups a and b for excitability and inhibitory property, and inputs. Shift register 13a as a memory (first and second memories) of at least 2 bits or more, which is separately provided for each and stores the coupling coefficient T _ij
j , 13b _j , a reading means (not shown) for sequentially reading the contents (coupling coefficient) stored in these shift registers 13 in synchronization with a synchronization clock, and the read contents of the shift register 13. AND gates 14a _j , 14b as a logical product means (first and second logical operation means) for sequentially calculating a logical product with the input contents
_j , two OR gates 15a and 15b as logical sum means (third and fourth logical operation means) for sequentially calculating logical sums of a plurality of logical product results for each group, and an OR gate 15a for one group AND gate (logical operation means) 1 for sequentially calculating the logical product of the logical sum output of the above and the logical output of the OR gate 15b for the other group and the negation by the inverter 16
It is formed by 7 and. Where inverter 16 and AND
A logical operation means (output means) 18 is constituted by the gate 17. Further, the AND gate 14, the OR gate 15, and the logical operation means 18 constitute the arithmetic processing means 19 according to the present invention.

In the case of FIG. 2, the nerve cell mimicking unit 11 has a plurality of input lines 20 _ij and a coupling coefficient provided individually for each input.
Of the shift register 21 _ij and the 1-bit memory 22 _ij as a memory (first and second memories) of at least 3 bits, which stores T _ij and 1-bit information for grouping, and a memory 22 _ij for grouping. Read-out means (not shown) for sequentially reading out the contents of these shift registers 21 _ij except for 1-bit information, and AND means for sequentially calculating the logical product of the read-out contents of the shift register 21 _ij and the input contents. (First
AND gate 23 _ij as a logical operation means) and memory 22 _ij
Switching logic circuit (2nd and 3rd logic operation) by AND gates 24a _ij and 24b _ij (inverter 25b _ij intervenes for one group) that divides the input into two groups of excitatory and inhibitory according to the 1-bit information in Means) and a logical sum means for sequentially calculating the logical sum of the results of a plurality of logical products for each group (first
4, OR gates 15a and 15b as logic operation means),
AND which sequentially calculates the logical product of the logical sum output of the OR gate 15a for one group and the negation of the logical sum output of the OR gate 15b for the other group by the inverter 16
It is formed by the gate 17 (logical operation means). Also in this case, AND gates 23 and 24, inverter 25, and OR gate 1
5. The logical processing means 18 constitutes the arithmetic processing means 27 according to the present invention.

In the case of FIG. 3, the nerve cell mimicking unit 11 is provided with a plurality of input lines 28 _ij and a memory (first and second memories) each of which is provided with two sets for each input and stores the coupling coefficient T _ij. Shift registers 29a _ij , 29b _ij , reading means (not shown) for sequentially reading the contents of these shift registers 29a _ij , 29b _ij , and the read contents and input contents of the shift registers 29a _ij , 29b _ij. AND means for sequentially calculating the logical product of
AND gates 30a _ij and 30b _ij as (2 logic operation means), and a logical sum that sequentially calculates the logical sum of the results of a plurality of logical ANDs output from these AND gates 30a _ij and 30b _{ij for} each group divided into groups. Two OR gates 15a and 15b as means (third and fourth logical operation means), and an inverter 16 of a logical sum output of logical sum outputs of the OR gate 15a for one group and the OR gate 15b for the other group It is formed by an AND gate 17 (logical operation means) that sequentially calculates a logical product with negation. In this case as well, the AND gate 30, the OR gate 15, and the logical operation means 18 constitute the arithmetic processing means 31 according to the present invention. That is,
Two sets of coupling coefficients are prepared for one input by the shift registers 29a _ij and 29b _ij . In this case, the contents of the shift registers 29a _ij and 29b _ij may be different, but in the present embodiment, one shift register 29a _ij stores the excitatory junction coefficient T _ij and the other shift register 29b _ij. The inhibitory coupling coefficient T _ij is stored in.

In any of these configurations, the logical operation means (output means) 18 is configured to use an OR gate 32 as the logical operation means instead of the AND gate 17 as shown in FIG. You may take the logical sum with.

In any of the circuit configurations, in the present embodiment method, all the input / output signals are binarized and synchronized. For example, it is a binary value of "1" and "0".
The amount of a signal of a certain input j is represented by a pulse density, and is represented by, for example, the number of states of “1” within a certain fixed period. FIG. 5 is a diagram showing a signal that represents a synchronization clock and information of 0.5. There are 5 "1" and 5 "0" as input signals in 10 synchronization pulses. This time,
It is desirable that the arrangement of "1" and "0" is random.

On the other hand, the coupling coefficient T _ij is similarly expressed by pulse density,
A bit string of "0" and "1" is prepared in advance in the memory (shift registers 13, 19, 29). For example, "1001
"010110" represents 0.5, but at this time, it is desirable that the arrangement of "0" and "1" be random as in the input (how to specifically determine will be described later). Such binary bit strings are sequentially read from the memory (shift registers 13, 19, 29) according to the synchronous clock, and AND gates 14, 23 or
The logical product of 30 and the input pulse train is obtained. As a result, a nerve cell mimicking unit that is a certain i-th nerve cell
Define the input to 11. That is, to explain using the above example, as shown in FIG. 6, when the input signal is “1010001011”, the coupling coefficient T _ij is read from the memory in synchronization with this.
The bit string "1001010110" of is called and the logical product is sequentially obtained, and the result "1000000010" is obtained.
It shows that V _ij is transformed by the coupling coefficient T _ij and the pulse density becomes 0.2. This part approximately means that the output pulse density is the product of the pulse density of the input signal and the pulse density of the coupling coefficient T _ij , and has the same function as the analog coupling coefficient. This is a function closer to the product as the signal sequence is longer and the arrangement of "1" and "0" is more random. When the pulse train of the coupling coefficient T _ij is shorter than the input pulse train and there is no data to be read, it returns to the beginning of the data again,
The reading may be repeated.

By the way, since one nerve cell mimicking unit 11 has multiple inputs, there are also many logical products of the above-mentioned input signal and the coupling coefficient T _ij. Therefore, the OR gate 15 calculates the logical sum of these. At this time, since the respective inputs are synchronized, for example, if the first data is "1000000010" and the second data is "0110100100", the logical sum of both is "1110100110" as shown in FIG. Become. This is calculated for multiple inputs at the same time and used as the output. The processing of this part corresponds to the calculation of the sum in the analog calculation and the processing of the part of the non-linear function (sigmoid function). When the pulse density is low, the pulse density of the logical sum thereof approximately matches the sum of the pulse densities. As the pulse density increases, the output of the logical sum gradually becomes saturated, so the result does not match the sum of the pulse densities, and nonlinearity appears. In the case of OR, the pulse density will never be greater than 1, and
It does not become smaller than 0, and is monotonically increasing, and is approximately the same as the sigmoid function.

In addition, the coupling has excitability and inhibitory property, and in the case of numerical calculation, it is represented by the positive / negative sign of the coupling coefficient, and in the case of an analog circuit, the coupling coefficient T _ij becomes negative (inhibitory coupling). The output is inverted using an inverting amplifier and is coupled to other nerve cells with a resistance value equivalent to T _ij . In this respect, in the digital system of the present embodiment, first, each coupling is divided into two groups, an excitatory coupling and an inhibitory coupling, _depending on whether the coupling coefficient T _ij is positive or negative. The calculation up to the part that takes the logical sum with the pulse train is performed for each group, and then, only when the output of the excitatory coupling group is “1” and the output of the inhibitory coupling group is “0”, the neuronal cell mimicking unit 11 Output from "1"
Should be issued. In order to realize this function, as shown in FIG. 8, the logical product of the negation of the output of the inhibitory coupling group and the output of the excitatory coupling group may be taken. This makes it possible to realize both excitatory coupling and inhibitory coupling even if they are digital. In the figure, the shift register 13, 21 or 29 is used as the memory, but a commercially available memory and controller may be combined.

At this time, excitatory coupling and inhibitory coupling are divided into two groups in advance at the input stage of the input lines 12a _j , 12b _j , and which input is which coupling is fixed in advance and the logical product is calculated for each group. The method shown in FIG. 1 is such that the logical sum calculation is performed. In addition, 1-bit information representing excitatory coupling and inhibitory coupling is separately prepared in the memory 22 (either coupling may be “0” or “1”), and it is configured to be switchable according to the content of the memory 22. Is the method shown in FIG. Regarding this switching function, for example, as shown in FIG.
It can be easily realized by a logic circuit such as 25 and AND gate 24, and can also be configured by using a relay or the like. Further, in the system shown in FIG. 3, two sets of memories for storing coupling coefficients indicating excitatory coupling and inhibitory coupling are prepared for each input.

Alternatively, as shown in FIG. 4, the OR gate 32 may be used as the logical operation means 18, and both groups may output "1" when "0" or "1".

The above description is about the nerve cell mimicking unit 11 alone, but it is necessary to provide a plurality of nerve cell mimicking units 11 to form a network in order to actually function. For this purpose, for example, as shown in FIG. 9, a hierarchical network structure is used, and the output of a certain nerve cell mimicking unit 11 is connected to the input of each nerve cell mimicking unit 11 in the next layer. And if the whole network is synchronized, it is possible to calculate with the same function one after another.

By the way, the coupling coefficient in such networks
The method of _obtaining T _ij will be described. FIG. 10 shows a nerve cell model (McCulleau, Pitts model) that has been often used in conventional numerical calculation, and the backpropagation method may be applied by considering the network of this model. First,
The layer configuration is the same as that of the digital circuit (the number of layers, the number of neurons in each layer), and the input is an analog value of 0 to 1. The coupling coefficient is "positive" for excitability and "negative" for inhibitory properties, and the equation y _j = f (Σx _i T _ij ) f (x) = 1 / (1 + e ^-x ) ...... ( 1) is used to calculate. This is sequentially calculated for each layer of the network to obtain the final output. The coupling coefficient is randomly selected at first. Given an input, we get some output y _i , so compare this to the desired output t _i , The coupling coefficient T _ij is recalculated based on the following equation. After repeating this several times, the desired output will be obtained when given an input. This operation is performed on a computer in advance, the coupling coefficient T _ij is calculated, and this is converted into a pulse density. At this time, the pulse train preferably has random pulse intervals as described above. To obtain the pulse train from the analog value, for example, a random number is generated in the computer and compared with the analog value. If the random number is larger, the value is "1", and if the random number is smaller, the value is "0". A desired pulse train is obtained by repeating the above procedure several times. The pulse train thus obtained is stored directly in a memory (shift register
13,21,29) to be stored above.

The method of _obtaining the coupling coefficient T _ij may be as follows. That is, in the case of a hierarchical network, the coupling coefficient T _ij is determined using the following equation. At this time, initially, the coupling coefficient T _ij is randomly determined.

a. From the output obtained in the final output layer and the ideal output,
Calculate the error signal δ.

When the error is expressed by a numerical value, generally, both positive and negative values can be taken. However, since such an expression cannot be made by the pulse density, a signal representing a + component and a signal representing a − component are 2
Shall be used to represent the error signal. That is, assuming that the output is y and the ideal output is d, δ ⁺ ≡ (y XOR d) AND d δ ⁻ ≡ (y XOR d) AND y (3) b. The coupling coefficient T _ij is calculated from this error signal δ. Newly asked. That is, From the error signal of ca, the error signal used for the calculation in the previous layer is obtained.

GP _i = δ ⁺ _i ∩T _ij , GM _i = δ ^- _i ∩T _ij (T = excitability) GP _i = δ ^- _i ∩T _ij , GM _i = δ ⁺ _i ∩T _ij (T = inhibitory) (5) d. Find the error signal in the previous layer.

Perform the same calculation as eb, c.

f. Calculate d and e in the previous layer, and repeat the same calculation until the first layer.

Such calculation is repeated many times until the output y becomes the ideal output d, and finally the coupling coefficient T _ij is obtained. This is obtained on a computer, and the obtained pulse train is stored in the memory (shift registers 13, 21, 29) as it is.

On the other hand, the input data is generally an analog value, so to convert this into a pulse train, a random number is generated by a random number generator as in the above case, and this is compared with the input data to determine the magnitude. The desired one is obtained by generating "1" or "0". Further, the output is also output in the form of a pulse train, which can be obtained as a value corresponding to the pulse density by using a counter or the like. Further, depending on the application, the pulse train output may be used as it is.

The method of expressing and processing a signal by pulse density as in the present embodiment is useful not only for actual circuits but also for simulation on a computer. That is, the calculation is performed serially on the computer, but compared with the calculation using the analog value, only the binary logical calculation of "0" and "1" is performed, so the calculation speed is significantly improved. Become. In general,
A real-valued four arithmetic operation requires many machine cycles for one calculation, but the number of arithmetic operations required by the logical operation as in this embodiment is small. In addition, it has an advantage that a low-level language for high-speed processing can be easily used if only logical operations are performed.

Now, a specific example of the configuration example of the nerve cell mimicking unit 11 shown in FIG. 2 will be described. First, the shift register 21 for 128 bits is used as the coupling coefficient for each input. The contents should be rotated and used. Further, in order to distinguish between excitability and suppressiveness, a 1-bit memory 22 is provided for each input, and when it is "1", it is suppressive and when it is "0", it is excitable. With such a unit structure,
The network was configured as shown in the figure. Here, it has a three-layer structure. In the figure, the first layer on the input side is composed of 256, the second layer in the middle is composed of four, and the third layer on the output side is composed of five nerve cell mimicking units 11. In such a three-layer structure, the first and second
The input and output of the units are all coupled between the layers and between the second and third layers.

In this specific example, a handwritten character is input and character recognition is performed on such a network. The coupling coefficient (contents of the shift register 21) for this purpose was obtained by computer simulation as follows. First,
Characters as shown in FIG. 11 were read by a scanner and divided into 16 × 16 meshes, a mesh having a character portion was set to a pulse density “1”, and a mesh having no character portion was set to a pulse density “0”. this
256 pieces of data were input to the network, and the position of the output having the largest output among the outputs of the nerve cell mimicking unit 11 of the third layer having 5 outputs was set as the recognition result. Therefore, when a number from "1" to "5" is input, learning is performed so that the output of the number corresponding to the number becomes the largest. Specifically, each coupling coefficient, excitatory coupling, and inhibitory coupling were determined by the following procedure. First, the same network configuration as this embodiment, that is, the first, second, and third
A network having 256, 4, and 5 units each is prepared on a computer simulation, and the same input signal as that described above is input. Initially, if each coupling coefficient is made random, the output result is not always the desired one. Therefore, each coupling coefficient is newly obtained by using the above-mentioned equation (2), and this is repeated several times so that a desired output can be obtained. The absolute value of the coupling coefficient thus obtained was converted into a pulse density by the procedure described above, and the result was written in the shift register 21. Also,
Since the sign of the coupling coefficient indicates the excitability and the inhibitory property, this was written in the memory 22. Here, since the input is "0" or "1", the input pulse train is always L level or H level, and the random number generator as described above is not particularly necessary. Also, the final output from the third layer is
The LED is connected through a transistor so that the LED is turned off when the L level is output and is turned on when the H level is output. Also, since the frequency of the synchronization clock is set to 1000 kHz, the brightness of the LED will change to the human eye depending on the pulse density, and the brightest LED part will be the answer. As a result of recognizing the characters sufficiently learned by the computer simulation by this circuit, the same result as the computer simulation was obtained.

As a different concrete example, as shown in FIG. 9, the network is configured to have a three-layer structure as shown in FIG. 9. The first layer on the input side is 256, the second layer in the middle is 20, and the output is The third layer on the side was made up of five nerve cell mimicking units, the characters as shown in FIG. 11 were read by a scanner, the computer simulation learning was carried out in the same manner to obtain the coupling coefficient, and the coupling coefficient was written in the shift register 29. Here, since each coupling coefficient has excitatory and inhibitory properties, the excitable one is correspondingly selected from the two sets,
Only the shift register 29a side is written, and the suppressive one is written only to the shift register 29b side. As a result of recognition performed by such a circuit, the same result as the computer simulation was obtained.

EFFECTS OF THE INVENTION Since the present invention is configured as described above, since it is entirely digital processing, there is no problem of being affected by the temperature characteristics of the amplifier as in the analog system, and stable operation can be performed. Also, since the coupling coefficient is also prepared in the memory, it is rewritable and versatile, unlike the case where the resistance value is used, and the circuit configuration is simplified by a logic circuit or the like. It is possible to realize a neural network with an order of several thousands of neural cell mimicking units. In particular, since a signal based on pulse density expression is handled, it is simple to simulate the circuit function on a computer. Because of the binary processing, the calculation speed is high and it is suitable for low-level languages suitable for high-speed calculation.

[Brief description of drawings]

1 to 11 show an embodiment of the present invention.
1 is a block diagram showing a unit configuration of the invention of claims 6 and 7, FIG. 2 is a block diagram showing a unit configuration of the invention of claims 4 and 5, and FIG. 3 is a diagram of claims 8 and 9 4 is a block diagram showing a unit configuration of the invention of FIG. 4, FIG. 4 is a block diagram showing a modified example, FIGS. 5 to 8 are timing charts of pulse trains showing operation, FIG. 9 is a conceptual diagram showing a network configuration, and FIG. FIG. 11 is a schematic diagram of a nerve cell model, FIG. 11 is an explanatory diagram, and FIGS. 12 and 13 are circuit diagrams showing a conventional example. 11 …… Nerve cell mimicry unit, 12,20,28 …… Input line, 1
3,21,22,29 …… Memory, 14,23,30 …… AND product, 15…
... OR means, 18 ... Logic operation means, 19,27,31 ... Logic operation processing means

Claims (12)

(57) [Claims] 1. A nerve cell mimicking network comprising a plurality of nerve cell mimicking units for processing inputs defined by pulse density, wherein each nerve cell mimicking unit comprises a plurality of input lines and for each input. Memories individually provided to store the junction coefficient determined by the pulse density, reading means for sequentially reading the contents of these memories, and digitally processing the read contents of the memory and the input contents. And an arithmetic processing means for outputting each as a binarized output determined by the pulse density, and the output of a certain nerve cell mimicking unit is coupled to the input of self or another nerve cell mimicking unit. A neural cell mimicking network. 2. The neural cell mimicking network according to claim 1, wherein the arithmetic processing means is a logical arithmetic processing means. 3. A nerve cell mimicking unit for processing a plurality of input signals and outputting a nerve cell mimicking output signal representing a processing result, wherein a plurality of input signals represented by a signal amount according to pulse density are received. An input line, a memory for storing a coupling coefficient determined by a pulse density, a logical product of the input signal received from the input line and a coupling coefficient read from the memory corresponding to the input line is input line. A first logical operation means for each operation, a second logical operation means for inputting an excitatory signal from the first logical operation means to perform a logical operation, and a suppression type signal from the first logical operation means, respectively. A third logic operation means for inputting and performing a logic operation, and a fourth logic operation means for synthesizing output signals of the second logic operation means and the third logic operation means and outputting a nerve cell mimicking output signal. A neuron mimicking unit characterized by 4. A nerve cell mimicking network comprising a plurality of nerve cell mimicking units for processing inputs defined by pulse density, wherein each nerve cell mimicking unit is provided with a plurality of input lines and for each input. A memory of at least 3 bits, which is separately provided and stores the coupling coefficient determined by the pulse density and the 1-bit information for grouping, and the contents of these memories except the 1-bit information for grouping Reading means for sequentially reading, logical product means for sequentially calculating the logical product of the read contents of the memory and input contents, and a logical sum of the results of a plurality of logical products for grouping in the memory The logical sum means for sequentially calculating the groups divided by the 1-bit information and the logical operation means for performing logical operation processing on the operation results of the groups and outputting the result. Forms, nerve cell mimics circuitry is characterized in that by coupling the output of one neuron mimetic unit to the input of the self or other nerve cells mimicking unit. 5. A nerve cell mimicking unit for processing a plurality of input signals and outputting a nerve cell mimicking output signal representing the processing result, wherein a plurality of input lines for receiving the input signals and each input line are provided. A first memory for storing a corresponding coupling coefficient; and group information for indicating, for each input line, which group of the excitatory group and the inhibitory group the input line corresponds to And a second memory for performing the logical product of the input signal received from the input line and the coupling coefficient read from the first memory corresponding to the input line for each input line. Means for calculating the logical product of the group information read from the second memory and the logical product output from the first logical operation means for each input line; and the second logical operation means. From memory Third logical operation means for calculating the logical product of the inversion information of the group information issued and the logical product output from the first logical operation means, and output from these second logical operation means. Fourth logical operation means for calculating the logical sum of the logical products, fifth logical operation means for calculating the logical sum of the logical products output from these third logical operation means, and from the fifth logical operation means An inverter for inverting the output logical sum, and a logical operation means for calculating the logical product or logical sum of the output of this inverter and the logical sum output from the fourth logical operation means A neural cell mimicking unit, comprising: 6. A nerve cell mimicking network comprising a plurality of nerve cell mimicking units for processing an input determined by pulse density, wherein each nerve cell mimicking unit is provided with a plurality of input lines divided into two groups. A memory having at least 2 bits or more, which is individually provided for each input and stores a coupling coefficient determined by the pulse density, a reading means for sequentially reading the contents of these memories, and a memory for reading the memory. A logical product means for sequentially calculating the logical product of the contents and the input contents, a logical sum means for sequentially calculating the logical sum of the results of a plurality of logical products for each group, and a logical operation process for the operation results for each group It is characterized in that the output of a certain nerve cell mimicking unit is coupled to the input of self or another nerve cell mimicking unit. Nerve cells mimic circuit network. 7. A nerve cell mimicking unit for processing a plurality of input signals and outputting a nerve cell mimicking output signal representing a processing result, and a plurality of first input lines for receiving a first input signal, A plurality of second input lines for receiving the second input signal, and a first for storing a coupling coefficient corresponding to each of the first input lines.
A memory and a second for storing a coupling coefficient corresponding to each second input line
A first logic for calculating, for each first input line, a logical product of a memory, the first input signal received from the first input line, and a coupling coefficient read from the first memory corresponding to the first input line. Second calculating means calculates a logical product of the second input signal received from the second input line and the coupling coefficient read from the second memory corresponding to the second input line for each second input line. A logical operation means, a third logical operation means for calculating a logical sum of logical products output from these first logical operation means, and a logical sum of logical product output from these second logical operation means And a logical product of the inverter output and the logical sum output from the third logical calculation means. Logical operation means for calculating the sum Neurons mimicking unit, characterized in that an output means for outputting the more become neurons mimic output signal. 8. A nerve cell mimicking network comprising a plurality of nerve cell mimicking units for processing inputs defined by pulse density, wherein each nerve cell mimicking unit comprises at least a plurality of input lines and for each input. And a memory for storing the coupling coefficient determined by the pulse density, the reading means for sequentially reading the contents of these memories, and the logical product of the read contents of the memory and the input contents. And a logical sum means for sequentially calculating the logical sum of the results of a plurality of logical products for each group that can be divided into groups of the memory, and a logical operation processing of the operation results for each group and outputting A neural cell mimicking unit that is coupled to the output of one neuron mimicking unit or the input of another neuron mimicking unit. Imitation circuit network. 9. A nerve cell mimicking unit for processing a plurality of input signals and outputting a nerve cell mimicking output signal representing a processing result, wherein a plurality of input lines for receiving the input signals are provided, each corresponding to each input line. For storing each coupling coefficient
A memory and a second memory; first logical operation means for calculating, for each input line, a logical product of the input signal received from the input line and the coupling coefficient read from the first memory corresponding to the input line; Second logical operation means for calculating the logical product of the input signal received from the input line and the coupling coefficient read from the second memory corresponding to the input line, and output from the first logical operation means. A third logical operation means for calculating a logical sum of the logical products, a fourth logical operation means for calculating a logical sum of the logical products output from the second logical operation means, and a fourth logical operation And a logical operation means for calculating a logical product or a logical sum of the output of the inverter and the logical sum output from the third logical operation means. Neurons mimicking unit, characterized in that an output means for outputting a force signal. 10. The input signal and the coupling coefficient are represented by a signal amount based on a pulse density.
The nerve cell mimicking unit according to 5, 7, or 9. 11. A coupling density is represented by a pulse density defined by at least one of the number of first values and the number of second values randomly arranged within a predetermined time. Claim 3 or 10 characterized in that
The described neuronal cell mimicking unit. 12. A plurality of nerve cell mimicking units forming a hierarchical structure having a plurality of layers, and outputs of any nerve cell mimicking unit of a layer having a hierarchical structure to any nerve cell of another layer of the hierarchical structure. A plurality of signal lines coupled to an input of a mimicking unit and a part of the neuron mimicking unit for processing a plurality of input signals and outputting a neuron mimicking output signal representing the processing result. A nerve cell mimicking network comprising the nerve cell mimicking unit according to 5, 7, or 9.