JPH04322360A - Signal processing electric network - Google Patents

Abstract

PURPOSE:To improve the general usefulness and the processing capability by preventing the digital signals obtained from the last output layer of a neural network in the digital system from being limited to pulse density expression signals. CONSTITUTION:A neural model in the digital system like a hierarchical network is used as the base, and a counting and comparing circuit 39 is provided which counts an output 26E obtained from the output circuit of a circuit unit placed in the last output layer by a counter 37 and compares the counted value with a preliminarily set prescribed value by a comparator 38, and a selective output circuit 42 which outputs different information in accordance with the comparison result is provided, and a reset circuit 52 is provided which resets the counted value of the counting and comparing circuit 39 in another circuit unit to prescribed value 'O' in accordance with the comparison result.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a signal processing circuit for a neural computer that imitates neurons.

0002

[Prior Art] The function of nerve cells (neurons), which are the basic unit of information processing in living organisms, is imitated, and this
The so-called neural network is a network of "neuron mimicking elements" that aims to process information in parallel. There are many things, such as character recognition, associative memory, and interlocking control, that are easily accomplished in living organisms, but are difficult to achieve with conventional von Neumann computers. biological nervous system,
In particular, many attempts are being made to solve these problems by imitating functions unique to living organisms, such as parallel processing and self-learning. Many of these attempts have been carried out using computer simulations, and parallel processing is required to achieve the original functionality, and for this purpose it is necessary to implement neural networks in hardware.

[0003] Among these, there is one as shown in FIG. 13 as an example of one realized by an electric circuit. This is disclosed in Japanese Patent Application Laid-Open No. 62-295188, and basically includes a plurality of amplifiers 1 having an S-shaped transfer function,
A resistive feedback network 2 is provided which connects the output of each amplifier 1 to the input of the amplifiers of the other layer as shown by the dash-dotted lines. A CR time constant circuit 3 consisting of a grounded capacitor and a grounded resistor is individually connected to the input side of each amplifier 1. And input currents I1, I2,
~, IN are applied to the input of each amplifier 1, and the output is obtained from the set of output voltages of these amplifiers 1.

Here, the strength of the connection between neurons is expressed by the resistance value of the resistor 4 (lattice point in the resistive feedback network 2) that connects the input/output line between each cell, and is expressed by the neuron response function. is expressed by the transfer function of each amplifier 1. Furthermore, as is well known, there are excitatory and inhibitory connections between neurons, which are mathematically expressed by the positive and negative signs of the connection coefficient. However, it is difficult to realize positive and negative signals using constants on the circuit, so here we divide the output of amplifier 1 into two and invert one output to generate two positive and negative signals.
This is achieved by making appropriate selections.

[0005] Also, FIG.
This figure shows the content proposed in the publication, and is an improved version of the one shown in FIG. This is a simplified circuit based on mathematical analysis, using a negative gain amplifier 5 with a single output instead of the amplifier 1, and a clipped T-matrix circuit 6 instead of the resistive feedback network 2. It was constructed using

In any case, these circuits are basically of an analog type. That is, the input/output amount is expressed by a current value or a voltage value, and all internal arithmetic processing is performed in an analog manner. However, in the case of the analog method, it is difficult to operate accurately and stably due to, for example, the temperature characteristics of the amplifier, drift after power-on, and the like. In particular, in the case of a neural network, the number of amplifiers required is at least several hundred, and the stability of the operation is important because it performs nonlinear operation. Furthermore, it is not easy to change circuit constants such as resistance values, and the device lacks versatility.

[0007]

[Problem to be solved by the invention] From the above,
For example, a digital representation of a neural network is published in the Institute of Electronics, Information and Communication Engineers Technical Research Report, ICD88-130.
It is reported in ``Configuration of a Completely Digital Neurochip'' in . However, this is an emulation of the conventional analog system, and the circuit is somewhat complex, including the use of up/down counters.

In order to solve these drawbacks, a digital neuron model was proposed by the applicant in Japanese Patent Application No. 1999-1-1.
No. 79629 has already been proposed, and furthermore, in such a neuron model, a model in which a digital signal obtained from the final output layer is converted into a pulse density and then converted into an analog output as appropriate has also been proposed. but,
According to such a proposed example, the digital signal is limited to being treated as a pulse density, and it lacks versatility or processing ability.

[0009]

[Means for Solving the Problem] According to the invention as claimed in claim 1, in a signal processing circuit network configured to simultaneously process a plurality of binarized information strings, at least two or more inputs and , a reading means for sequentially reading the memory contents from these memories, an AND circuit for calculating the AND of the memory contents sequentially read from the memory and the input information, and an AND circuit for each input. An OR circuit that calculates the OR of all inputs for each of the two groups set in advance for each input for these AND results obtained, and an OR circuit that calculates the OR of all inputs for each of the two groups set in advance for each input, and an OR circuit that calculates the OR of the two sets of OR results obtained by these OR circuits. A plurality of circuit units each having an output circuit that performs a logical operation on the A counting comparison circuit that counts the output obtained from the output circuit of the circuit unit located in the output layer and compares it with a predetermined value set in advance, a selection output circuit that outputs different information depending on the comparison result, and a selection output circuit that outputs different information depending on the comparison result. Accordingly, a reset circuit is provided to reset the count value of the count comparison circuit in the other circuit unit to a predetermined value.

In the invention as claimed in claim 2, the first
A memory and a second memory are provided, and the AND circuit calculates the AND of the memory contents sequentially read from the first memory and the input information for each input, and the OR circuit calculates the AND of the input information obtained by the AND circuit. Regarding these logical product results, the second
The logical sum of all inputs shall be calculated for each content of the memory, and the output circuit shall perform a logical operation on the logical sum results for each content obtained by these logical sum circuits and output it.
Furthermore, similarly to the invention described in claim 1, a count comparison circuit, a selection output circuit, and a reset circuit are provided for the output circuit of the final output layer.

[0011] In the invention according to claim 3, the first
In addition to providing a memory and a second memory, there is also a first AND circuit that calculates the AND of the memory contents sequentially read from the first memory and the input information for each input, and a first logical sum circuit that calculates the logical sum of all inputs for the logical product results of the logical product, and a second logical product circuit that calculates the logical product of the memory contents sequentially read from the second memory and the input information for each input. , and a second logical sum circuit that calculates the logical sum of all inputs for these logical product results obtained by the second logical product circuit, and further, as in the invention as claimed in claim 1, a final output layer is provided. A count comparison circuit, a selection output circuit, and a reset circuit are provided for the output circuit.

In the invention according to claims 4 to 6, in the invention according to claims 1 to 3, when the two sets of OR results obtained by the OR circuit do not match, the output circuit is switched to the predetermined set. When they match, the logical product result of the above input and another external input or another memory provided in association with this external input and this external input is output.

[0013]

[Operation] Since both systems are based on digital systems, problems such as temperature characteristics and drift that occur with analog systems are eliminated. Furthermore, since the information of the coupling coefficient is stored in the memory, it is easy to rewrite and change, making the device highly versatile. Here, the output obtained from the output circuit of the unit circuit located in the final output layer is counted by the counting comparison circuit and compared with a predetermined value set in advance, and depending on the comparison result, different information is outputted by the selected output circuit. On the other hand, since the reset circuit resets the count value of the count comparison circuit in other circuit units to a predetermined value according to the comparison result, the output is not limited to what is treated as pulse density, making it more versatile and A digital signal output with high processing capacity can be obtained.

[0014]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described with reference to FIGS. 1 to 12. First, basically, input/output signals, intermediate signals, coupling coefficients, etc. regarding the circuit unit forming each neuron,
It is assumed that all teacher signals and the like are represented by binary pulse trains of "0" and "1". All these signals are synchronized. Now, if the i-th input is yi, the intensity of the signal of input yi is expressed by pulse density, for example, as shown in Figure 2.
As in the pulse train shown in
” is expressed as the number of states. That is, the example in FIG. 2 represents 4/6, and the signal has four "1"s and "1" among six synchronizing pulses.
0" are two. At this time, it is desirable that the arrangement of "1" and "0" is random, as will be described later.

On the other hand, the coupling coefficient Tij, which indicates the degree of coupling between neurons, is similarly expressed in terms of pulse density, and is prepared in advance in the memory as a pulse train of "0" and "1". The example shown in FIG. 3 represents "101010"=3/6. In this case as well, it is desirable that the ``1''s and ``0'' be arranged randomly. The specific method for determining this will be described later.

[0016] Then, these pulse trains are sequentially read out from the memory in accordance with the synchronization clock, and the logical AND of each pulse train with the input signal pulse train is calculated (yi ∩ Tij). This is the input to neuron j. To explain in the case of the above example, when the input signal is input as "101101", by reading the pulse train from the memory in synchronization with this and performing the AND operation sequentially, "101000" as shown in FIG. 4 is obtained. This shows that the input yi is transformed by the coupling coefficient Tij and the pulse density becomes 2/6.

The pulse density resulting from such a logical product is approximately the product of the pulse density of the input signal and the pulse density of the coupling coefficient, and has the same function as the coupling coefficient of the analog system. This means that the longer the signal train is, the more
The more random the arrangement of and "0" is, the closer the function is to a product. Note that when the pulse train of the coupling coefficient is shorter than the input pulse train and there is no more data to be read, it is sufficient to return to the beginning of the data and repeat the reading.

Here, since one neuron unit has multiple inputs, there are also many "AND results of input signals and coupling coefficients", and then the OR circuit calculates the OR of these results. The inputs are synchronized, so for example, the first data is "101000" and the second data is "010000".
In this case, the OR of the two results in "111000". This is calculated simultaneously with multiple inputs (the number of inputs is m) and output. That is, it becomes as shown in FIG. This corresponds to the sum calculation and nonlinear function (sigmoid function) part in analog calculation.

When the pulse density is low, the pulse density obtained by taking their logical sum approximately matches the sum of the respective pulse densities. As the pulse density increases, the output of the OR circuit gradually becomes saturated, so it does not match the sum of the pulse densities and nonlinearity appears. In the case of logical sum, the pulse density never becomes larger than 1 or smaller than 0, and furthermore, it is a monotonically increasing function and is approximately similar to a sigmoid function.

By the way, coupling has excitatory and inhibitory properties, and in the case of numerical calculations, it is expressed by the sign of the coupling coefficient, and in the case of analog circuits, as mentioned above, when Tij is negative (inhibitory coupling), The output is inverted using an amplifier and coupled to other neurons with a resistance value corresponding to Tij. In this regard, in this embodiment of the digital method, the pulse density is always positive, but if one of the following three methods is used, even if the coupling coefficient is expressed as a pulse density, the excitement of the coupling can be reduced. It becomes possible to deal with sexual and restraint.

First, a configuration corresponding to claims 1 and 4 is shown in FIG. Here, whether each bond is excitatory or inhibitory is set in advance, and the above-mentioned logical sum is calculated separately for the excitatory bond group and the inhibitory bond group. Alternatively, whether each input is excitatory or inhibitory is set in advance, and the excitatory input group and the inhibitory input group are logically ORed separately. For example, as shown in FIG. 6, at the input stage, the inputs are grouped in advance into an excitatory connection group 11a and an inhibitory connection group 11b, and memories 13a and 13b storing the connection coefficient Tij are provided for each input 12. Bye. The AND gates (AND circuits) 14a and 14b perform the logical product of the input signal and the pulse train of the coupling coefficient Tij. Then, OR gates (logical sum circuits) 15a and 15b perform a logical sum for each group 11a and 11b, and a logical sum result (OR gate 15a output) 16a for the excitatory group 11a.
and the result of the logical sum of the inhibitory group 11b (OR gate 15
b output) 16b is obtained.

On the other hand, a configuration corresponding to claims 2 and 5 is shown in FIG. In this method, each bond has a memory (second memory) 17 indicating whether the bond is excitatory or inhibitory, and a gate circuit 18 arbitrarily controls whether the bond is excitatory or inhibitory depending on the contents of the memory (second memory). Allow settings. By passing through such a gate circuit 18, the excitatory connection group and the inhibitory connection group determined by the contents of this memory 17 are separately ORed by OR gates 15a and 15b, and the logic for each group is calculated. Sum result 16a, 16
get b.

Furthermore, a configuration corresponding to claims 3 and 6 is shown in FIG. In this method, each connection has an excitatory coupling coefficient and an inhibitory coupling coefficient, and as shown in FIG.
Place it on top of 0. This corresponds to decomposing and expressing the coupling coefficient into the sum of a positive quantity and a negative quantity. Then, the AND gate (first AND circuit) 21 calculates the logical products of all the input signals and the excitatory coupling coefficients stored in the memory 19, and the logical sum of the outputs of these AND gates 21 is calculated by the OR gate. (First OR circuit) Taken by 15a. On the other hand, the AND gate (second AND circuit) 2
2, and the OR gate (second OR circuit) 15b calculates the logical sum of the outputs of these AND gates 22. In this way, the excitatory/inhibitory gender disjunction result 1
6a and 16b are obtained.

Next, the logical sum result 1 obtained in this way
6a and 16b are outputted after being subjected to logical operation processing by the output circuit 23. Here, as a process by the output circuit 23, if the logical sum result of the excitatory group and the logical sum result of the inhibitory group do not match, the logical sum result of the excitatory group is output (that is, the logical sum result of the excitatory group is The sum result is “0”
”, if the logical sum result of the inhibitory group is “1”, then “
0", and conversely, the OR result of the excitatory group is "
1” and the logical sum result of the inhibitory group is “0”,
(outputs “1”). Further, when the logical sum results of both groups match, "0" or "1" is output.

The output circuit 23 according to the invention according to claims 1, 2, and 3 for this purpose is configured as shown in FIG. 9 or 10, for example. Figure 9 shows the logical sum result 16b of the inhibitory group.
is passed through an inverter 24, and the logical sum result 16a of the excitatory group is directly inputted to an AND gate 25 to perform a logical product and output as a unit output 26. In FIG. 10, an OR gate 27 is used in place of the AND gate 25 to perform a logical sum.

Further, the output circuit 23 according to the invention according to claims 4, 5, and 6 is configured as shown in FIG. 11, for example. In this method, an input 28 is set separately from the input 12, and a memory 29 is also provided in association with this input.
Taken by 0. And both logical sum results 16a, 16
b is input to an exclusive OR gate 31, and when the two do not match, a predetermined result 16a is output as a unit output 26 through processing by an AND gate 32 and an OR gate 33. On the other hand, when both match, exclusive O
The output inverted by the inverter 34 of the R gate 31 and the output of the AND gate 30 are ANDed by an AND gate 35 and outputted as a unit output 26 via an OR gate 33. Alternatively, when there is a match, the input 28 may be output directly as the unit output 26.

The above explanation is based on the neuron mimicking unit (
Regarding the single circuit unit) 36, in order to actually function, it is necessary to provide a plurality of neuron imitation units 36 to form a network. To do this, for example, as shown in FIG. 12, a hierarchical network structure is created such as an input layer, an intermediate layer, and an output layer (final output layer), and the output of a certain neuron imitation unit 36 is used to imitate each neuron in the next layer. Coupled to the input of unit 36. By synchronizing the entire network, it becomes possible to perform calculations using the same function one after another.

Here, since the data at the input 12 is generally an analog value, in order to convert it into a pulse train, a random number is generated from a random number generator, and this is compared with the input to determine its magnitude. If "1" or "0" is generated by , the desired value can be obtained. On the other hand, the unit output 26 is also output in the form of a pulse train, and its value can be determined using a counter or the like. However, depending on the application, it is also possible to use the pulse train as it is.

Accordingly, in this embodiment, in this prerequisite configuration, the processing of the unit output 26E from the neuron imitation unit 36 located in the final output layer of the network is particularly devised. As mentioned above, the neuron mimicking unit 36 located in the final output layer
The unit output 26E is also output in the form of a pulse train, but in this embodiment, this pulse train is counted and the count OFF output is used as the output of this network until the predetermined value N is reached. After that, the count ON output is used as the output of the network. For example, if N = 8 and the count value for the pulse train is n, the count is OFF from n = 1 to 8 as shown in Figure 1(b).
The output is made a network output, and from the next reference clock when n=8 (=N), the count ON output is made a network output.

FIG. 1(a) shows a circuit configuration for processing the unit output 26E of the neuron imitation unit 36 in the final output layer. First, a counting comparison circuit 39 having a counter 37 and a comparator 38 is provided. It is being The counter 37 counts the number of pulses in the pulse train of the unit output 26E of the final output layer, and sends the result to the comparator 38 as a binary value. Further, the comparator 38 compares a predetermined value N preset and registered in the memory 40 with the count value n obtained from the counter 37,
It outputs output according to its size. This comparison output 41 outputs "0" if n<N, and outputs "1" if n≧N.

A selection output circuit 42 is connected to the output side of the comparator 38. Here, the selection output circuit 4
2, first, a memory 43 storing count OFF outputs and a memory 44 storing count ON outputs are prepared. The memory 43 side is input to an AND gate 46 with an inverter 45 so that it is selected when the comparator 38 output is "0", and the memory 44 side is inputted to an AND gate 46 so that it is selected when the comparator 38 output is "1".
is input to the D gate 47, and these AND gates 46,
The output of 47 is input to an OR gate 48. This O
The output 49 from the R gate 48 corresponds to the output in FIG. 1(b). The output of this OR gate 48 may be the final output 50 of the neuron mimicking unit 36 located in the final output layer. Alternatively, as shown in the figure, the output 49 from the OR gate 48 and the unit output 26E of the final output layer are ANDed by an AND gate 51 (or the OR gate may be used to perform the logical sum), and the The result may be the final output 50. Alternatively, the memories 43 and 44 may be omitted and the final output 50 may be obtained by performing a logical operation on the output 41 of the comparator 38 and the unit output 26E. Furthermore, the output 41 of the comparator 38 may be used as the final output 50.

[0032]The above explanation is for the output of one neuron imitation unit 36 in the final output layer, but the output relationship between these units will now be explained. Figure 1(c) shows, for example, the outputs A and B of the three final output layers.
, C (corresponding to output 26E). First, the number of pulses of each output A, B, and C starts counting from timing T1, and when the count value nA of output A reaches a predetermined value N for the first time, a count ON output is issued. Next, the count value nC of the output C
When reaches a predetermined value N, a count ON output is output, and at the same time output A is set to a count OFF output.
is reset to nA =0. Next, when the count value nB of output B reaches a predetermined value N, output B is set as a count ON output, and at the same time, output C is set as a count OFF output and the counter 37 is reset to nC =0. In this way, the count value of the unit outputs 26E from all the neuron imitation units 36 in the final output layer or the unit outputs 26E from the grouped neuron imitation units 36 in the final output layer reaches the predetermined value N. Only the output that has reached the count output state is set to the count ON output state, and the output that was in the count output ON state until then is reset to the count OFF state. The reset circuit 52 shown in FIG. 1(a) is a circuit for this purpose. First, an OR gate 53 is provided which receives as input the output group 41ALL from the comparator 38 in the other neuron imitation unit 36 located in the final output layer (
Therefore, the output 41 from the own comparator 38 is input to the OR gate in the other reset circuit as one of the output group 41ALL), and the own comparator 38
The signal is input to an exclusive OR gate 54 along with the output 41 from the output 41, and is further input to an AND gate 55. The output of this AND gate 55 is connected to the reset terminal of the counter 37.

As a result, when the count value n reaches the predetermined value N in its own unit and the output 41 is generated from the comparator 38, it enters a standby state waiting for the AND gate 55, and in this state, when the count value n reaches the predetermined value N, the output 41 is generated from the comparator 38. When the count value n reaches the predetermined value N, any one of the output groups 41ALL becomes "1".
”, it matches this output 41, and the output from the exclusive OR gate 54 to the AND gate 55 becomes “1”, the AND gate 55 is opened, and the counter 3
7 will be reset.

Note that the method for resetting the counter 37 is not limited to this; for example, it may be reset at a certain fixed time interval, or by arbitrary input from outside the network as shown at timing T2 in FIG. 1(c). All the neuron imitation units 36 of the final output layer or the grouped neuron imitation units 3 of the final output layer
6 may be reset. In this case, with this as the external input 56, as shown in FIG.
The counter 37 may be configured to be reset via the output of the ND gate 55 and the OR gate 57 selectively. In any case, the reset circuit 52 is not limited to the one shown in the figure, and may be any other circuit as long as it can perform such a function.

By the way, the above-described method of expressing and processing a signal in terms of pulse density is useful not only for actual circuits but also for simulating on a computer. That is,
Calculations are performed serially on a computer, but compared to calculations using analog values, the calculation speed is significantly improved because only binary logical operations of "0" and "1" are performed. Furthermore, in general, real-value arithmetic operations require many machine cycles for one calculation, but logical calculations require fewer machine cycles. Furthermore, the use of only logical operations has the advantage of making it easier to use low-level languages for high-speed processing.

[0036] As for the configuration for realizing the above-described processing, it is not necessary to implement all of it into a circuit, and some or all of it may be performed by software. Further, the circuit configuration is not limited to the one illustrated, and may be replaced with another circuit with equivalent logic, or the above-mentioned logic may be replaced with negative logic.

[0037]

[Effects of the Invention] Since the present invention is configured as described above, all digital processing is performed, so there are no problems such as temperature characteristics, drift, etc. that occur with analog systems.
Stable operation can be achieved, and since the coupling coefficient information is also stored in memory, it is easy to rewrite and change, providing versatility. Regarding the output obtained from the output circuit of the unit circuit, the number of pulses is counted by a counting comparison circuit and compared with a predetermined value set in advance, and depending on the comparison result, different information is output by the selected output circuit. Since the count value of the count comparison circuit in other circuit units is reset to a predetermined value by the reset circuit according to the The network can provide a digital signal output.

[Brief explanation of drawings]

FIG. 1 shows the gist of the present invention, and (a) is a circuit diagram;
(b) and (c) are timing charts.

FIG. 2 is a timing chart showing a pulse train for explaining basic operations.

FIG. 3 is a timing chart showing a pulse train for explaining basic operations.

FIG. 4 is a timing chart showing a pulse train for explaining basic operations.

FIG. 5 is a timing chart showing a pulse train for explaining basic operations.

FIG. 6 is a circuit diagram showing a configuration corresponding to the invention according to claims 1 and 4;

FIG. 7 is a circuit diagram showing a configuration corresponding to the invention according to claims 2 and 5.

FIG. 8 is a circuit diagram showing a configuration corresponding to the invention according to claims 3 and 6;

FIG. 9 is a circuit diagram showing an example of the configuration of an output circuit according to the invention according to claims 1, 2, and 3;

FIG. 10 is a circuit diagram showing another example of the configuration of an output circuit according to the invention according to claims 1, 2, and 3;

FIG. 11 is a circuit diagram showing an example of the configuration of an output circuit according to the invention according to claims 4, 5, and 6;

FIG. 12 is a conceptual diagram showing a network configuration.

FIG. 13 is a circuit diagram showing a conventional example.

FIG. 14 is a circuit diagram showing a conventional example.

[Explanation of symbols]

12 Input 13. Memory 14. AND circuit 15 Logical sum circuit 16 Logical sum output 17 Second memory 19 1st memory 20 Second memory 21 First AND circuit 22 Second AND circuit 23 Output circuit 28 External input 29 Memory 36 Circuit unit 39 Counting comparison circuit 42 Selective output circuit 52 Reset circuit

Claims (6)

[Claims] Claim 1: A signal processing circuit configured to simultaneously process a plurality of binarized information strings, comprising at least two inputs, a memory provided for each input, and memory contents from these memories. an AND circuit that calculates the AND of the memory contents sequentially read from the memory and the input information for each input; It has an OR circuit that calculates the OR of all inputs for each of the two sets set to , and an output circuit that performs a logical operation on the two sets of OR results obtained by these OR circuits and outputs A plurality of circuit units are provided, and the outputs of these circuit units are connected to the inputs of other circuit units or to the own circuit unit side to form a hierarchical network, and the output of the circuit unit located in the final output layer is obtained from the output circuit of the circuit unit located in the final output layer. A counting comparison circuit that counts the output of the output and compares it with a preset predetermined value, a selection output circuit that outputs different information depending on the comparison result, and a counting comparison circuit in other circuit units depending on the comparison result. A signal processing circuit network comprising a reset circuit for resetting a count value to a predetermined value. 2. A signal processing circuitry configured to simultaneously process a plurality of binarized information sequences, comprising at least two or more inputs, a first memory provided for each input, and a second memory provided for each input.
A memory, a reading means for sequentially reading memory contents from these memories, an AND circuit for calculating a logical product of the memory contents sequentially read from the first memory and input information, and a logical product obtained by the logical product circuit. an OR circuit that calculates the logical sum of all inputs for each content of the second memory, and a logical sum circuit that performs a logical operation on the logical sum results of each content obtained by these logical sum circuits. A plurality of circuit units having output circuits are provided, and the outputs of these circuit units are connected to the inputs of other circuit units or to the own circuit unit side to form a hierarchical network, and are located in the final output layer. A counting comparison circuit that counts the output obtained from the output circuit of the circuit unit and compares it with a preset predetermined value, a selection output circuit that outputs different information depending on the comparison result, and other circuits depending on the comparison result. A signal processing circuit network comprising: a reset circuit for resetting a count value of a count comparison circuit in a unit to a predetermined value. 3. A signal processing circuitry configured to simultaneously process a plurality of binarized information strings, comprising at least two or more inputs, a first memory provided for each input, and a second memory provided for each input.
a memory, a reading means for sequentially reading memory contents from these memories, a first AND circuit for calculating a logical product of the memory contents sequentially read from the first memory and input information for each input, and a first logic circuit. A first logical sum circuit calculates the logical sum of all inputs for these logical product results obtained by the product circuit, and a logical product of the memory contents sequentially read from the second memory and the input information is calculated for each input. a second AND circuit,
A second logical sum circuit calculates the logical sum of all inputs for these logical product results obtained by the second logical product circuit, and performs a logical operation on two sets of logical sum results obtained by these logical sum circuits. A plurality of circuit units having an output circuit that outputs a A counting comparison circuit that counts the output obtained from the output circuit of the located circuit unit and compares it with a preset value, a selection output circuit that outputs different information depending on the comparison result, and a selection output circuit that outputs different information depending on the comparison result. A signal processing circuit network comprising: a reset circuit for resetting the count value of the count comparison circuit in the circuit unit to a predetermined value. 4. A signal processing circuitry configured to simultaneously process a plurality of binarized information strings, comprising at least two inputs, a memory provided for each input, and memory contents from these memories. an AND circuit that calculates the AND of the memory contents sequentially read from the memory and the input information for each input; An OR circuit that calculates the OR of all inputs for each of the two groups set to A circuit unit having an output circuit that outputs a sum result, and outputs an AND result of the input and another external input or another memory content provided incidentally to this external input and this external input when they match. A plurality of circuit units are provided, and the outputs of these circuit units are connected to the inputs of other circuit units or to the own circuit unit side to form a hierarchical network, and the output obtained from the output circuit of the circuit unit located in the final output layer. a counting comparison circuit that counts and compares it with a preset predetermined value, and a selection output circuit that outputs different information depending on the comparison result.
1. A signal processing circuit network comprising: a reset circuit for resetting a count value of a count comparison circuit in another circuit unit to a predetermined value according to a comparison result. 5. A signal processing circuitry configured to simultaneously process a plurality of binarized information sequences, comprising at least two or more inputs, a first memory provided for each input, and a second memory provided for each input.
A memory, a reading means for sequentially reading memory contents from these memories, an AND circuit for calculating a logical product of the memory contents sequentially read from the first memory and input information, and a logical product obtained by the logical product circuit. A logical sum circuit calculates the logical sum of all inputs for each content of the second memory for these logical product results, and when the logical sum results obtained by these logical sum circuits do not match, a predetermined an output circuit that outputs the result of the logical sum of the input and another external input, or the contents of another memory provided along with this external input, and this external input when they match; A plurality of circuit units are provided, and the outputs of these circuit units are connected to the input of other circuit units or to the own circuit unit side to form a hierarchical network, and from the output circuit of the circuit unit located in the final output layer. A counting comparison circuit that counts the obtained output and compares it with a preset predetermined value, a selection output circuit that outputs different information depending on the comparison result, and a counting comparison circuit in another circuit unit depending on the comparison result. 1. A signal processing circuit network comprising: a reset circuit for resetting a count value to a predetermined value. 6. A signal processing circuit configured to simultaneously process a plurality of binarized information sequences, comprising at least two inputs, a first memory provided for each input, and a second memory provided for each input.
a memory, a reading means for sequentially reading memory contents from these memories, a first AND circuit for calculating a logical product of the memory contents sequentially read from the first memory and input information for each input, and a first logic circuit. A first logical sum circuit calculates the logical sum of all inputs for these logical product results obtained by the product circuit, and a logical product of the memory contents sequentially read from the second memory and the input information is calculated for each input. a second AND circuit,
When the second logical sum circuit calculates the logical sum of all inputs for these logical product results obtained by the second logical product circuit, and the two sets of logical sum results obtained by these logical sum circuits do not match, Outputs the logical sum result of a predetermined set, and when they match, outputs the logical product result of the input and another external input, or another memory content provided along with this external input, and this external input. A plurality of circuit units having output circuits are provided, and the outputs of these circuit units are connected to the inputs of other circuit units or to the circuit unit side of the circuit unit itself to form a hierarchical network, and the circuit located in the final output layer. A counting comparison circuit that counts the output obtained from the output circuit of the unit and compares it with a preset predetermined value, a selection output circuit that outputs different information depending on the comparison result, and another circuit unit depending on the comparison result. A signal processing circuit network comprising: a reset circuit for resetting a count value of a count comparison circuit therein to a predetermined value.