JPH04229361A - Learning method for neural network and signal processor using the same - Google Patents

Abstract

PURPOSE:To adapt a back-propagation learning rule by adding a learning function to a digital neural network of simple circuit constitution. CONSTITUTION:An error signal regarding a neuron is found in each step of learning and a coupling coefficient T is varied by using the error signal to performs a learning process. The error signal is found first as to the neurons in a final layer and the error signal of this final layer is used to find errors of layers in order toward the front. This learning method can be applied to a neural network wherein differentiation is impossible because of the internal potential of a neural cell response function and a neural network wherein an internal potential itself can not be defined.

Description

[Detailed description of the invention]

0001

[Industrial Application Field] The present invention relates to a neural network learning method for a neurocomputer, which is a parallel distributed information processing device, which aims to artificially realize the information processing function of a neuronal network, and the use of this method. This invention relates to a signal processing device.

0002

[Prior Art] The function of nerve cells (neurons), which are the basic unit of information processing in living organisms, is imitated, and this
The so-called neural network is a network of "neuron mimicking elements" that aims to process information in parallel. Many things, such as character recognition, associative memory, and motor control, are difficult to achieve with conventional von Neumann computers, even though they are easily accomplished in living organisms. biological nervous system,
In particular, many attempts are being made to solve these problems by imitating functions unique to living organisms, such as parallel processing and self-learning, using neural networks. Many of these attempts have been carried out using computer simulations, and parallel processing is required to achieve the original functionality, and for this purpose it is necessary to implement neural networks in hardware. Some attempts have already been made to turn it into hardware, but the self-learning function, which is one of the characteristics of neural networks, has not been realized, which has been a major bottleneck. Furthermore, most of them are implemented using analog circuits, which poses problems in terms of operation, as will be described later.

[0003] The conventional methods will be considered in order below. First, a conventional neural network model will be explained. FIG. 17 is a diagram showing one nerve cell unit A, and FIG. 18 is a diagram showing this as a network. A1, A2, and A3 each represent a neuron unit. 1
One neuron unit connects with many other neuron units, receives signals, processes them, and produces output. Figure 18
In this case, the network is hierarchical, and neuron unit A2 is connected to neuron unit A1 in the previous (left) layer.
It receives signals from the neuron unit A3 and outputs them to the neuron unit A3 in the next layer (on the right).

[0004] This will be explained in more detail. First, in neuron unit A in Fig. 17, what is called the coupling coefficient represents the degree of coupling between other neuron units and the own unit. The coupling coefficient is generally denoted by Ti,j. Now, assuming that your neuron unit is the j-th unit, and the output of the i-th neuron unit is yi, Ti,jyi, which is multiplied by the coupling coefficient Ti,j, is the input to your unit. Become. As mentioned above, 1
Since one neuron unit is connected to many neuron units, Ti,j y for those units
ΣTi,jyi, which is the result of adding up i, becomes the input to its own neuron unit within the network. This is called the internal potential and is expressed as uj.

[0005]

[Math. 18]

[0006]Next, by performing nonlinear processing on this input, it becomes the output of that neuron unit. The function used at this time is called a neuron response function, and a sigmoid function as shown in equation (2) and FIG. 19 is used as the nonlinear function.

[0007]

[Math. 19]

When such neuron units are configured into a network as shown in FIG.
By giving i and j and calculating equations (1) and (2) one after another, parallel processing of information becomes possible and the final output is obtained.

An example of such a network realized by an electric circuit is shown in FIG. 20. This is disclosed in Japanese Patent Application Laid-Open No. 62-295188, and is based on a plurality of amplifiers 1 having an S-shaped transfer function.
and a resistive feedback network 2 connecting the output of each amplifier 1 to the input of the amplifier in the other layer. A CR time constant circuit 3 consisting of a grounded capacitor and a grounded resistor is individually connected to the input side of each amplifier 1. Input currents I1, I2, .

Here, the signal strength of the input and output to the network is expressed by voltage, and the strength of the connection between neuron units is determined by the resistance 4 (in the resistive feedback network 2) connecting the input and output lines between each cell. The nerve cell response function is represented by the transfer function of each amplifier 1. That is, in FIG. 20, the plurality of amplifiers 1 have inverted outputs and non-inverted outputs, and the input of each amplifier 1 has a CR time constant circuit 3 serving as an input current supply means, and a pre-selected value. It has a feedback network 2 connecting the output of each of the amplifiers 1 to the input with a resistor 4 (Ti,j) . Resistor 4 represents the transconductance between the i-th amplifier output and the j-th amplifier input, and is chosen so that the network produces equilibrium minima, minimizing the energy function with the minima. I try to do that. In addition, connections between neurons have excitatory and inhibitory properties, which are mathematically expressed by the positive and negative signs of the coupling coefficient, but it is difficult to realize positive and negative signs using constants on the circuit, so here So,
By dividing the output of the amplifier 1 into two and inverting one output, two positive and negative signals are generated, and this is realized by appropriately selecting one of the two signals. Furthermore, an amplifier is used as an equivalent to the sigmoid function shown in FIG.

However, such an analog circuit system has the following problems. ■ When signal strength is expressed as an analog value such as electric potential or current, and internal calculations are also performed in an analog manner, the value changes due to temperature characteristics, drift immediately after power-on, etc. ■ Since it is a network, it requires a large number of elements, but it is difficult to match the characteristics of each element. ■ When the accuracy or stability of one element becomes a problem, when it is made into a network, new problems may arise, and the behavior of the entire network cannot be predicted. - The coupling coefficients Ti,j are fixed, and the only way to do this is to use values learned in advance by other methods such as simulation, and self-learning is not possible.

On the other hand, as a learning rule used in numerical calculations, there is the following one called a backpropagation learning rule.

First, the coupling coefficient between each neuron unit is initially set to a random value. If input is given to the network in this state, the output result will not necessarily be desirable. For example, in the case of character recognition, if the handwritten character "1" is given, the desired output result would be "This character is '1'", but if the coupling coefficient is random, this is not necessarily the case. This is not a desirable result. Therefore, a correct answer (teacher signal) is given to this network, and each coupling coefficient is changed so that the correct answer is obtained when the same input is received again. At this time, the algorithm for determining the amount by which the coupling coefficient is changed is called backpropagation.

For example, in a hierarchical network as shown in FIG. 18, if the output of the j-th neuron unit in the final layer (A3) is yj, and the teacher signal for that neuron unit is dj, then

[Math. 20] So that E expressed by is minimized,

The coupling coefficient Ti,j is changed using the following equation. More specifically, first, the output layer A3 and the layer A2 immediately before it.
When calculating the coupling coefficient with

[Equation 22] When calculating the error signal δ and calculating the coupling coefficient between the intermediate layer A2 further before it and the layer A1 immediately before it,

The error signal δ is determined using the following equation. f' is the first differential function of the sigmoid function f.

[0015] Using this,

[Formula 24] is obtained and Ti,j is varied. Here, η is a learning constant, and α is a stabilization constant. Each cannot be determined logically, so they are determined empirically. Ti,j′
, ΔTi,j' are the values from the previous learning.

[0016] Learning is performed in this manner, and then input is given again to calculate the output and learning is performed. By repeating this operation many times, a coupling coefficient Ti,j that will yield a desired result for a given input is eventually determined. This allows the learning function of the network to be realized.

If a learning method based on such a backpropagation learning rule is intended to be implemented in hardware as it is, the circuit will become large-scale because a large number of four arithmetic operations must be executed. In addition, it is not possible to define the amount corresponding to the internal potential ui, or
In the case of a network in which the differential f' of the response function cannot be defined because the neuron response function is not a monovalent function of the internal potential, this backpropagation learning rule cannot be applied.

On the other hand, an example of a neural network implemented using a digital circuit will be explained with reference to FIGS. 21 to 23. FIG. 21 shows the circuit configuration of a single neuron, in which each synaptic circuit 6 is connected to a cell body circuit 8 via a dendrite circuit 7. FIG. 22 shows an example of the configuration of the synapse circuit 6, which is applied to the input pulse f via the coefficient circuit 9 by a magnification a(
A rate multiplier 10 is provided to which a value obtained by multiplying the feedback signal by a factor of 1 or 2 is input, and a synapse load register 11 that stores a weighting value w is connected to the rate multiplier 10. Further, FIG. 23 shows a configuration example of the cell body circuit 8, and the control circuit 12
, an up/down counter 13, a rate multiplier 14, and a gate 15 are connected in this order, and an up/down memory 16 is further provided.

[0019] This represents the input and output of the neuron unit as a pulse train, and the pulse density represents the amount of signal. The coupling coefficient is expressed as a binary number and stored in the register 11. By inputting the input signal to the clock of the rate multiplier 10 and inputting the coupling coefficient to the rate value,
The pulse density of the input signal is reduced according to the rate value. This is based on the backpropagation model equation Ti,
This corresponds to the jyi part. Next, the Σ portion of ΣTi, jyi is realized by an OR circuit represented by a dendrite circuit 7. Since the connections have excitatory and inhibitory properties, they are divided into groups in advance and OR'd for each group. An output is obtained by inputting these two outputs to the up side and down side of the counter 13 and counting them. Since this output is a binary number, the rate multiplier 14 is used again to convert it into a pulse density. By making these units into a network, a neural network can be realized. Learning is realized by inputting the final output to an external computer, performing numerical calculations inside the computer, and writing the results to the register 11 for coupling coefficients. Therefore, there is no self-learning function at all. Furthermore, the circuit configuration is complicated, as the pulse density signal is first converted into a numerical value (binary number) using a counter, and then converted back into pulse density.

[0020]

[Problems to be Solved by the Invention] As described above, in the case of the conventional technology, the analog circuit system does not operate reliably;
Learning methods based on numerical calculations also require complicated calculations, making them unsuitable for use in hardware, and digital systems that ensure reliable operation have complex circuit configurations. Another drawback is that self-learning cannot be performed on the hardware.

In particular, when attempting to solve these drawbacks by adding a self-learning function to a digital neural network with a simple circuit configuration, it is difficult to properly define the internal states or response functions of neurons, so backproperization is required. gation learning rules cannot be applied. Therefore, it is desired to devise a learning rule that can be applied in such a case and to realize this learning rule using a digital circuit.

[0022]

In the invention as claimed in claim 1, the coupling coefficient between a neuron i in a certain layer and a neuron j in the next layer in a hierarchical neural network is Ti.
,j, and this coupling coefficient Ti,j is the positive component T(+)
As the difference between i,j and the negative component T(-)i,j

[Formula 25], the output value from neuron i is yi, the output sensitivity of neuron j is Z(+)i,j, Z(-)i,j,
The error signal in neuron j is expressed as δ(+)j, δ(−
)j, then for each step of learning,

[Formula 26] The amount ΔT(+)i,j is defined as the coupling coefficient T(+)i,j
(T(+)i,j+ΔT(+)i,j
) or the value obtained by adding the inertia term to this value as the new T(+)i,j,

[Formula 27] The amount ΔT(-)i,j is expressed as the coupling coefficient T(-)i,j
(T(-)i,j +ΔT(-)i,
The learning is performed by setting the value of T(-)i,j or the value obtained by adding an inertia term to this value as the new T(-)i,j. However, the output sensitivity Z(+)i,j, Z(-)i,
j is the product with respect to n

Assuming that [Equation 28] means calculating the product for all neurons n other than neuron i among neurons connected to neuron j in the layer to which neuron i belongs, then

[Math. 29] The sum of k is calculated by

If [Equation 30] means that the sum is calculated for all neurons k connected to neuron j in the layer next to the layer to which neuron j belongs, then the error signal δ(+)j,
δ(-)j is, in the output layer, if the teacher signal is dj,

[Math. 31] In the middle class,

It is calculated by [Equation 32]. Also, T(+)i,j,
When T(-)i,j and yi can take values larger than 1, divide them by the maximum value that they can take and get T(+)i,j ≦1, T(-)i,j ≦1,yi
It is assumed that it is normalized to ≦1.

In the invention as claimed in claim 2, the excitatory coupling coefficient between the neuron i in a certain layer and the neuron j in the next layer in the hierarchical neural network is expressed as T(+
)i,j, the inhibitory coupling coefficient is T(-)i,j, the output value from neuron i is yi, the output sensitivity of neuron j is Z(+)i,j, Z(-)i,j, When the error signals in neuron j are δ(+)j and δ(-)j, these T(+)i,j and T(-)i,j
,yi ,Z(+)i,j,Z(-)i,j ,δ(
+)j, δ(-)j are all expressed as a pulse train, and by using the logical sum, logical product, and logical negation of these pulse trains, and the thinning operation of the pulses in the pulse train, for each step of learning,

The pulse train obtained as a result of the logical operation [Equation 33] is transformed into a new T(+
)i,j,

The pulse train obtained as a result of the logical operation [Equation 34] is transformed into a new T(-
) i, j. However, the logical sum of two pulse trains X and Y is represented by the symbol X∪Y, the logical product is represented by the symbol X∩Y, and the logical negation of the pulse train X is expressed by ~(
The symbol ∧(X) indicates an operation for thinning out pulses in the pulse train X. Also, n
disjunction for

[Equation 35] means to calculate the sum of all neurons n other than neuron i among the neurons in the layer to which neuron i belongs and which are connected to neuron j with an excitatory coupling coefficient, and for n, logical sum of

Define [Equation 36] to mean the sum of all neurons n other than neuron i among the neurons in the layer to which neuron i belongs and which are connected to neuron j with an inhibitory coupling coefficient. When Z(+)i,j
, Z(-)i,j is

It is calculated by [Equation 37]. In addition, the operation to thin out the pulses in the pulse train X to half the pulse density is expressed by the symbol ∇(X), and the logical

[Equation 38] means to perform a logical sum on all neurons k that are in the layer next to the layer to which neuron j belongs and are connected to neuron j with an excitatory coupling coefficient, and the logical sum on k is

When [Equation 39] is defined as meaning the logical OR of all neurons k that are in the layer next to the layer to which neuron j belongs and are connected to neuron j with an inhibitory coupling coefficient, then δ (+)j, δ(-)j are, in the output layer, if the teacher signal is dj,

[Math. 40] In the middle class,

[Math. 41] It shall be calculated as follows.

[0024] Furthermore, in the invention as set forth in claim 3, a signal processing device using such a learning method includes a plurality of circuit units that receive an input signal and output an output signal.
These circuits have at least one circuit that receives signals from outside the network, one circuit that receives signals from other circuit units within the network, and one circuit that outputs signals to the outside of the network. A hierarchical neural network consisting of digital logic circuits in which units are connected in a network is provided, and when one circuit unit receives an output signal from another circuit unit as an input signal, weight data for weighting the input signal is used as a coupling coefficient. The learning method according to claim 2 is provided with a memory for storing the information, and performs variable processing of varying the coupling coefficient value based on a difference between an output signal from a circuit unit outputting to the outside of the network and a signal given from outside the network. A coefficient variable circuit based on a digital logic circuit that performs this function is provided within the circuit unit or outside the circuit unit within the network.

[0025] Furthermore, in the invention as set forth in claim 4, a neural network is formed by connecting a plurality of neurons in a hierarchical manner to process an input signal representing a bit string representation by digital logic operations and outputting an output signal representing a bit string representation. When a neuron receives an output signal from another neuron as an input signal, weight data for weighting the input signal is used as a bit string representation of a connection coefficient, and for each connection, an excitatory connection coefficient and an inhibitory connection coefficient are calculated. The learning method according to claim 1 or 2 is used to perform variable processing of varying the coupling coefficient values stored in the neurons in order to bring the output value from the neural network closer to a desired value. In the neural network learning method carried out, the bit string of the excitatory coupling coefficient is shifted by one bit or more relative to the bit string of the inhibitory coupling coefficient for each cycle of the learning.

In the invention as claimed in claim 5, the signal processing device using such a learning method includes a plurality of neurons that process an input signal represented by a bit string by a digital logic circuit and output an output signal represented by a bit string. A neural network is formed by connecting in a hierarchical manner, and when one neuron receives an output signal from another neuron as an input signal, weight data for weighting the input signal is used as a connection coefficient in a bit string representation for each connection. A memory for storing two types of coupling coefficients, an excitatory coupling coefficient and an inhibitory coupling coefficient, is provided, and the coupling coefficient value stored in the neuron is varied in order to bring the output value from the neural network closer to a desired value. A coefficient variable circuit is provided which is a digital logic circuit that performs processing using the learning method according to claim 1 or 2, and in this coefficient variable circuit, a bit string of excitatory coupling coefficients is coupled to an inhibitory coupling coefficient every cycle of the learning. A shift means is provided for shifting one or more bits relative to the bit string of the coefficient.

[0027]

[Operation] According to the learning method of the invention as set forth in claim 1, since the differential component of the neuron response function due to the internal potential of the neuron is not included, the neuron response function is 1 of the internal potential.
This method can also be applied to neural networks in which the differentiation of a neuron response function by internal potential cannot be defined because it is not a value function, or to neural networks in which the internal potential itself cannot be defined. In this case, the amount of change in the coupling coefficient is calculated by calculating only the amount that always takes a non-negative value, so it is suitable for hardware that is difficult to express negative values, such as those that treat pulse density as a signal. can also be easily applied. In particular, according to the learning method of the invention as set forth in claim 2, learning of the neural network can be performed only by logical operations on pulse trains and pulse thinning operations, so it is easy to implement the learning method in hardware using digital circuits.

Further, according to the signal processing device according to the third aspect, the functions of the neural network including the self-learning function can be performed in parallel on hardware at high speed. In particular, since it has a digital logic circuit configuration, problems such as temperature characteristics and drift that occur with analog circuit systems are eliminated. Furthermore, since the coupling coefficients are stored in memory, they can be easily rewritten and have versatility.

According to the learning method of the invention described in claim 4 or the signal processing device described in claim 5, the bit string of excitatory coupling coefficients is changed to the bit string of inhibitory coupling coefficients in each cycle of learning. Since it is relatively shifted by more than 1 bit,
The correlation in the bit arrangement between the bit string of the excitatory coupling coefficient and the bit string of the inhibitory coupling coefficient is erased,
It is possible to prevent the learning progress from stopping before reaching the desired coupling coefficient value, and the learning effect of the neural network is highly resistant to fluctuations in the bit arrangement of the coupling coefficients after learning. , which improves learning ability.

[0030]

Embodiment A first embodiment of the present invention will be explained based on FIGS. 1 to 12. This example assumes a digital logic circuit configuration, and all input/output signals, intermediate signals, coupling coefficients, teacher signals, etc. related to neuron units are "0".
It is represented by a bit string expressed as a binary value of "1". ■ The amount of signals inside the network is expressed in terms of pulse density (the number of 1's within a certain period of time in a bit string). ■ Calculations within a neuron unit are expressed by logical operations between bit strings. ■ Place the coupling coefficient bit string in memory. ■
Learning is achieved by rewriting this bit string. ■
Regarding learning, the error is calculated based on the given teaching signal bit string, and the coupling coefficient bit string is changed based on this. At this time, calculation of errors and calculation of changes in coupling coefficients are all performed by logical operations on bit strings of "0" and "1". This is how it was done.

An explanation will be given below based on an example of a pulse density hierarchical neural network that embodies this idea. First, the configuration of the signal calculation section will be explained with reference to FIG. FIG. 2 shows a portion corresponding to one neuron (circuit unit) A, and the network configuration is hierarchical as in the case of FIG. 18. All input and output are "1" and "0"
The data that has been binarized and synchronized is used. The intensity of the input signal yi is expressed by the pulse density of the bit string. For example, as in the bit string shown in FIG. 3, it is expressed by the number of states of "1" within a certain period of time. The illustrated example represents 4/6, and the signal is 4 “1”s and 0 “0” out of 6 synchronization pulses.
There are 2 pieces. At this time, the arrangement of "1" and "0" is
Preferably random.

On the other hand, the coupling coefficient Ti,j is similarly expressed by the pulse density of a bit string, and is prepared in advance in the memory as a bit string of "0" and "1". Figure 4 shows “101
010'' = 3/6. In this case as well, "1" and "0"
It is desirable that the arrangement of the items be random.

Then, this bit string is sequentially read out from the memory in accordance with the synchronous clock, and as shown in FIG.
The ND gate 21 performs AND with the input signal bit string (yi ∩ Ti,j). This is taken as an input to neuron j. To explain in the case of the above example, the input signal is “1”.
01101", by reading the bit string from the memory in synchronization with this and sequentially ANDing it, "101000" as shown in FIG. 5 is obtained, which means that the input yi is the coupling coefficient Ti,j This shows that the pulse density is converted to 2/6.

The pulse density of the output of the AND gate 21 is:
Approximately, it is the product of the pulse density of the input signal and the pulse density of the coupling coefficient, and has the same function as the coupling coefficient of the analog system. This means that the longer the signal train is, the more
The more random the arrangement of and "0" is, the closer the function is to a product. Note that when the bit string of the coupling coefficient is shorter than the input bit string and there is no more data to be read, it is sufficient to return to the beginning of the data and repeat the reading.

Since one neuron unit has multiple inputs, there are many "ANDs of input signals and coupling coefficients" as described above, and then the OR circuit 22 performs a logical OR of these. The inputs are synchronized, so for example, the first data is "101000" and the second data is "010000".
In this case, the OR of the two results in "111000". The m multi-input components are simultaneously calculated and output. That is, it becomes as shown in FIG. This corresponds to the sum calculation and nonlinear function (sigmoid function) part in analog calculation.

When the pulse density is low, the ORed pulse density approximately matches the sum of the respective pulse densities. As the pulse density increases, the OR circuit 22
Since the output gradually becomes saturated, it does not match the sum of the pulse densities, and nonlinearity appears. In the case of OR, the pulse density is neither greater than 1 nor less than 0, and is a monotonically increasing function, approximately similar to a sigmoid function.

By the way, in order to make the function of the neural network practical, it is desirable that the coupling coefficient can take not only positive values but also negative values. A connection with a positive coupling coefficient is called an excitatory connection, and a connection with a negative coefficient is called an inhibitory connection. In analog circuits, in the case of inhibitory coupling, an amplifier is used to invert the output and couple it to another neuron with a resistance value corresponding to the coupling coefficient. Pulse density is always positive, but if you use one of the three methods shown below (a, b, c), even if the coupling coefficient is expressed by pulse density, it will be possible to deal with the excitatory and inhibitory properties of the coupling. becomes possible.

First, as method a, it is set in advance whether each bond is excitatory or inhibitory, and the above-mentioned logical OR is performed separately for the excitatory bond group and the inhibitory bond group. Alternatively, whether each input is excitatory or inhibitory is set in advance, and the excitatory input group and the inhibitory input group are logically ORed separately. For example, as shown in FIG. 7, at the input stage, groups are divided in advance into excitatory connection group a and inhibitory connection group b, and shift registers 23a and 23 that store connection coefficients Ti,j for each input are used.
b may be provided. The input signal and the bit string of the coupling coefficient Ti,j are ANDed by AND gates 24a and 24b. Then, OR gates 25a and 25b are set for each group a and b.
The logical sum is calculated by

Here, the OR result of excitatory group a (OR gate 25a output) obtained in this way and the OR result of inhibitory group b (OR gate 25b output) are expressed as follows.
The gate circuit 26 performs the following combination to calculate the output value from the neuron. First, if the OR results of both OR gates 25a and 25b do not match, the output from the OR gate 25a of excitatory group a is taken as the output value from the neuron, that is, the gate circuit 26. In other words,
If the OR result of excitatory group a is "0" and the OR result of inhibitory group b is "1", output "0", and if the OR result of excitatory group a is "1" and the OR result of inhibitory group b is O
If the R result is "0", output "1". Also, both O
If the OR results of the R gates 25a and 25b match, a separately prepared separate input signal is output as is.

As method b, as shown in FIG. 8, each connection has a memory 27 indicating whether the connection is excitatory or inhibitory, and the excitatory or inhibitory characteristics of the connection are determined depending on the contents of the memory 27. The gate circuit 28 allows for arbitrary setting. An OR gate 2 is formed between the excitatory connection group and the inhibitory connection group determined by the contents of this memory 27.
A logical sum is calculated separately using 9a and 29b. The logical OR results for each group thus obtained are processed by the gate circuit 26 and outputted from the neuron as in the case of FIG.

As method c, each connection has an excitatory coupling coefficient and an inhibitory coupling coefficient, as shown in FIG.
Both are placed on memories 30 and 31, respectively. This corresponds to decomposing and expressing the coupling coefficient into the sum of a positive quantity and a negative quantity. Then, the AND gate 32 performs a logical product of all the input signals and the excitatory coupling coefficients stored in the memory 30.
The outputs of these AND gates 32 are logically summed by an OR gate 33a. On the other hand, the AND gate 34 calculates the logical products of all input signals and the inhibitory coupling coefficients stored in the memory 31, and the logical sum of the outputs of these AND gates 34 is calculated by the OR gate 33b. The logical OR results for each group thus obtained are processed by the gate circuit 26 and output from the neuron as in the case of FIG.

In any case, the neural network to which the present invention is applied is configured as a hierarchical network as shown in FIG. 18 by combining neurons having such output functions. If the entire network is synchronized, each layer can perform calculations in parallel using the functions described above.

[0043]The learning method, which is the gist of this embodiment, will now be explained. In this example, as a method for dealing with excitatory connections and inhibitory connections, there is a method in which excitatory connection coefficients and inhibitory connection coefficients are stored in the memories 30 and 31 for each connection, as shown in the method shown in FIG. It shall be based on the following.

The learning method of this embodiment is to first obtain an error signal for each neuron, and then perform learning by changing the coupling coefficient value using this error signal. The error signal is first calculated for the neurons in the final layer, then calculated for the neurons in the previous layer using the error signal of the final layer just calculated, and then calculated using the error signal of the layer just calculated. Find the neurons in the previous layer, and so on, going backwards through the layers, starting from the last layer. The error can also take a negative value, but in the case of this embodiment, the signal is expressed in terms of pulse density, so it is not possible to express a quantity that can take both positive and negative values with one signal. Therefore, here, the error signal is expressed using two types of signals: a signal representing a positive component and a signal representing a negative component.

■ Error signal in the final layer (output layer) The error signal of neuron j in the final layer (assuming the Nth layer is the final layer) is expressed as the following δ(+)j, N, δ(-)
Let j, N. That is, if the output signal of the j-th neuron is expressed as yj and the teacher signal is expressed as dj, then the error signal δ(+)j,N representing the positive component is

[Math. 42] The error signal δ(-)j,N representing the negative component is

[Formula 43]. Next, a method for calculating these error signals in the above-described neural network structure that transmits signals using bit strings will be described. in this case,
The above equation can be calculated on a neural network by performing AND processing on the multiplications appearing in the above equation and replacing subtraction from 1 with NOT processing. That is, y
j(1-dj) by yj ∩(~dj), dj(
1-yj ) by dj ∩(~yj ). Here, AND processing is represented by ∩, and NOT processing is represented by ~. Calculation based on this logical formula can be realized by a gate circuit that is a combination of exclusive OR gate 35 and AND gates 36 and 37 shown in FIG.

(1) Error Signal in Intermediate Layer In this embodiment, the error signal δ(+)j,L, δ(-)j,L in the j-th neuron of the L-th layer is obtained from the following equation.

[0047]

[Math. 44]

Here, the logical sum Σ for k means to calculate the sum of all neurons that are in the (L+1)th layer one layer ahead of the Lth layer and are connected to neuron j. do. Also, T(+)j,k,L+1 is the j-th neuron of the L-th layer and the one ahead (L
+1) is the excitatory coupling coefficient between the kth neuron in the Lth layer and the excitatory coupling coefficient between the jth neuron in the Lth layer and the of (L
+1) is the inhibitory coupling coefficient with the kth neuron in the kth layer.

[0049] Also, Z(+)j, k, L+1, Z(-
)j, k, L+1 are determined by the following formula.

[Math. 45]

Here, yn,L is the nth layer of the Lth layer.
is the output from the th neuron, T(+)n,k,
L+1 is the excitatory coupling coefficient between the nth neuron of the Lth layer and the kth neuron of the (L+1)th layer, and T(-)n,k,L+1 is the excitatory coupling coefficient between the nth neuron of the Lth layer and the kth neuron of the (L+1)th layer. It is the inhibitory coupling coefficient between the nth neuron of the Lth layer and the kth neuron of the (L+1)th layer. Also, the logical product Π for n is the (L+1)th
This means taking the product for all neurons n other than the j-th neuron among the neurons of the L-th layer that are connected to the k-th neuron of the L-th layer.

Next, a method for realizing the above-mentioned learning operation in the above-described neural network structure in which signals are transmitted using bit strings will be explained. In this case, calculation can be performed on the neural network by replacing multiplication in the above equation with AND processing, addition with OR processing, and subtraction from 1 with NOT processing. This processing operation will be explained with reference to the circuits of FIGS. 1 and 11. It is assumed that the circuit in FIG. 1 and the circuit in FIG. 11 are connected at the portions marked with ■■.

First, the input signal that the k-th neuron of the (L+1)-th layer receives from the i-th neuron of the L-th layer is yi,L, and the excitatory connections stored in the memory 30 regarding the input are The coefficients are T(+)i,k,L+
1. The inhibitory coupling coefficient stored in the memory 31 is T(-)
Let it be expressed as i, k, L+1. At this time, the error signal δ(+)j at the j-th neuron of the L-th layer
, L, δ(-)j, L are determined as follows. first,
In the kth neuron of the (L+1)th layer, the error signal calculation signal Δ(+)j,k,L+1,Δ(-)j,k,L+1, which will be defined later, is obtained by the following processing. . For all i such that i≠j, the input signal yi,
The logical product of L and the excitatory coupling coefficient T(+)i,k,L+1 is taken by an AND gate 32, the logical sum of the outputs of these AND gates 32 is taken by an OR gate 38, and O
The output of R gate 38 is inverted by NOT gate 39. Let this negative output be Z(+)j,k,L+1. Similarly, for all i such that i≠j, the input signal yi,L
and the inhibitory coupling coefficient T(-)i,k,L+1 by an AND gate 33, and the outputs of these AND gates 33 are logically summed by an OR gate 40,
The output of the OR gate 40 is inverted by the NOT gate 41. Let this negative output be Z(-)j,k,L+1.

Next, the NOT output Z(+
)j, k, L+1 and coupling coefficient T(+)j, k, L+1
The AND gate 42 performs a logical product with
The output of the gate 42 is ANDed with the error signal δ(+)k,L+1 input from the connection part and the AND gate 43
Depends on it. Similarly, the negative output Z(
-)j,k,L+1 and coupling coefficient T(-)j,k,L+
1 by an AND gate 44, and an AND gate 48 performs a logical product between the output of the AND gate 44 and the error signal δ(-)k,L+1 inputted from the connecting portion. The outputs of these AND gates 43 and 48 are logically summed by an OR gate 46. The signal Δ(+)j,k,L+1 obtained by such processing is transmitted to the jth neuron of the previous layer. This Δ(+)j,k,L+1 can be expressed as follows.

[0054]

[Formula 46] However, in this equation, AND is represented by the symbol ∩, and OR is represented by the symbol ∪.

Similarly, the AND gate 47 calculates the logical product of the output of the AND gate 42 and the error signal δ(-)k,L+1 inputted from the connection part (2). Also, AND
The output of the gate 44 is ANDed with the error signal δ(+)k,L+1 input from the connection part and the AND gate 45
Depends on it. The outputs of these AND gates 47 and 45 are logically summed by an OR gate 49. The value Δ(-)j,k,L+1 obtained through such processing is transmitted to the j-th neuron in the previous layer. Δ(-)j,
When k, L+1 is expressed as an equation, it is as follows.

[0056]

[Math. 47]

Next, in the j-th neuron of the L-th layer, the OR gate shown in FIG. A logical OR is performed using the group 50. Similarly, in the jth neuron of the Lth layer, the
Δ(
-) For j, k, and L+1, perform a logical sum using the OR gate group 51 shown in FIG. 50 of these OR gates
, 51 through 1/2 frequency divider circuits 52 and 53, respectively, to halve the pulse density and obtain the error signal δ(+)j,
Let L, δ(-)j, L. That is,

[0058]

[Formula 48]. Here, ∪ for k means ORing all k, ie, all neurons of the (L+1)th layer. In addition, 1/2 frequency dividing circuits 52, 53
is a circuit for outputting 1 with probability 1/2 when the input is 1. This can be easily achieved by using the thermal noise of the transistor as a random number generation source and comparing this with a certain voltage value using a comparator. Alternatively, a method of erasing every other pulse may be used, and in this case, this can be easily realized using a commonly available circuit, such as a configuration that performs logical operations on the output of a counter, or a flip-flop.

■ Change of coupling coefficient using error signal Error signal δ(+)j obtained by the calculation process of ■■ mentioned above
, L , δ(-)j, L , each coupling coefficient is changed as follows. first,

[Math. 49] Find ΔT(+)i,j,L by: Also,

∆T(-)i, j, L is determined by Equation 50. Here, η
is any positive real number smaller than 1, yi,L-1 is the output from the i-th neuron of the (L-1)th layer, and Z(+)i,j,L,Z( -) i, j, L
is the quantity determined by the following equation.

[0060]

[Formula 51] Here, ym,L-1 is the m-th layer of the (L-1)th layer.
This is the output from the th neuron. T(+)m,j,
L is the excitatory coupling coefficient between the mth neuron of the (L-1)th layer and the jth neuron of the Lth layer. Similarly, T(-)m,j,L is the inhibitory coupling coefficient between the m-th neuron of the (L-1)th layer and the j-th neuron of the L-th layer. be. Also, the product Π for m is the sum of all neurons m other than the i-th neuron among the neurons in the (L-1)th layer that are connected to the j-th neuron in the L-th layer. means to take the product of

The coupling coefficient ΔT(+)i,j thus calculated
, L , ΔT(-)i, j, L , T(+)i
,j,L+ΔT(+)i,j,L as new T(+)
i, j, L, T (-) i, j, L + ΔT (-)
Let i,j,L be new T(-)i,j,L.

Next, a method for realizing such arithmetic processing on the neural network of the above-mentioned method of transmitting signals using bit strings will be explained. In this case, by ANDing the multiplications that appear in the above formula, the addition can be reduced to O
By replacing subtraction with NOT and AND in the operation of taking R, the above equation can be calculated on a neural network. This process will be explained with reference to FIG.

Now, the coupling coefficient to be changed is Lth
Let it be the coupling coefficient between the j-th neuron of the (L-1)th layer and the i-th neuron of the (L-1)th layer.

First, for all m where m≠i, the AND gate 3 calculates the logical product of the input signal ym,L-1 and the coupling coefficient T(+)m,j,L stored in the memory 30.
2, their logical sum is taken by an OR gate 38, and it is negated by a NOT gate 39. The value is Z(+)i,
Let j, L. Similarly, for all m where m≠i, the AND of the input signal ym,L-1 and the coupling coefficient T(-)m,j,L stored in the memory 31 is ANDed.
gate 33 and their logical sum is OR gate 4.
0 is taken, and NOT gate 41 is used to negate. Let the value be Z(-)i,j,L. Next, the AND gate 54 takes the AND of the negative output Z(+)i, j, L and the input yi, L-1, and the error signal δ(-) given from the AND gate 54 output and the connection part j, L+1
The AND gate 55 performs a logical product with the following. Also, AN
The AND gate calculates the logical product of the output of the D gate 54 and the error signal δ(+)j,L+1 given from the connection point ■.
Take it at 9. Similarly, the AND gate 56 takes the AND of the negative output Z(-)i, j, L and the input yi, L-1, and the error signal δ(-) given from the AND gate 56 output and the connection part AND the logical product with j, L+1
Take it at gate 57.

In addition, the output of the AND gate 56 and the connection section ■
An AND gate 60 performs a logical product with the error signal δ(+)j,L+1 given from δ(+)j,L+1.

Next, the pulse density conversion circuit 61 converts the AN
After reducing the pulse density of the output of the D gate 55, T(+
) i, j, and L using the OR gate 62. Further, after reducing the pulse density of the output of the AND gate 59 by the pulse density conversion circuit 58, the NOT gate 6
3 takes logical negation. Here, reducing the pulse density by the pulse density conversion circuit corresponds to an operation of multiplying by a learning constant η when calculating the amount of change in the coupling coefficient. Further, the output of the NOT gate 63 and the output of the OR gate 62 are ANDed by an AND gate 64 to obtain a new coupling coefficient T(+)i,j,L. As a result of this process,
The resulting new coupling coefficient T(+)i,j,L can be expressed as follows.

[0067]

[Equation 52] Here, OR is represented by the symbol ∪, AND is represented by the symbol ∩, and NOT is represented by the symbol ~. Also, η(X
) represents the operation of reducing the pulse density of X, then

[Math. 53] It is.

Similarly, the pulse density conversion circuit 65 converts A
After reducing the pulse density of the output of the ND gate 60, T(
-) The OR gate 67 calculates the logical sum with i, j, and L. Further, after the pulse density of the output of the AND gate 57 is reduced by the pulse density conversion circuit 66, a logical negation is performed by the NOT gate 68. Here, reducing the pulse density by the pulse density conversion circuit corresponds to an operation of multiplying by a learning constant η when calculating the amount of change in the coupling coefficient. Further, the output of the NOT gate 68 and the output of the OR gate 67 are ANDed by an AND gate 69 to obtain a new coupling coefficient T(-)i,j,L. The new coupling coefficient T(-)i,j,L obtained as a result of this process can be expressed as follows.

[0069]

[Math. 54]

Here,

[Math. 55] It is.

To reduce the pulse density, pulses may be thinned out. For example, if every other bit string is erased, the pulse density is halved. Such a thinning operation can be easily realized using a commercially available circuit, by performing a logical operation on the output of a counter, or by using a flip-flop or the like. When a counter is used, the rate at which the pulse density is reduced can be arbitrarily and easily set, making it possible to control the characteristics of the network circuit.

[0072] Although it is desirable that the above-described modification of the coupling coefficients be carried out for all coupling coefficients in the network, it is not necessarily limited to this, and in some cases, the modification process may not be carried out for some coupling coefficients. In some cases.

Furthermore, the OR gates 33a and 3 shown in FIG.
The part following 3b is shown in FIG. 12, which is the gate circuit 26 shown in FIG. 9, etc. That is, it is the part that generates the output from the neuron in the forward process.

[0074] Next, examples of learning using the method of this embodiment will be given as specific examples 1 and 2. First, the conditions for specific example 1 are that the number of layers is 4, the number of neurons is 1 in the first layer, 9 in the second layer, 9 in the third layer, 1 in the fourth layer, and the input signal value is 0. .2, the teacher signal value is 0.8, and after 1000 steps of learning, the output is collected for an input signal of 0.2 by 10
When the distribution of the output values was observed after repeating the process 00 times, it was found that the output signal had a distribution with the mode value being 0.8, indicating that learning was performed correctly.

Furthermore, the conditions for specific example 2 are that the number of layers is 3, the number of neurons is 2 in the first layer, 3 in the second layer, and 3 in the third layer.
When the layer is 1 and the input signal value is (1.0, 0.0), the teacher signal value is 0.0, and when the input signal value is (0.0, 1.0), the teacher signal value is 1.0. , after 1000 steps of learning, we repeated sampling of the output for the set of input signal values (1.0, 0.0) 1000 times and looked at the distribution of the output values, and found that the output signal has 0.0 as the mode. A sharp distribution with a sharp distribution of A sharp distribution of values was obtained, and the learning was successful.

Next, a second embodiment of the present invention is shown in FIG.
This will be explained with reference to FIGS. This embodiment further improves the learning ability of the previous embodiment. First, in a pulse density hierarchical neural network like the above embodiment to which this embodiment is applied, in the learning process, the excitatory coupling coefficient (positive coupling coefficient) and the inhibitory coupling coefficient (negative coupling coefficient) are determined. However, in order for these to have the intended effect, the AND operation has the effect of creating a product of pulse densities, and the OR
It is necessary to show that the operation creates the sum of pulse densities. For this purpose, it is necessary to ensure that the bit arrangement of the bit string with a positive coupling coefficient and the bit arrangement of the bit string with a negative coupling coefficient have no correlation. In fact, if the bit arrangements of bit string A with pulse density a and bit string B with pulse density b are independent of each other (i.e., the position where the bit in bit string A is turned on and the bit in bit string B is unrelated to the position where is turned on), A∪B
When A∩B is executed many times, the resulting pulse density will be on average close to the sum of a and b, and when A∩B is executed many times, the resulting pulse density will be on average close to the sum of a and b. The value is close to the product of

However, if there is a correlation between the bit arrangements of both bit strings A and B, for example, A=“01010101” and B
= "00010001" where the positions of the on bits of both tend to overlap, the pulse density of A∪B is not the sum of a and b but a value close to a, and the pulse density of A∩B is a The value is not the product of and b, but a value close to b. Therefore, when the correlation of the on bit positions between the bit string with a positive coupling coefficient and the bit string with a negative coupling coefficient increases,
Learning ability decreases.

Here, if there are two types of coupling coefficients, positive and negative, for each coupling as described above, the bit arrangement of the bit string with a positive coupling coefficient and the bit arrangement of the bit string with a negative coupling coefficient are correlated. It is often possible that learning progresses in the direction of having. For example, as learning progresses, the number of connections in which the on-bit position of a bit string with a positive coupling coefficient matches the on-bit position of a bit string with a negative coupling coefficient, or conversely, This is because the number of combinations in which the on bit position of the bit string of and the off bit position of the bit string of the negative coupling coefficient match often increases.

In such a case, the progress of learning may stop before it reaches a desired level. Further, even if the bit string of the coupling coefficient after learning is slightly shifted for some reason, the learning effect will be lost. Therefore, in this embodiment, the learning progresses in the direction in which the bit arrangement of the bit string with a positive coupling coefficient and the bit arrangement of the bit string with a negative coupling coefficient have a correlation, so that the learning progress of the pulse density hierarchical neural network is This is to prevent the learning from stopping, and the learning effect has strong resistance to fluctuations in the on-bit position of the coupling coefficient after learning, thereby increasing the learning ability.

Basically, in the learning process,
Shifting a bit string with a positive coupling coefficient by 1 bit or more with respect to a bit string with a negative coupling coefficient, or conversely, shifting a bit string with a negative coupling coefficient by 1 bit or more with respect to a bit string with a positive coupling coefficient every cycle. This prevents the bit arrangement of a bit string with a positive coupling coefficient and the bit arrangement of a bit string with a negative coupling coefficient from proceeding in a direction in which there is a correlation.

That is, several methods can be considered to prevent the correlation between bit strings from increasing.
In this embodiment, as described above, this is achieved using an extremely simple method of relatively shifting the bit string of the positive coupling coefficient and the bit string of the negative coupling coefficient by one bit or more every cycle of learning. be. In this case, the bit strings of positive and negative coupling coefficients may be shifted by one or more bits from each other after all the bits of the bit string of the coupling coefficient in the memory that stores the coupling coefficients have been updated, but the bit string of the coupling coefficient It is easier to shift the bit of the positive or negative coupling coefficient by one or more bits each time one bit of is processed, and the procedure is simpler and the circuit for this purpose is simpler.

Next, a specific learning method according to this embodiment will be explained. First, using the n-th bit of the positive coupling coefficient bit string and the n+1-th bit of the negative coupling coefficient bit string, a new positive coupling coefficient bit is created by the logical operation as explained in the first embodiment. and the values of the bits of the new negative coupling coefficient. Or, conversely, by using the n+1st bit of the bit string with a positive coupling coefficient and the nth bit of the bit string with a negative coupling coefficient, a new positive coupling is created by the logical operation as explained in the first embodiment. Compute the values of the bits of the coefficient and the bits of the new negative coupling coefficient. When storing these new coupling coefficients in memory,
The new positive coupling coefficient bit value is stored in the nth bit position of the positive coupling coefficient bit string, and the new negative coupling coefficient bit value is stored in the nth bit position of the negative coupling coefficient bit string. do. Such processing is performed with n=1, 2,
3, . . . are repeated in the direction in which the value of n increases, and when all bits of the bit string of the coupling coefficient have been processed, return to the beginning and repeat the same process.

Alternatively, without being limited to the above method, for example, using the n-th bit of the bit string with a positive coupling coefficient and the n-th bit of the bit string with a negative coupling coefficient, a new positive Compute the values of the bits of the coupling coefficient and the bits of the new negative coupling coefficient. When storing these new calculated coupling coefficients in memory, the value of the bit of the new positive coupling coefficient is stored in the nth bit position of the bit string of the positive coupling coefficient, but the value of the bit of the new negative coupling coefficient is stored in the nth bit position of the bit string of the positive coupling coefficient. The value is stored in the n-1th bit position of the bit string of the negative coupling coefficient. Or, conversely, the value of the bit of the new positive coupling coefficient is stored in the n-1 bit position of the bit string of the positive coupling coefficient, but the value of the bit of the new negative coupling coefficient is stored in the bit string of the negative coupling coefficient. is stored in the nth bit position of . This process is repeated in the direction of increasing the value of n, such as n = 1, 2, 3, etc. When all bits of the bit string of the coupling coefficient have been processed, return to the beginning and repeat the same process. may be repeated.

According to such a learning method, the bits of the positive and negative coupling coefficients updated at the same time are not used simultaneously in the next learning cycle, so the bit arrangement of the bit string of the positive coupling coefficient It is possible to prevent learning from proceeding in a direction in which there is a correlation between the bit string and the bit arrangement of the bit string having a negative coupling coefficient. In the above description, the bit strings are relatively shifted by 1 bit, but the shift is not limited to 1 bit, and any shift of 1 bit or more is sufficient.

[0085] Such a learning method is illustrated in FIGS. 13 to 1.
This is realized by a circuit as illustrated in 6. These illustrated examples have the same components; first, a memory 71 which corresponds to the memory 30 and stores a bit string with a positive coupling coefficient; and a memory 72 which corresponds to the memory 31 and stores a bit string with a negative coupling coefficient. and is provided. each memory 71
, 72 are provided with bit storage circuits 73, 74 and bit extraction circuits 75, 76. Bit extraction circuit 75
, 76 are connected to a new coupling coefficient calculation circuit 78 together with an output calculation circuit 77.
The output sides of are fed back to the memories 71 and 72 through the bit storage circuits 73 and 74, respectively, so that they can be updated and rewritten. The output calculation circuit 77 has the circuit configuration shown in FIG. 9, for example, and the new coupling coefficient calculation circuit 78
has the circuit configuration shown in FIGS. 1 and 11, for example (However, in FIGS. 9 and 1, the memory 7 shown outside the circuits 77 and 78 in FIGS. 13 to 16)
1 and 72 are shown included in their respective circuits as indicated by memories 30 and 31).

Furthermore, a first pointer 79 and a second pointer 80 are provided for specifying the bit position on the bit string in the memories 71 and 72. Here, the value of the first pointer 79 (bit indicated position) is set to be 1 or more larger than the value of the second pointer 80 (bit indicated position), and the positive and negative coupling coefficients are set to 1 bit each, 2 bits in total. Each time the update is completed, the values of these pointers 79 and 80 are both incremented by 1. 13 to 16, the positions and connection relationships of these pointers 79 and 80 are different. These pointers 79 and 80 serve as shifting means.

First, in the method shown in FIG. 13, the bit at the position indicated by the first pointer 79 is extracted from the memory 71 storing the bit string of the positive coupling coefficient, and the bit string of the negative coupling coefficient is extracted. The second memory from the memory 72 that stores
The bit at the position indicated by pointer 80 is extracted. Using these extracted bits, the new coupling coefficient calculation circuit 7
After calculating the bit of the new positive coupling coefficient by 8, the bit is stored in the bit position indicated by the second pointer 80 in the memory 71, and the new coupling coefficient calculation circuit 7
After calculating the bit of the new negative coupling coefficient by 8, the bit is stored in the bit position pointed to by the second pointer 80 in the memory 72.

In the system of FIG. 14, the second pointer 8 is selected from the memory 71 storing the bit string of the positive coupling coefficient.
The bit at the position indicated by 0 is retrieved, and the bit at the position indicated by the first pointer 79 is retrieved from the memory 72 storing the bit string of the negative coupling coefficient. Using these extracted bits, the new coupling coefficient calculating circuit 78 calculates new positive and negative coupling coefficient bits, respectively, and then stores the bits in the memories 71 and 72 to the second pointer 80.
are stored in the bit positions indicated by .

In addition, in the method shown in FIG. 15, the bit at the position indicated by the first pointer 79 is retrieved from the memory 71 storing the bit string of the positive coupling coefficient, and the bit string of the negative coupling coefficient is extracted. The bit at the position pointed to by the first pointer 79 is also retrieved from the stored memory 72. After calculating new positive coupling coefficient bits by the new coupling coefficient calculation circuit 78 using these extracted bits,
After storing that bit in the bit position indicated by the first pointer 79 in the memory 71, and calculating a new negative coupling coefficient bit by the new coupling coefficient calculation circuit 78,
The bit is stored in memory 72 at the bit location pointed to by second pointer 80.

In the method shown in FIG. 16, the bits at the positions indicated by the first pointer 79 are extracted from the memories 71 and 72 storing bit strings of positive and negative coupling coefficients, and these extracted bits are After calculating a bit of a new positive coupling coefficient using the bit of the new coupling coefficient calculation circuit 78, the bit is stored in the bit position indicated by the second pointer 80 in the memory 71, while After the calculation circuit 78 calculates a new negative coupling coefficient bit, the bit is stored in the memory 72 at the bit position pointed to by the first pointer 79.

Next, a learning example using the method of this embodiment will be explained using a specific experimental example. Here, in a hierarchical neural network that is equipped with the functions of this embodiment and has three layers, and each layer is composed of three neurons, a set of input signals of three input signals and a teacher signal is used.
Teacher signal (1,0,0) →
(1,0,0)(0,1,0) → (0,1
, 0) (0, 0, 1) → (0, 0, 1) were presented 2,000 times for learning, and then each of these three types of input signals was presented 1,000 times. For each presentation, output signals were collected while randomly changing only the bit positions where bits were turned on without changing the total number of on bits in the bit array of positive and negative coupling coefficients. For all of the input signals, an output value distribution is obtained in which the mode is a value close to each teacher signal value.

By the way, as a comparative example, a neural network that is exactly the same as the above experimental example except that it does not have the function of this embodiment, that is, the bit string of the coupling coefficient is not shifted during the learning process, is trained in exactly the same way as the above experimental example. When the output signals were collected in exactly the same manner as in the above experimental example, the output values from the neurons whose output value should be 1 and the output values from the neurons whose output value should be 0 were almost the same average value. The output value distribution becomes wider, and the learning effect is lost.

[0093]

Effects of the Invention Since the present invention is configured as described above, according to the learning method of the invention as claimed in claim 1, since the differential component of the neuron response function due to the internal potential of the neuron is not included, It can also be applied to neural networks in which the differential of the neuron response function cannot be defined because the cell response function is not a monovalent function of the internal potential, or to neural networks in which the internal potential itself cannot be defined. Since it is calculated by calculating only quantities that always take non-negative values, it can be easily applied to hardware that is difficult to express negative values, such as those that treat pulse density as a signal. In particular, according to the second aspect of the invention, learning of the neural network can be performed only by logical operations on pulse trains and thinning operations on pulses, making it easy to implement hardware using digital circuits.

Further, according to the signal processing device of the invention as set forth in claim 3, the functions of the neural network including the self-learning function can be performed in parallel on hardware at high speed, and in particular, the functions of the neural network including the self-learning function can be performed in parallel at high speed. This structure eliminates the problems of temperature characteristics, drift, etc. that occur with analog circuit systems.Furthermore, since the coupling coefficient is stored in memory, it is easy to rewrite and has versatility. .

Furthermore, according to the learning method of the invention set forth in claim 4 or the signal processing device set forth in claim 5, one of the learning
Since the bit string of the excitatory coupling coefficient is shifted by one bit or more relative to the bit string of the inhibitory coupling coefficient in each cycle, the bit string of the excitatory coupling coefficient and the bit string of the inhibitory coupling coefficient are It is possible to eliminate the correlation in the bit arrangement between the two, thereby preventing the learning progress from stopping before reaching the desired level, and to reduce the learning effect of the neural network to fluctuations in the bit arrangement of the coupling coefficient after learning. It has a strong resistance to this and can improve learning ability.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of a neuron showing a first embodiment of the present invention.

FIG. 2 is a schematic circuit diagram showing the basics of signal processing in neurons.

FIG. 3 is a timing chart showing an example of pulse density signal processing.

FIG. 4 is a timing chart showing an example of pulse density signal processing.

FIG. 5 is a timing chart showing an example of pulse density signal processing.

FIG. 6 is a timing chart showing an example of pulse density signal processing.

FIG. 7 is a circuit diagram for processing excitatory/inhibitory connections.

FIG. 8 is a circuit diagram for processing excitatory/inhibitory connections.

FIG. 9 is a circuit diagram for processing excitatory/inhibitory connections.

FIG. 10 is a circuit diagram for generating an error signal.

FIG. 11 is a circuit diagram for calculating the logical sum of error signals.

FIG. 12 is a circuit diagram of a gate circuit for neuron output.

FIG. 13 is a block diagram showing a second embodiment of the present invention.

FIG. 14 is a block diagram.

FIG. 15 is a block diagram.

FIG. 16 is a block diagram.

FIG. 17 is a conceptual diagram showing one unit configuration showing a conventional example.

FIG. 18 is a conceptual diagram of a neural network configuration.

FIG. 19 is a graph showing a sigmoid function.

FIG. 20 is a specific circuit diagram of one neural network.

FIG. 21 is a block diagram showing an example of a digital configuration.

FIG. 22 is a circuit diagram of a part thereof.

FIG. 23 is a circuit diagram of a part thereof.

[Explanation of symbols]

23, 30, 31 Memory

Claims (5)

[Claims] [Claim 1] Let Ti,j be the coupling coefficient between neuron i in a certain layer and neuron j in the next layer in a hierarchical neural network, and let this coupling coefficient Ti,j be a positive component T(+)i,j. The difference from the negative component T(-)i,j is expressed as [Equation 1], the output value from neuron i is yi, and the output sensitivity of neuron j is Z(+)i,j, Z(-)i,j ,
The error signal in neuron j is expressed as δ(+)j, δ(−
)j, then at each step of learning, the quantity ΔT(+)i,j becomes the coupling coefficient T(+)i,j
(T(+)i,j +ΔT(+)i,
j) or the value obtained by adding an inertia term to this value as the new T(+)i,j, and the amount ΔT(-)i,j as [Equation 3] as the coupling coefficient T(-)i,j
(T(-)i,j+ΔT(-)i,j
) or a value obtained by adding an inertia term to this value as a new T(-)i,j. However, the output sensitivity Z(+)i,j, Z(-)i,j
Assuming that the product with respect to n [Equation 4] means taking the product with respect to all neurons n other than neuron i among the neurons that are in the layer to which neuron i belongs and are connected to neuron j. , [Formula 5], and the sum for k [Formula 6] means that the sum is calculated for all neurons k that are connected to neuron j in the layer next to the layer to which neuron j belongs. Then, the error signal δ(+)j,
In the output layer, δ(-)j is calculated by the following equation (7), where dj is the teacher signal, and in the intermediate layer, by the following equation (8). Also, T(+)i,j, T(-)i,j and yi
can take a value greater than 1, divide them by the maximum value of those values and get T(+)i,j ≦1, T
(−) It is assumed that i, j ≦1, yi≦1. 2. In a hierarchical neural network, the excitatory coupling coefficient between neuron i in a certain layer and neuron j in the next layer is T(+)i,j, and the inhibitory coupling coefficient is T(-)i. ,j, the output value from neuron i as y
i, the output sensitivity of neuron j is Z(+)i,j,
Z(-)i,j, the error signal at neuron j is δ
(+)j, δ(-)j, these T(+)
i, j , T (-) i, j , yi , Z (+) i, j
, Z(-)i, j , δ(+)j , δ(-)j are all expressed as a pulse train, and using logical sum, logical product, logical negation of these pulse trains, and thinning operation of pulses in the pulse train, For each step of learning, the pulse train obtained as a result of the logical operation [Equation 9] is transformed into a new T(+
)i,j, and the pulse train obtained as a result of the logical operation [Equation 10] is expressed as a new T(-
) A learning method for a neural network, characterized in that learning is performed by setting i, j. However, the logical sum of two pulse trains X and Y is shown by the symbol X∪Y, the logical product is shown by the symbol X∩Y, and the logical negation of the pulse train X is shown by the symbol ~(X). is denoted by the symbol ∧(X). Also, the logical sum [Equation 11] for n is summed for all neurons n other than neuron i among the neurons in the layer to which neuron i belongs and which are connected to neuron j with an excitatory coupling coefficient. This means that the logical sum [Equation 12] for n is calculated for all neurons n other than neuron i among the neurons in the layer to which neuron i belongs and which are connected to neuron j with an inhibitory coupling coefficient. When defined as meaning taking the sum, Z(+)i,j
, Z(-)i,j shall be calculated using the following equation. In addition, the operation to thin out the pulses in the pulse train This means to perform a logical sum for all neurons k that are connected to neuron j with an excitatory coupling coefficient. and δ(+)j and δ(-)j are defined as the logical OR of all neurons k connected with an inhibitory coupling coefficient, then in the output layer, δ(+)j and δ(-)j are dj, then [Formula 16] In the middle layer, it is calculated by [Formula 17]. 3. A plurality of circuit units that receive input signals and output output signals include one that receives signals from outside the network and one that receives signals from other circuit units within the network; each having at least one or more outputting a signal to the outside of the network,
A hierarchical neural network consisting of digital logic circuits in which these circuit units are connected in a network is provided, and when one circuit unit receives an output signal from another circuit unit as an input signal, weight data is used to weight the input signal. 3. The learning method according to claim 2, wherein a memory for storing coupling coefficients is provided, and variable processing is performed to vary the coupling coefficient value based on a difference between an output signal from a circuit unit outputted to the outside of the network and a signal given from outside the network. A signal processing device characterized in that a coefficient variable circuit using a digital logic circuit is provided inside a circuit unit or outside a circuit unit in a network. 4. A neural network is formed by connecting a plurality of neurons in a hierarchical manner that processes an input signal represented by a bit string using digital logic operations and outputs an output signal represented by a bit string, and one neuron receives input signals from other neurons. When receiving an output signal as an input signal, two types of weight data, an excitatory coupling coefficient and an inhibitory coupling coefficient, are stored as coupling coefficients in a bit string representation for weighting the input signal. 3. A neural network learning method using the learning method according to claim 1 or 2, wherein variable processing is performed to vary the coupling coefficient value stored in the neuron in order to bring the output value from the neural network closer to a desired value. . A neural network learning method, characterized in that, for each cycle of the learning, a bit string of excitatory coupling coefficients is shifted by one bit or more relative to a bit string of inhibitory coupling coefficients. 5. A neural network is formed by connecting a plurality of neurons in a hierarchical manner that processes an input signal expressed as a bit string by a digital logic circuit and outputs an output signal expressed as a bit string. A memory that stores two types of weight data for each connection, an excitatory coupling coefficient and an inhibitory coupling coefficient, as a bit string representation of a coupling coefficient for weighting an input signal when an output signal is received as an input signal. 3. A coefficient formed by a digital logic circuit that performs a variable process of varying the coupling coefficient value stored in the neuron in order to bring the output value from the neural network closer to a desired value using the learning method according to claim 1 or 2. A variable circuit is provided, and a shift means is provided in the coefficient variable circuit for shifting the bit string of the excitatory coupling coefficient by one bit or more relative to the bit string of the inhibitory coupling coefficient every cycle of the learning. Characteristic signal processing device.