JPH0580942A - Electronic computer - Google Patents

Abstract

PURPOSE:To detect whether or not an unspecified number of external storage devices being connected to an electronic computer by providing a means which detects the select signals of the external storage devices by an arithmetic processing part. CONSTITUTION:This electronic computer is provided with the means which detects the select signals of the external storage devices 10 and 12 by the CPU 1. In this case, when the CPU 1 accesses an address space where the external storage devices 10 and 12 are possible mounted once, the CPU 1 can detect the select signals for the external storage devices 10 and 12 which are generated by themselves, so whether the external storage devices 10 and 12 are mounted or not is detected. Namely, the address space for input to and output from the external storage devices 10 and 12 can securely be found with extremely inexpensive components, and consequently all the external storage devices 10 and 12 to which the CPU 1 is connected can securely be detected, so the external storage devices 10 and 12 can be mounted and demounted and proper processing accompanying that can automatically be performed without any special arrangement.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an electronic computer, and more particularly to an electronic computer having a detecting means for detecting attachment / detachment of an unspecified number of external storage devices.

[0002]

2. Description of the Related Art In a conventional method for detecting attachment / detachment of an external storage device, the attachment / detachment of the external storage device is processed by a calculation processing unit (hereinafter referred to as CPU
Or the like) is provided, or the CPU reads and writes data from the external storage device and collates and compares whether or not a predetermined result is obtained to detect attachment / detachment of the external storage device.

[0003]

However, in the conventional technique, the method using a switch increases the cost for the switch and complicates the mechanism. In addition, all the external storage devices that can be mounted must be assumed and the state of the switch must be assigned, so that the flexibility for unexpected expansion is poor.

Further, in the method of reading / writing data and collating and comparing the data, it is necessary to pull up / down a bus line for exchanging data in order to obtain a reliable result. In this case, power consumption is increased. Invite. Further, there is a problem that the read-out data must be surely predicted and a teaching means for this data is additionally required.

Therefore, the present invention solves such a problem, and an object thereof is to realize an electronic computer having a detection means for detecting attachment / detachment of an unspecified number of external storage devices with a simple circuit. The purpose is to do.

[0006]

The electronic computer of the present invention comprises:
A CPU for processing data, a means for generating a selection signal from an address signal generated by the CPU (hereinafter referred to as a decoder), and an unspecified number of external storage devices for detecting selection, and the CPU for generating data. An external computer which has a means (hereinafter referred to as a bus) for transmitting an address to the external storage device and for exchanging data between the CPU and the external storage device corresponding to the address. It is characterized in that the CPU has means for detecting a selection signal.

[0007]

Since the present invention has the above-described configuration, once the CPU accesses the address space where the external storage device may be mounted, the CPU makes a selection for the device itself generated by the external storage device. Since the CPU can detect the signal, it is possible to detect the attachment / detachment of the external storage device.

[0008]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram of an electronic computer according to an embodiment of the present invention. In the figure, 1 is a CPU, 10 is a fixed external storage device which is the minimum necessary for the computer to operate, and 12 is a removable external storage device. The CPU 1 transmits the generated address signal and the control signal of the memory cycle to each external storage device 10 and 12 through the address bus, and transmits and receives the data signal through the data bus 8 with the external storage device that has detected selection by the address signal. I do. In the figure, reference numeral 100 denotes a decoder circuit (hereinafter referred to as a guard decoder) that generates "true" from the input / output upper limit address value. Transistor 11
Then, the load resistance connected to the power supply 5 of the "true" level generates the NOR signal 4 of the selection signal output of the removable external storage device 12, and the latch circuit 3 outputs the NOR signal 4 of "false". , The latch output 2 is set to “true”,
Hold that state. The CPU 1 can monitor the latch output 2. Further, the CPU 1 releases the latch by setting the reset input 7 of the latch circuit 3 to “false”,
Latch output 2 can be "false".

FIG. 2 is an example of a block diagram of the removable external storage device 12. Reference numeral 15 is a data bus, 17 is an address bus, 16 is a decoder circuit, 18 is a selection signal, and 14 is an address bus 17 when the selection signal 18 becomes “true”.
Is a memory element for reading and writing the memory cell at a specific address by the address signal and the memory cycle signal.

FIG. 3 is a timing chart showing a timing example of each signal. Reference numeral 19 is an address signal waveform, 20 is a signal indicating an address validity (hereinafter referred to as an address enable signal) waveform, 21 is a data signal waveform, 22 is a generated selection signal waveform, 23 is a reset input waveform of a latch circuit, and 24 is It is an output waveform of the latch circuit. Reference numeral 26 is a change in the latch output reset by the reset input, and 25 is a change in the latch output set by the selection signal.

FIG. 4 shows an electronic computer system which is an application example of the present invention. Reference numeral 27 is a computer main body including a CPU, a data display means, a data input / output means, a unique external storage device, and a keeper decoder, and 28 is a system bus including an address bus and a data bus. Also system bus 2
Reference numeral 8 also includes a logical sum signal line for the selection signal of each external storage device connected. Reference numeral 30 is a removable memory card, and 29 is a connecting portion between the memory card and the system bus (hereinafter referred to as a memory card socket). The memory card 30 has one or a plurality of storage elements, as shown in FIG. 2, and a decoder that generates a selection signal from an address transmitted to the storage elements. The memory card socket 29 has a built-in means for generating a logical sum corresponding to the transistor 11 of FIG. 1, and transmits a selection signal of the memory card 30 to the computer main body 27. The electronic computer main body 27 has a latch means for the transmitted selection signal, which corresponds to the latch circuit 3 of FIG.

FIG. 5 is a block diagram of the connecting portion. Three
Reference numeral 1 is a switch for teaching an address arrangement uniquely given to each connection portion, and 32 is a subtracter for subtracting the address. The decoder of the memory card connected to the memory card socket uses the subtracted address 3
A selection signal is generated with 3 as an absolute address.

The procedure for detecting the memory card mounting address in this application example will be described with reference to the flowcharts of FIGS. First, FIG. 8 is a subroutine having an argument AD and returning "true" / "false" by determining whether indirect reference reading using the value of AD as an address generates a selection signal of the external storage device (subroutine name is SUB1 And)). First, the latch circuit that latches the selection signal is reset (step 50). Next, indirect reference reading is performed using the AD value as an address (step 5).
1). The latch output is tested (step 52), and if set, "true" is stored in the return value SUB1RET (step 53), and if not set, "false" is stored (step 54), and the subroutine SUB1 is ended. ..
FIG. 7 is a flowchart of a subroutine (subroutine name is SUB2) for obtaining the start address and the end address of the input / output address space of the external storage device after the detection start address is used as the argument STAD. First, the value of STAD is stored in the argument AD of SUB1 (step 55), and SUB1 is called (step 56). If the return value SUB1RET of SUB1 is judged (step 57) and it is "false", the value of STAD is incremented by 1 (step 58) and the procedure from step 55 is repeated.
If “true” in step 57, return value SUB3RE
The value of STAD is stored in T1 (step 59). Next, the value of STAD is stored in the argument AD of SUB1 (step 60), and SUB1 is called (step 61). SU
Determine the return value SUB1RET of B1 (step 62)
If "true", the value of STAD is incremented by 1 (step 6).
3), the procedure from step 60 is repeated. If "false", the value of STAD-1 is stored in the return value SUB2RET2 (step 64), and SUB2 ends. SUB here
2RET1 is the start address of the input / output address space,
SUB2RET2 becomes the end address. FIG. 6 shows input / output address spaces for all external storage devices.
It is a flowchart of the program stored in each line of the array A shown in (a). In the figure, reference numeral 35 is the start address of the address space, and 36 is the data for storing the end address (column 1 and column 2 respectively). First, the detection start address is stored in the variable AA, and 0 is stored in the variable I serving as the row index of the array A (step 65). The value of AA is stored in the argument STAD of SUB2 (step 66) and SUB2 is called (step 67). SUB2R to A _I 1 to SUB2RET1, A _I 2
ET2 is stored (step 68) and I is incremented by 1. If SUB2RET1 is determined (step 69), and the value is other than the address value at which the guard decoder is "true" (hereinafter referred to as guard address value), S is set to AA.
The value of UB2RET2 + 1 is stored (step 70) and the procedure from step 66 is repeated. In step 69, if the value of SUB1RET1 is the guardian address value, the program ends.

This system has four memory card sockets, 10000 ₁₆ , 20000 ₁₆ and 3000 respectively.
It is assumed that address arrangements of addresses 0 ₁₆ and 40 000 ₁₆ are given. Absolute address 01000 _{16 to} 004FFF
Storage elements to perform the reading from address ₁₆ in memory card and absolute address which is mounted 00000 ₁₆ ～03FF
It is assumed that memory cards with memory elements mounted so that they can be read from F16 are connected to the first and third memory card sockets respectively, and the address of the address decoder of the computer is set to address 50000 ₁₆ . It has been done. In the above configuration, the program shown in FIG.
The result of (b) can be obtained in the sequence A.

In this embodiment and the applied examples, the upper limit of the address for detecting the external storage device is obtained by the guard decoder, but in the program, the CPU may always detect the address while monitoring the address. Of course you can.

[0016]

As described above, according to the present invention, it is possible to reliably obtain an address space for inputting / outputting from / to an external storage device by using several inexpensive parts. With this, for example, an unspecified number of manufacturers different from the manufacturer of the electronic computer manufacture and supply the external storage device, or
Even when a program is created and stored in the external storage device and supplied, all the external storage devices to which the CPU is connected can be reliably detected, so that there is no special arrangement for address space allocation. It becomes possible to automatically carry out attachment / detachment and appropriate processing associated therewith.

[Brief description of drawings]

FIG. 1 is a block diagram of a computer according to an embodiment of the present invention.

FIG. 2 is a block diagram of a removable external storage device.

FIG. 3 is a timing chart showing a timing example of each signal.

FIG. 4 is a computer system diagram showing an application example of the present invention.

FIG. 5 is a block diagram of a connection unit.

FIG. 6 is a flowchart of a program for obtaining an input / output address space for all external storage devices.

FIG. 7 is a flowchart of a subroutine SUB2.

FIG. 8 is a flowchart of a subroutine SUB1.

FIG. 9 is a diagram showing an array A that stores the obtained input / output address.

[Explanation of symbols]

 1 CPU 9 address bus 10, 12 external storage device

Claims (1)

[Claims] 1. An unspecified number of external storage devices having an arithmetic processing unit for processing data and means for generating a selection signal for the device itself from an address signal generated by the arithmetic processing unit and detecting the selection. An electronic computer having a means for transmitting an address generated by the arithmetic processing unit to the external storage device and exchanging data between the external storage device corresponding to the address and the arithmetic processing unit, An electronic computer comprising means for allowing the arithmetic processing unit to detect a selection signal of an external storage device.