JPH0575453A - Pll synthesizer - Google Patents

Abstract

PURPOSE:To provide the PLL synthesizer applied suitably to the digital portable telephone system by setting a frequency step small and setting a comparison frequency high. CONSTITUTION:An output of a frequency divider 3 and an output of a 2nd reference oscillator 7 are inputted to a 1st frequency converter 8, which converts a frequency of the output of the frequency divider into a higher frequency than that of the frequency divider 3. Furthermore, an output of a 1st reference oscillator 5 and an output of a 2nd reference oscillator 7 are given to a 2nd frequency converter 6, which converts the frequency of the 1st reference oscillator into a higher frequency than that, and outputs from the 1st and 2nd frequency converters 8, 6 are inputted to a controlled voltage generator 2, and the frequency is compared at a higher frequency than the output frequency of the 1st reference oscillator 5 to reduce a lock-up time. Thus, the PLL synthesizer which requires a high speed lock-up time is obtained by setting the comparison frequency of the PLL synthesizer to a high frequency independently of the frequency step.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a PLL synthesizer device used in a system requiring a fast lockup time with a small frequency step, such as a digital mobile phone system.

[0002]

2. Description of the Related Art PLL which has been generally used conventionally
The synthesizer device is configured as shown in FIG. That is, in the figure, the voltage controlled oscillator 1 is configured so that the frequency of its output 1a can be varied by the control voltage 2a provided by the control voltage oscillator 2. The output 1a of the voltage controlled oscillator 1 is divided by the frequency divider 3 at the set frequency division ratio. The frequency division ratio of the frequency divider 3 can be externally set to an arbitrary value. The output 3a of the frequency divider 3 is connected to one input of the control voltage generator 2. Also, from the reference oscillator 4 for determining the settable frequency step of the PLL synthesizer, the frequency signal 4 equal to the frequency step
a is output and is connected to the other input of the control voltage generator 2. The reference oscillator 4 is composed of a crystal oscillator and has an output 4a.
If a low frequency is required, a frequency divider circuit is provided.

The control voltage generator 2 receives the input signal 3a,
An error voltage corresponding to the phase difference between the input signals 3a and 4a, which is composed of a phase comparator that generates a phase difference signal of 4a and a low pass filter (LPF) that smoothes the phase difference signal and converts it into a DC voltage. 2a is output.

In the PLL synthesizer having such a configuration, the frequency of the output 1a of the voltage controlled oscillator 1 is as follows. That is, when the frequency of the output 4a of the reference oscillator 4 is f _REF and the frequency division ratio of the frequency divider 3 is N, the frequency f _out of the output 1a of the voltage controlled oscillator 1 is

[0005]

[Equation 1]

[0006] By externally setting the frequency division ratio N in the above equation, f _out can be changed at the frequency step f _REF .

[0007]

[Problems to be Solved by the Invention]
In the LL synthesizer, the control voltage generator 2 detects the phase difference between the input signals 3a and 4a, and the frequency component f _REF is removed from the phase difference signal by the LPF to generate the DC voltage 2a. That is, the time constant of the LPF is f
_It is determined by _REF, and the lower f _REF is, the more L
It is necessary to increase the time constant of PF, which results in PLL.
The lockup time of the synthesizer becomes slow. Also,
Since the output frequency step of the PLL synthesizer is also determined by f _REF , if the frequency step is reduced,
There was also the problem that the lockup time would be delayed.

For this reason, such a conventional PLL synthesizer cannot be used in a system such as a digital mobile phone system in which the wireless channel interval is narrow and a fast lock-up time is required. It was

[0009]

In order to solve the problems of the prior art, the PLL synthesizer device of the present invention includes a voltage controlled oscillator in which the output signal frequency changes according to the input control voltage level, A divider for dividing the output of the voltage controlled oscillator, a first reference oscillator for determining the output frequency step of the voltage controlled oscillator, and a mixer for mixing the outputs of the divider and the first reference oscillator. A second reference oscillator for generating a reference frequency signal, one input connected to the output of the divider and the other input connected to the second reference oscillator, and a sum component of the two input frequencies or A first frequency converter that outputs a difference component;
A second frequency converter having one input connected to the output of the first reference oscillator, the other input connected to the output of the second reference oscillator, and outputting a sum component or a difference component of the two input frequencies. And one input connected to the output of the first frequency converter and the other input connected to the output of the second frequency oscillator, and a voltage corresponding to the frequency difference between the two input signals is applied to the voltage controlled oscillator. And a control voltage generator connected to the input of.

[0010]

In the present invention, by inputting the output of the frequency divider and the output of the second reference oscillator to the first frequency converter,
The frequency is converted to a frequency higher than the frequency divider output, and the output of the first reference oscillator and the output of the second reference oscillator are changed to the second output.
Frequency converter converts the frequency to a frequency higher than the frequency of the first reference oscillator, inputs the outputs from the first and second frequency converters to the control voltage generator, and The lockup time can be shortened by performing the frequency comparison operation at a frequency higher than the output frequency.

[0011]

1 to 3 are block diagrams showing a first embodiment of a PLL synthesizer device according to the present invention, in which a voltage controlled oscillator 1 and a frequency divider 3 have the same construction as in the prior art. In addition, the first reference oscillator 5 and the second reference oscillator 7
Is a crystal oscillator similar to the reference oscillator 4 of the prior art.

The output signal 3a from the frequency divider 3 and the output signal 7a of the second reference oscillator 7 are input to the first frequency converter 8, and the sum component of the frequencies of these signals 3a and 7a is output signal 8a. Is output as. The output signal 8a is the signal 3a,
It may be a frequency difference component of 7a. First frequency converter 8
2 is composed of a mixer circuit 10 using a transistor 9 and a bandpass filter (BPF) 11 for extracting only the sum component of the frequencies of the signals 3a and 7a, as shown in FIG. If the frequency of the signal 3a is f _var and the frequency of the signal 7a is f _conv , then 10a in FIG.

[0013]

[Equation 2]

Is output and the center frequency f _{0 of the} BPF 11 is output.
To

[0015]

[Equation 3]

If the component is removed, the sum component output 8a can be output.

By using the configuration of FIG. 4 for the second frequency converter 6 as well, the frequency f _REF of the output 5a of the first reference oscillator 5 and the frequency f _conv of the output 7a of the second reference oscillator 7 are used.
Sum component with

[0018]

[Equation 4]

Is output as the output signal 6a.

The control voltage generator 2 has a structure as shown in FIG. 3, for example. The lockup time of the PLL synthesizer is determined by the time constant of the LPF 12 in the figure. However, the LPF 12 needs to remove the components 6a and 8a serving as comparison inputs from the phase difference signal 13a output from the phase comparator 14 via the charge pump 13.
That is, the lock-up time of the PLL synthesizer depends on the frequencies of the signals 6a and 8a. The higher the frequency, the smaller the time constant of the LPF 12, and the shorter the lock-up time.

By the above operation, the frequency of the PLL synthesizer output 1a becomes

[0022]

[Equation 5]

[0023] This is the same as the output frequency of the prior art, and the frequency step of the PLL synthesizer is f
It becomes _REF . On the other hand, the comparison frequency f _r of the signal 6a input to the control voltage generator 2 is

[0024]

[Equation 6]

Therefore, the lock-up time can be designed by determining the comparison frequency f _r . That is, in this embodiment, the frequency step is set to f _REF.
The lock-up time can be set by f _conv , and these can be performed by selecting the oscillation frequencies of the first and second reference oscillators 5 and 7. Therefore, f _REF is small (for example, 30 kHz), and f _conv
Is set to a large value (for example, 10 MHz), the frequency step is small and P having a fast lock-up time.
An LL synthesizer can be realized.

FIG. 4 shows a second embodiment of the PLL synthesizer device according to the present invention. In this embodiment, a multiplication circuit 15 for multiplying the output signal 3a of the frequency divider 3 is provided,
The output signal 15a of the multiplication circuit 15 is supplied to the control voltage generator 2
Is one of the inputs. Therefore, by setting the oscillation frequency of the reference oscillator 4 and the multiplication factor of the multiplication circuit 15, the frequency step and the lock-up time can be set arbitrarily as in the first embodiment shown in FIG.

[0027]

According to the present invention, the comparison frequency of the PLL synthesizer can be set to a high frequency independently of the frequency step. Therefore, by setting the frequency step small and the comparison frequency high, It is possible to realize a PLL synthesizer device having a narrow channel interval and requiring a high-speed lock-up time like a mobile phone system.

[Brief description of drawings]

FIG. 1 is a block diagram showing a first embodiment of a PLL synthesizer device according to the present invention.

FIG. 2 is a diagram showing a configuration of a frequency converter.

FIG. 3 is a diagram showing a configuration of a control voltage generator.

FIG. 4 is a block diagram showing a second embodiment of the PLL synthesizer device according to the present invention.

FIG. 5 is a block diagram showing a conventional PLL synthesizer device.

[Explanation of symbols]

 1 Voltage Controlled Oscillator 1 2 Controlled Voltage Generator 2 3 Frequency Divider 3 5 1st Reference Oscillator 7 2nd Reference Oscillator 6 2nd Frequency Converter 8 1st Frequency Converter 15 Multiplier Circuit

Claims (2)

[Claims] 1. A voltage-controlled oscillator whose output signal frequency changes according to an input control voltage level, a frequency divider for dividing the output of the voltage-controlled oscillator, and an output frequency step of the voltage-controlled oscillator. And a second reference oscillator for generating a reference frequency signal for mixing the outputs of the frequency divider and the first reference oscillator,
A first frequency converter having one input connected to the output of the frequency divider and the other input connected to the second reference oscillator and outputting a sum or difference component of the two input frequencies; A second frequency converter having one input connected to the output of the first reference oscillator, the other input connected to the output of the second reference oscillator, and outputting a sum component or a difference component of the two input frequencies. And one input connected to the output of the first frequency converter and the other input connected to the output of the second frequency oscillator, and a voltage corresponding to the frequency difference between the two input signals is applied to the voltage controlled oscillator. PLL synthesizer device comprising a control voltage generator connected to the input of the. 2. A voltage-controlled oscillator whose output signal frequency changes according to an input control voltage level, a frequency divider for dividing the output of the voltage-controlled oscillator, and an output frequency step of the voltage-controlled oscillator. And a multiplication circuit for multiplying the output of the frequency divider, one input of which is connected to the output of the reference oscillator and the other input of which is connected to the output of the multiplication circuit. A PLL synthesizer device comprising a control voltage generator connected to an input of the voltage controlled oscillator, the voltage corresponding to a frequency difference between signals.