KR930007103B1 - Lsi of digital freq. syn. for a small size wireless - Google Patents

Abstract

The circuit transimits and receive high-frequency signal used by the oscillator of the portable radio device for short-distance. The circuit comprises the oscillator (1) generating the oscillation signal of 10.2 MHz; the dividing device for a reference signal (fR) of 12.5 KHz; the phase comparator (3) comparing a reference signal (fR) with a feedback signal (fV); the loop after-effect device (4) transforming the phase margin voltage to the DC voltage; the voltage control oscillator (5) generating the frequency (fO), 35.7-41.2 MH; the transpose dividing device (6) inputted by a feedback signal (fO) using the output of a voltage control oscillator (5); the dividing controller (9) to control dividers (6-8) and the channel selecting device (10).

Description

Digital PLL Frequency Synthesizer for Small Radios Large Scale Integrated Circuit

1 is a block diagram showing the system of the digital PLL frequency synthesizer of the present invention.

2 is a detailed circuit diagram of the first comparator phase comparator.

3 is a waveform diagram of each part of FIG.

4 is a response characteristic diagram of a step input of a secondary system loop.

5 is a detailed circuit diagram of the loop filter of FIG.

6 is a detailed circuit diagram of the voltage controlled oscillator of FIG.

7 is an explanatory diagram showing the timing relationship of the FIG.

8 is a bit terminal explanatory diagram for selecting a division ratio of the N, A dividers in FIG.

9 is a block diagram of a channel selector for selecting an operating frequency of FIG.

10 is a detailed block diagram of FIG.

11 is a detailed circuit diagram of FIG.

12 is a detailed circuit diagram of an output stage buffer amplifier of a voltage controlled oscillator.

13 to 15 are waveform diagrams of output frequency measurement of a voltage controlled oscillator.

16 is a transient response characteristic diagram of a voltage controlled oscillator control voltage when switching a channel switch.

* Explanation of symbols for main parts of the drawings

1: oscillator 2: divider

3: phase comparator 4: loop filter

5: voltage controlled oscillator 6: predivider

7: A divider 8: N divider

9: Dispensing controller 10: Channel selection encoder

11: 10/4 encoder 21,22,23: Operating frequency selection code

24,27: Channel select adder 25,28: Carry generator

26: step increase unit 29: N division value generator

30: A division value generator

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a large-scale integrated circuit (PLL) frequency synthesizer that is used as a local oscillator of a short-range portable radio to generate a high frequency signal for transmission and reception, and to generate an intermediate frequency signal so as to obtain an information signal upon reception.

As a local oscillator of a conventional short-range future radio, a crystal-controlled oscillator using a crystal bank is used, but this is accompanied by the hassle of replacing a crystal every time the frequency is changed and re-adjusting using a regulator, and accuracy and stability of the frequency. Since it is mainly determined by the crystal there was a problem that can not maintain a high stability.

In addition, an Incoherent frequency synthesizer has been introduced that can obtain many kinds of frequencies with only a few crystals in order to solve the operational inconveniences and obtain good frequency characteristics. However, the rapid growth of the communication field along with the technological progress in the electronic field has increased the need for a frequency synthesizer that is more accurate and stable than the Incoherent frequency synthesizer, and a coherent frequency synthesizer has been created that can satisfy this demand.

The main difference between the Incoherent and the Coherent Frequency Synthesizer is that the Incoherent Frequency Synthesizer uses many crystal controlled oscillators, while the Coherent Synthesizer uses only one reference source.

On the other hand, the coherent frequency synthesizer has a direct (direct) method and an indirect (direct) method, and the direct method obtains a lot of output frequencies by inputting the frequency generated from one signal source to a plurality of mixers, dividers, multipliers In this way, the circuit configuration becomes bulky and expensive.

In addition, the indirect method uses a phase locked loop for fixing a phase and a frequency of an output signal to a reference signal using a feedback principle. The frequency synthesizer of the direct method is a coherent frequency synthesizer of the direct method. Compared with the simpler circuit, the circuit can be miniaturized and reduced in weight, and the circuit construction cost is low. It is also easy to make each element of the PLL frequency synthesizer into a monolithic IC. It can be suppressed to more than 50dB, and there is almost no problem such as high frequency dispersion disturbance which causes mutual interference especially at high frequency, and the frequency increase interval is relatively wide, about 1-100MHz.

However, this type of frequency synthesizer has a very large pull-in range, the time taken for acquisition depends on the size of misalignment of the voltage controlled oscillator, and the frequency settling time It is relatively slow, and the phase noise is determined by the voltage controlled oscillator and the loop bandwidth. Therefore, the design of the voltage controlled oscillator and the loop filter requires particular attention.

In order to solve the above-mentioned drawbacks, the present invention can select 221 frequencies at 25KHz frequency interval by operating only 9 channel select dip switches for operating frequency 25-30.5MHz of radio. We have created a large scale integrated circuit of a simple structured digital PLL frequency synthesizer that can be used.

As described above, the present invention inputs a 10.2 MHz oscillation signal to a phase comparator using a reference frequency of 12.5 MHz. At this time, the output signal of the voltage controlled oscillator is pre-divided by the control of the frequency dividing controller. After division, feedback is input to the phase comparator, and the phase comparator compares the frequency and phase of the reference frequency input signal and the feedback input signal to detect the error phase voltage, and after the error phase voltage is amplified and filtered through the loop filter, Converted to a DC voltage and configured to control the voltage controlled oscillator, described in detail with reference to the accompanying drawings as follows.

FIG. 1 is a schematic diagram showing a digital PLL frequency synthesizer circuit of the present invention. As shown in FIG. 1, an oscillator 1 for generating a 10.2 MHz oscillation signal and 816 divided by 1816 MHz oscillation signal of the oscillator 1 A phase comparator 2 generating a phase error voltage by comparing a frequency divider 2 generating a reference signal f _R of 12.5 KHz and a frequency and phase of the reference signal f _R and the feedback signal f _V. ), A loop filter (5) for amplifying the phase error voltage output from the phase comparator (3), and converting the filter into a DC voltage, and under the control of the DC voltage output from the loop filter (5), operating frequency. the range of frequencies of 35.7-41.2MHz voltage-controlled oscillator 5, a feedback signal to the voltage-controlled oscillator 5, the phase comparator (3) by dividing the frequency (f ₀₎ that is output from for generating an (f ₀₎ pre-divider applying a _(V f) (6) and a, N frequency divider (7), (8) and said frequency divider (6-8) the The controller consists of a frequency divider 9 and, the A, N frequency divider (7), (8) Channel selection encoder 10 to apply a channel selection signal on to.

Therefore, when the oscillator signal of 10.2 MHz is generated and output from the oscillator 1, when the oscillation signal of 10.2 MHz is generated and outputted, the oscillation signal of 10.2 MHz ₂ is divided by 816 in the frequency divider 2. is output to the reference signal (f _R) of 12.5KHz, the reference signal (f _R) is fed back to be dispensed is fed back from the pre-divider (6) and a, N frequency divider (7), (8) a signal _(V f Phase and frequency are compared in the phase comparator 3, and a phase error voltage is output from the phase comparator 3, and the phase error voltage is controlled to control the voltage controlled oscillator 5 through the loop filter 4. do.

₁),(

₂)에 공통접속하고, 그의 출력단자(

₁),(

₂)신호는 인버터(I₃)(I₄),(I₅)(I₆)를 각각 통해 위상오차전압(øR),(øV)으로 출력되게 구성한다.FIG. 2 is a detailed circuit diagram of the first-phase phase comparator 3, and as shown therein, the reference signal f _R and the feedback signal f _V flip through the inverters I ₁ and I ₂ , respectively. It is connected to the clock terminals CK ₁ and CK _{2 of the} flops FF ₁ and FF ₂ , respectively, and its output terminals Q ₁ and Q _{2 are} connected through the NAND gate ND ₁ . His reset terminal (

₁ ), (

₂ ) common connection and its output terminal (

₁ ), (

₂ ) The signal is configured to be output as the phase error voltages? R and? V through the inverters I ₃ , I ₄ , and I ₅ , I ₆ , respectively.

The phase comparator 3 configured as described above compares the rising edges of the two clock inputs, the reference signal f _R and the feedback signal f _V , and generates phase error voltages? _R and? _V by the phase difference. That is, when greater than the frequency of the reference signal (f _R) of the feedback as a waveform help three separate signals (f _V), or the phase of the feedback signal (f _V) ahead than the reference signal (f _R) a phase error voltage (øV The pulse is changed to the low potential state to generate error information, and the phase error voltage øR remains at the high potential state.

Also, if the frequency of the feedback signal f _V is less than the reference signal f _R , or the phase of the feedback signal f _V is behind the reference signal f _R , the phase error voltage? _R pulse is in a low potential state. Error information is generated by changing to, and the phase error voltage øV remains at a high potential state.

If the frequency and phase of the reference signal f _R and the feedback signal f _V are the same, the phase error voltages øV and øR return immediately after their pulses become low potential only for a short period of time. High potential state.

As described above, the phase error voltages? V and? R output from the phase comparator 3 are amplified and filtered by the loop filter 4, and then converted into DC voltages to control the voltage controlled oscillator 5. In this case, since the frequency 12.5 KHz component of the reference signal f _R may be input to the input terminal of the voltage controlled oscillator 5, the noise band B n may be sufficiently smaller than the frequency of the reference signal f _R 12.5 KHz.

However, to reduce the noise band Bn, the natural frequency omega n must be small, so that the locking time must be long. Therefore, these values should be traded off as appropriate.

4 is a response characteristic diagram for the step input of the secondary system loop. As can be seen, the characteristics of the PLL loop depend on the natural frequency ω n and the attenuation factor ξ.

5 is a detailed circuit diagram of the loop filter 4 of FIG. 1, and as shown therein, the phase error voltages øR and øV of the phase comparator 3 are resistors R ₁ and R ₂ . Are connected to the capacitors (C ₁ ) and (C ₂ ), respectively, and the resistors (R ₃ ) and (R ₄ ) are connected to the inverting and non-inverting input terminals of the operational amplifier (OP ₁ ), respectively. The non-inverting input terminal of the operational amplifier OP ₁ is connected to the capacitor C ₃ via a resistor R ₅ , and the inverting input terminal is connected to its output terminal via a resistor R ₆ and a capacitor C ₄ . The output terminal of the operational amplifier OP ₁ is connected to the control terminal of the voltage controlled oscillator 5, and the values of the resistors R _{1 to} R ₄ and R ₅ and R ₆ are respectively determined. The same setting is made, and the values of capacitors C ₁ , C ₂ and C ₃ and C ₄ are also set to the same.

However, in the PLL loop, the gain of the phase comparator 3, the gain of the voltage-controlled oscillator 5, and the N value of the N divider 8 are values determined by the selected circuit elements and design details. ) Is calculated.

From Figure 1 we can derive the following relationship:

Kø: Gain of the phase comparator (3) (Volt / radian)

F (S): transfer function of loop filter (4)

Ko: Gain (radian / sec / Volt) of the voltage controlled oscillator 5

N _T : NP + A

으로 가정하고, 저항(R₅,R₆)의 값은 r₂로 가정하며, 캐패시터(C₁,C₂),(C₃,C₄)값은 C_c,C로 가정한다.The transfer function is defined as the ratio of the Laplace transform and the Laplace transform of the input signal when all initial values are 0, and the values of the resistors R ₁ -R ₄ are

It is assumed that the values of the resistors R ₅ and R ₆ are r ₂ , and the values of the capacitors C ₁ , C ₂ and C ₃ and C ₄ are C _c and C.

The phase error θe (S) is represented by the following equation,

In this loop, the transfer function B (S) becomes:

If you multiply the denominator of the above equation by S

Becomes

Also, the transfer function F (S) of the loop filter is as follows.

Therefore, if the transfer function F (S) of the loop filter is substituted into the loop transfer function B (S),

However, in the automatic control system, the standard form of the response characteristic equation of the secondary system is S ² (2ξωn) S + ωn ² = 0

Therefore, the natural frequency is ωn

or

Decay rate ξ is

From natural frequency ωn

From the decay rate ξ

It becomes

Using the above two equations, the R and C values of the loop filter are calculated.

Becomes

The 3 dB bandwidth is obtained as follows.

The noise bandwidth Bn is obtained as follows.

here,

to be.

In FIG. 4, when ξ _typ = 1, when ωn.t _s = 5, the response characteristic is set to less than 5% of the input size. Here, if the locking time is designed within 20ms, the following conditions are achieved.

2500 (rad/sec)ωn

2500 (rad / sec)

The operating frequency range of the frequency synthesizer is 35.7-41.2MHz and f _R = 12.5KHz, so N _min , N _max is

The gain k ø of the phase comparator 3 is as follows.

The gain Ko of the voltage controlled oscillator 5 is as follows.

8.86 × 10 ⁶ (rad / sec / V)

Here, r ₁ , r ₂ and C values are obtained as follows.

In this way, the R and C values of the fifth degree loop filter 4 can be selected.

On the other hand, the phase error voltages? _R and? _V input to the loop filter 4 are compared with the frequency and phase of the reference signal f _R and the feedback signal f _V in the phase comparator 3 so that As outputs proportional to the phase difference, these outputs are converted into a steady state DC error voltage having a magnitude equal to the error of the two signals through the loop filter 4 to control the voltage controlled oscillator 5.

In addition, the loop filter 4 performs two functions as follows in the loop.

First, it has interference elimination characteristic by attenuating harmonic signal appearing at the output of phase comparator 2. Second, it provides short Term memory function for PLL system, so that the system is locked out of noise due to noise transient. The signal is quickly recovered by the filter's charging voltage.

Therefore, the loop filter 4 influences the acquisition and transient response characteristics of the PLL by attenuating the harmonic error voltage in the loop, and the reduction of the filter bandwidth affects the system as follows. That is, the acquisition process becomes slower, the pull-in time increases, and the acquisition range decreases.

In addition, the interference cancellation characteristic of the PLL is improved because the error voltage caused by the interference frequency is further attenuated by the loop filter 4, and the transient response characteristic and the PLL response characteristic of the loop with respect to the sudden change of the input frequency within the acquisition range. Is weakened.

In addition, the active loop filter is dropped when a large error voltage is generated in the phase comparator 3, or a pulse clipping phenomenon occurs. This phenomenon occurs because the maximum output voltage of the phase comparator 3 is simultaneously generated with a transient overshoot. do. Thus, the settling time becomes uncertain and eventually increases.

In order to prevent such a phenomenon, the RC low filter is inserted at the front end of the loop filter 4, and the low filter suppresses the transient response characteristics without affecting the characteristics of the loop.

That is, in order to stabilize the loop, the cutoff frequency (ωc) of the RC low pass filter should be at least 5-10 times the natural frequency (ωn), and in order to obtain a better effect, the upper limit frequency of the cutoff frequency (ωc) should be ω _R = It should be lower than 2π.f _R to reduce the reference frequency (f _R ), thereby improving the transient response characteristics of the loop and minimizing the influence of the interference signal.

On the other hand, the cutoff frequency (ωc) of the RC low pass filter is

It is designed to be 10 times or more of ωn = 2.5KHz and lower than ω _R = 2π.f _R = 2π × 12.5 = 78.5KHz. In addition, the voltage controlled oscillator 5 should determine the method in consideration of the oscillation frequency band and phase stability. The VCXO using a crystal oscillator (X-Tal) has a very high phase stability, but the oscillation band is not wide for frequency synthesizer. Since the voltage controlled oscillator is inadequate and the LC tuned oscillator is relatively high in phase stability and the oscillation band can be widened, the voltage controlled oscillator 5 of the present invention is constructed using the LC tuned oscillator as shown in FIG. In the voltage-controlled oscillator 5 of FIG. 6, the oscillation transistor TR ₁ is for high frequency having low noise characteristics, and a power source of 8.4 V and 9.1 V is popular for the power supply terminals Vcc ₁ and Vcc ₂ . The linearity of the oscillation frequency with respect to the voltage V _T depends on the capacitance characteristics of the varactor diodes VD ₁ and VD ₂ and is never linearized. Therefore, it is designed so that the linearized part can be used.

In addition, the voltage controlled oscillator 5 oscillates in the band 35.7-41.2 MHz according to the control voltage V _T , and the oscillation signal is output through the buffer amplifier.

In this way, the signal output from the voltage controlled oscillator 5 is applied to the DBM (Double Balanced Mixer) and the pre-divider 6.

On the other hand, the pre-divider 6 and the A, N dividers 7 and 8 are used to obtain the feedback signal f _v . The pre-divider 6 is a 40/41 divider capable of high-speed operation. to be. The output frequency f _o at this divider 6-8 can be expressed as follows.

f _o = (N + A / P) .Ff _R

= (NP + A) .f _R

If you put ± AP in the above equation,

f _o = (N.P + A + AP-AP) .f _R so

= [(NA) P + A (P + 1)]. F _R

Dispense A times with P + 1 module and N-A times with P module under the condition of N> A.

Therefore, the pre-divider 6 uses a dual-modulus pre-divider which can divide into P and P + 1, and the control divider is N divider 8 and A divider 7 Divided into

The timing relationship of these dividers 6-8 is the same as the waveform diagram of FIG. 7, in the initial state where the input frequency Fin input to the pre-divider 6 starts to be divided in the pre-divider 6 The output of the dispensing controller 9 is in a low potential state as shown in (d) of FIG. 7, and this low potential signal is transposed until the A divider 7 rubs the dispensing by an externally programmed value. The divider 6 divides the input frequency Fin into P + 1, that is, 41. At this time, the divided value is (P + 1) .A. After the A divider 7 finishes dispensing, the N divider 8 starts dispensing with an N-A value, wherein the value of the A divider 7 becomes "0". Here, the value of the N divider 18 is also an externally programmed value.

On the other hand, the latch circuit of the "0" value division controller 9 of the A divider 17 is triggered so that the output of the division controller 9 becomes from the low potential state to the high potential state. ) Has a divider value of P, that is, 40, and the transpose divider 6 dispenses the value of 40 until the N divider 8 finishes dispensing by an externally programmed value.

The value dispensed at this time is (NA) .P. Therefore, the total division value N _t at which the input frequency is divided in the divider 6-8 is

N _t = (P + 1) .A + (NA) .P

= NP + A.

When the N divider 8 reaches the " 0 " state, the A divider 7 and the N divider 8 are preset, and the output of the divider controller 9 is brought back to a low potential state. The pre-divider 6 starts dispensing again with a dispensing value of P + 1, that is, 41, and repeats this dispensing cycle.

On the other hand, N> A relationship should always be established in the divider using the dual-modulus pre-dividing technique. The pre-divider 6 used in the present invention is a 40/41 pre-divider, where f _R = 25KHz. Since N> A relation is not established, let f _R = 12.5KHz.

The N divider 8 is composed of 7 bits and the A divider 7 is composed of 6 bits, respectively. In order to select the division values of N, A dividers (8), (7) according to the frequency,

N _T = 2856-3296

Number of channels = 221

N _T = N.P + A

P = 40

N _min = 71 × 40 + 16 = 2856

N _min = 81 x 40 + 54 = 3296.

Therefore, A divider (7) is 16-54 to _10, and frequency division is enabled, N frequency divider 8 is dispensed when up to 71-81 _10, f _R = 12.5KHz and 25KHz channel spacing is so minute A The period 7 may be increased by 2 ₁₀ .

In consideration of the above conditions, the N, A divisions 8 and 7 are constructed as shown in FIG. Here, the N, A dividers 8 and 7 are as follows.

N _min = 71 ₁₀ = 10 00111 ₂

N _max = 81 ₁₀ = 10 1000 _{1 2}

A _min = 16 ₁₀ = 0 1000 02

A _max = 54 ₁₀ = 11011 02

In the above equation, N ₅ , N ₆ of the N divider 8 are always fixed bit terminals, and the A divider 7 has 16, 18, 20,... Since only even numbers are selected up to 54 ₁₀ , the bit terminal A ₀ of the A divider 7 can be fixed to " 0 ".

As a result, the number of bits to be controlled externally is 5 bits in the N divider 8 and 5 bits in the A divider 7. On the other hand, the bit is controlled using a 9-bit dip switch for channel selection, and the rotary switch is used to select 10 channels at 100 KHz intervals for arbitrary channel selection. The value of the period 7 is increased by eight. The channel selection encoder 10 that satisfies these conditions is configured as shown in FIG.

The channel selector 10 is composed of complex logic gates and divides the N divider 8 according to the input state by the selection of the dip switches DS ₁ -DS ₉ and the rotary switches RS ₀ -RS ₈ . bit terminals (N ₀ -N ₆₎ to 1000111-1010001 _2, a frequency divider 7 frequency division bit terminals (a ₀ -A _5), the value of up to 010000-110110 ₂ are input to the, a divider (7) It should include a logic circuit that increases the value of the A divider 7 by 8 when the external rotary switches RS ₀ -RS ₈ are increased by 100 KHz.

Further, the nine-bit DIP switch (DS ₁ -DS ₉₎ is arranged on the inside of the walkie-talkie, a rotary switch (RS ₀ -RS ₈₎ is arranged on the outside of a small transceiver, the switch (DS ₁ -DS ₉ ), (RS ₉ -RS ₈ ) to select the operating frequency, the relationship between the 9-bit dip switch (DS _1- DS ₉ ) and the operating frequency is shown in Table 1 below, the rotary switch ( RS ₀ -RS ₈ ) uses decimal rotary switches to increase the frequency selected by the dip switches DS ₁ -DS ₉ to ₉₀₀ KHz in 100 KHz steps.

TABLE 1

On the other hand, the frequency f _vco of the voltage controlled oscillator 5 is a value obtained by adding an intermediate frequency ( _{10.7 MHz} ) to the operating frequency as follows.

f _vco = 12.5 (KHz) × N _T

N _T = N.P + A

f _ch = f _vco -10.7 (MHz)

In addition, when the frequency selected according to the operating divider values input to the A, N dividers 7 and 8 is represented by a table, it is as follows.

TABLE 2

10 is a detailed block diagram of the channel selection encoder 10 described above. Here, 11 denotes a 10/4 encoder, and the 4-bit binary value (D ₀ -D ₃ ) is used to convert the operating frequency selection signal (S ₁ -S ₉ ) of the decimal number by the selection of the external rotary switches (RS ₁ -RS ₉ ). It is a kind of BCD encoder that converts into), and 21, 22, and 23 are selected within the operating frequency range of 25-29.6 MHz when the operating frequency is selected over 29.6 MHz by the dip switch (DS ₀ -DS ₈ ). This is the operating frequency selection code. That is, 21 is an operating frequency selection code for converting an operating frequency selection signal (P ₀ -P ₂ ) by a dip switch (DS ₀ DS ₂ ) into a 1 MHz unit selection signal (M ₀ -M ₂ ), and 22 is a dip switch. Operating frequency selection code for converting the operating frequency selection signal (P ₂ -P ₆ ) by (DS ₂ -DS ₆ ) to 100KHz unit selection signal (M ₃ -M ₆ ), 23 is a dip switch (DS ₇ , DS ₈ ) The operating frequency selection code (P ₇ -P ₈ ) is converted into 25KHz unit selection signals (M ₇ , M ₈ ) and output as A division value (A ₁ , A2).

On the other hand, 24 is 10 channels at intervals of 100KHz from the output signal (D ₀ -D ₃ ) of the 10/4 encoder 11 and the output signal (M ₃ -M ₆ ) of the operating frequency selection code unit 22. The channel select adder generates a channel select signal (CS _0- CS ₃ ) that can be selected, and 25 denotes a carry signal (C ₁ ) when the channel in the channel select adder 24 increases by 100 KHz and exceeds 1 MHz. The carry generation unit 26 generates a carry signal C ₁ output from the carry generation unit 25 to the selection signals M ₀ -M ₂ preset by the operating frequency selection code unit 21. In addition, it is a step increase unit generated by the selection signal (X ₀ -X ₂ ) in which the unit of MHz is increased by one step. Further, 27 is because it is binary data of a channel select signal (CS ₀ -CS ₃₎ output from the channel selection addition section 24. The 4-bit channel selection signal (CS ₀ -CS ₃₎ and said carry signal (C ₁ ) is a channel selection adder that generates a selection signal (B ₀ -B ₃ ) that selects 10 channels at 100 KHz intervals, and 28 is a selection signal (B ₀ -B ₃ ) output from the channel selection adder (27). Is a carry generator that generates a carry signal (C ₂ ) when the selection signal is 500 KHz or more, and 29 is a select signal (X ₀ -X ₂ ) output from the step increaser (26) and the carry generator (28). N division value generator for generating N division values (N ₀ -N ₄ ) from the output carry signal (C ₂ ), 30 is the selection signal (B ₀ -B ₃ ) output from the channel selection adder (27) A division value generator that generates A division value (A ₃ -A ₅ ) from.

In order to configure each part as a logic circuit described above, a logic gate should be minimized by using a Boolean function simplification method (Karnaugh Map).

First, if the input and output relationship of the operating frequency selection code 21 is represented by a truth table is shown in Table 3 below.

TABLE 3

Only sets inputs P ₂ -P ₁ to " 101 "," 110 "," 111 " and output M ₂ to " 0 ".

On the other hand, the following functional relation can be obtained from the above truth table.

M ₁ = P ₁

M ₀ = P ₀

If M ₂ is the sum of Minterham,

이 된다.

Becomes

In addition, the input / output relationship of the operating frequency selection code unit 22 is shown in Table 4 below.

TABLE 4

The above truth table should be designed so that the channel selection of 100KHz steps does not exceed 29.6MHz when P ₂ = 1, that is, when the selected operating frequency is 29MHz.

Therefore, when P ₂ = 1, M ₆ should always be "0".

On the other hand, the following conditions can be obtained from the truth table.

M ₄ = P ₄

M ₅ = P ₅

M ₆ can be easily obtained from the above conditions.

When P ₄ and P ₅ are both "1", M ₃ should always be "0".

In addition, considering the conditions applied to the operating frequency selection coder 22, the outputs M ₇ and M ₈ of the operating frequency selection coder 23 can be obtained as follows.

In addition, when the input / output relationship of the 10/4 encoder 11 is represented by a truth table, it becomes as Table 5 below.

TABLE 5

From the truth table above, the function expression is as follows.

In addition, when the input / output relationship of the carry generation part 25 is shown by the truth table, it will become as Table 6 below.

TABLE 6

As can be seen from the truth table above, when the input (S ₃ -S ₀ ) is more than "1010", the output (C ₁ ) becomes "1", so the simplified function from the Karnaugh Map is as follows. Can be obtained.

C ₁ = S ₃ .S ₂ + S ₃ .S ₁

= S _3. (S ₂ + S ₁ )

Alternatively, when the output C ₀ of the channel selection adder 24 is 1, C ₁ = 1, so that

C ₁ = C ₀ + S ₂ (S ₂ + S ₁ )

In addition, when the input / output relationship of the carry generation part 28 is shown by the truth table, it will become as Table 7 below.

TABLE 7

From the above truth table, the following function can be obtained by the simplified method.

C ₂ = B ₃ + B ₂ .B ₁ + B ₂ .B ₀ = B ₃ + B ₂ (B ₁ + B ₀ )

In addition, if the input / output relationship of the step increase part 26 is represented by a truth table, it will become as Table 8 below.

TABLE 8

From the truth table above, the function simplified by the map to the minternities in the output (X ₀ ) is

Similarly, a simplified function of the output (X ₁ ), (X ₂ ) is as follows.

In addition, when the input / output relationship of the N division value generator 29 is represented by a truth table, it becomes as Table 9 below.

TABLE 9

인 것을 바로 알 수 있다. 또, 위의 진리표로 부터 출력(N₄-N₁)에 대한 간소화된 함수식을 구하면 다음과 같이 된다.From the truth table above

It can be seen immediately. Also, from the above truth table, the simplified functional expression for the output (N ₄ -N ₁ ) is as follows.

In addition, when the input / output relationship of the A division value generator 30 is represented by a truth table, it is as shown in Table 10 below.

TABLE 10

From the truth table above, a simplified functional expression for the output (A ₃ -A ₅ ) is given by

When the simplified Boolean function of each part described above is designed as a logic gate, it is configured as in the eleventh aspect.

That is, the 10/4 encoder 11 is composed of NAND gates 101-104, and the operating frequency selection coder 21 is composed of a Noah gate 105 and a NAND gate 106, and an operating frequency selection coder. Numeral 22 denotes a NAND gate 107, an inverter 108, and end gates 109 and 110, and an operating frequency selection coder 23 includes an AND gate 111 and 112.

The carry generator 25 is composed of an ora gate 113, an inverter 114, and NAND gates 115, 116, and the step increase unit 26 is an inverter 117-119 and a NAND gate 120-128. The carry generator 28 includes an oragate 129, an inverter 130, and NAND gates 131 and 132, and the N division value generator 29 includes an inverter 133 and an exclusive noar gate ( 134, 136, ora gates (135, 139), and the end gate 138, the A division value generator 30 is an inverter (140-145, 154) and ora gates (152, 157), exclusive noah gate (153), NAND A gate 146-151, 155, 156, and an ora gate 157 are formed.

Referring to the operation of the channel selection encoder 10 configured as described above is as follows.

The frequency f _o output from the voltage controlled oscillator 5 is given by f ₀ = 12.5 KHz × N _T , so that N _t = 2856 to generate f _o = 35.7 MHz.

However, since N _T = NP + A, when the division value P of the battery divider 6 is 40, N = 71 and A = 16 are given. If the division values (N) and (A) are rewritten in binary, N = 1000111 and A = 010000. Accordingly, in order to generate the final output frequency f ₀ at 35.7 MHz, the frequency selector 10 generates the divided values N = 1000111 and A = 010000 and applies them to the N, A dividers 8 and 7. For example, if f ₀ = 35.7 MHz is set to the frequency specified by the dip switches DS _{1 to} DS ₉ , and 300 KHz is increased from the frequency to generate the final output frequency f ₀ = 36.0 MHz. Explain.

Since the specified frequency is 35.7 MHz, the intermediate frequency 10.7 MHz is subtracted from the frequency, and the operating frequency is 25.0 MHz.

Therefore, as shown in Table 1, the dip switches DS _{0 to} DS ₈ are short-circuited so that the operating frequency selection signals P _{0 to} P ₈ are all at low potential.

In addition, in order to increase 300KHz at the specified frequency, only the rotary switch RS ₃ of the rotary switches RS ₁ -RS ₉ is opened so that only the operating frequency selection signal S of the decimal number becomes a low potential.

As a result, the operating frequency selection signals P ₈ -P ₀ become "0" and the operating frequency selection signals S ₉ -S ₁ become "111111011".

Therefore, at this time, since the high potential signal is output from the NAND gate 106 of the operating frequency selection code unit 21, the selection signals M ₀ , M ₁ , and M ₁ output from the operating frequency selection code unit 21. ₂ ) becomes "0", "0", and "1".

At this time, since the high potential signal is output from the NAND gate 107 of the operating frequency selection code unit 22 and the low potential signal is output from both the AND gates 109 and 110, the operating frequency selection code unit ( The selection signals M ₆ -M ₃ output from 22 become "0" and are applied to the input terminal of the channel selection adder 24.

At this time, the selection signals M ₇ and M ₈ output from the AND gates 111 and 112 of the operating frequency selection coder 23 become low potentials and thus A division values A ₁ and A _2. Will be printed).

On the other hand, since the low-potential operating frequency selection code S ₁ is applied to the NAND gates 101 and 102 of the 10/4 encoder 11, a high potential signal is output to the output side thereof, and thus the 10/4. The output signal D ₃ -D ₀ of the encoder 11 becomes "11" and is applied to the other input terminal of the channel select adder 24. At this time, since the selection signal M ₆ -M ₃ output from the operating frequency selection code unit 22 and applied to the input terminal of the channel selection adder 24 is "0", the channel selection adder 24 is selected. Output signal CS ₃ -CS ₀ becomes " 11 &_quot; which is the output signal D ₃ -D ₀ of the 10/4 encoder 11, and the carry signal of high potential in the channel selection adder 24. (C ₀ ) is not output. Therefore, at this time, since the high potential signal is output from the inverter 114 and the NAND gate 115 of the carry generator 25 and applied to the input terminal of the NAND gate 116, the low potential signal is output to the output terminal thereof. As a result, the carry signal C _{1 of the high potential} is not output from the carry generator 25. Therefore, at this time, since the high potential signals are all output from the NAND gates 120-125 of the step increase unit 26, and the selection signal M ₂ is also in the high residual state, all of the NAND gates 126-128 have low potentials. The signal is output. As a result, the selection signals X _{0 to} X ₂ output from the step increase unit 26 are all at low potential.

In addition, the channel select adder 24 outputs CS ₃ -CS ₀ to " 11 ", and the output signal C ₁ of the carry generator 25 is " 0 " the output signal (B ₀ -B ₃₎ also set to "11" is applied to the carry generating unit 28 and the a frequency division value generating unit 30.

Therefore, at this time, the high potential signal is output from the inverter 130 and the NAND gate 131 of the carry generator 28 and is applied to the input terminal of the NAND gate 132 so that the carry signal C ₂ , which is its output signal, is low. It becomes a potential state and is applied to the N division value generation part 29. Accordingly, the high potential signal is output from the inverter 133 of the N division value generator 29, the high potential signal is output from the exclusive noah gate 134, and the low potential signal is output from the oragate 135. The high potential signal is output from the exclusive noah gate 136, the low potential signal is output from the exclusive ogate 137, and the low potential signal is output from the AND gate 138. The low potential signal is output from the oragate 139.

The output signals of the inverter 133, the exclusive noah gates 134, 136, the oragate 19, and the end gate 138 output as described above are N division values (N ₀ -N ₄ ), respectively. The N division value (N ₄ -N ₀ ) signal is " 111 "

In the above description, since the N division values N ₆ and N ₅ are fixed at " 10 ", the N division values N ₆ -N ₀ are set to " 1000111 ".

In addition, at this time, the high potential signal is output from the inverter 145 and the oragate 152 of the A division value generator 30, and the high potential signal is output from the exclusive noah gate 153 to output the oragate 157. A high potential signal is outputted from the inverter, and a high potential signal is outputted from the inverters 141 and 144 of the A division value generator 30, and the inverters 140, 142, 143 and 154 are outputted. Low potential signal is output from the NAND gate, high potential signal is output from the NAND gates 146, 148, 149, 150, and 151, and a high potential signal is output from the NAND gate 155, and The low potential signal is output from the gate 156. In this way, the signals output from the NAND gates 155, 156 and the oragate 157 are applied as the A division values A ₃ , A ₄ , and A ₅ , and thus the A division values A _5. -A ₃ ) The signal becomes "101". At this time, the output signals M ₇ and M _{8 of the} operating frequency selector 23 are "0", followed by the A division values A ₁ and A ₂ , and the A division values A ₀ . Since the signal is fixed at "0", the A division value (A ₅ -A ₀ ) signal becomes "101000".

As described above, since the N division value (N ₆ -N ₀ ) signal is "1000111", it is "71" as a decimal number, and the A division value (A ₅ -A ₀ ) signal is "101000", so "40" as a decimal number. Becomes Therefore, the total division value N _T is DMS N _T = 71 × 40 + 40 = 2880, and the final generated frequency f ₀ is f ₀ = 12.5 (KHz) × 2880 = 36.0 MHz.

In the above description, the case where the designated frequency by the dip switches DS _{0 to} DS ₈ is 35.7 MHz and the increase frequency by the rotary switches RS _{1 to} RS ₉ is 300 KHz has been described as an example _. It is operated in the same manner as above even when the designated frequency is changed by -DS ₈ ) and the increase frequency is changed by the rotary switches RS ₁ -RS ₉ .

On the other hand, as described above, the output of the oscillation signal generated by the voltage controlled oscillator 5 is divided by the division value according to the channel selection of the channel selection encoder 10, and the output 1 is connected to the double balanced mixer. The input 2 is input to the pre-divider 6 and is divided again. In order to match the outputs of the voltage-controlled oscillator 5 to the input level of each stage, it must be input through a buffer amplifier, and the circuit of this buffer amplifier is constructed as shown in FIG.

That is, the oscillation signal generated by the voltage controlled oscillator 5 is buffered through the first buffer amplifier 31 composed of capacitors C ₁₁ -C ₁₃ , resistors R ₁₂ -R ₁₆ , and transistor TR ₁₁ . The output signal of the first buffer amplifier 31 is connected to the resistors R _17- R ₂₀ and the capacitors C _14- C ₁₆ , the variable capacitor VC, the transistor TR ₁₂ , and the coil L. After the buffered amplified through the second buffer amplifier 32 is output to the output 1 (OUT ₁ ), the output signal of the first buffer amplifier 31 is a resistor (R ₂₁ -R ₂₃ ) and capacitor (C) ₁₇ -C ₁₉ ), the buffered amplified through the third buffer amplifier 33 composed of a transistor (TR ₁₃ ) and is configured to be output to the output 2 (OUT ₂ ). Here, the capacitors C ₁₁ , C ₁₄ , and C ₁₇ are AC coupled capacitors for DC blocking, and the capacitors C ₁₃ , C ₁₅ , and C ₁₈ are for AC bypass.

In the first buffer amplifier 13, the frequency characteristics of the first buffer amplifier 13 are made wide by a feedback circuit of the capacitor C ₁₂ and the resistor R ₁₄ . The difference can be suppressed to 1 dB or less.

In addition, the input base resistors R ₁₇ and R _{21 of} the second buffer amplifier 32 and the third buffer amplifier 33 are resistors for adjusting the output level. You must decide as you measure.

In addition, the variable capacitor VC and the coil L of the second buffer amplifier 32 should be set such that the impedance of the output 1 (OUT ₁ ) is 50Ω, and the resistor R ₁₈ is the frequency band 35.7 to be used. It should be determined by experiment so that the second harmonic component is the smallest within -41.2MHz). In addition, the resistor R ₂₃ of the third buffer amplifier 33 should be set such that the impedance of the output 2 (OUT ₂ ) is about 50Ω.

As described above, the PLL logic gate which occupies the largest part of the digital frequency synthesizer of the present invention can be monolithic integrated circuit.

That is, the phase comparators 3, the N, A dividers 8, 9, the divider 9, the channel select encoder 10, and the like are constituted by logic gates so that they can be integrated into a single collector.

Therefore, a semi-custom LSI, a loop filter (4), a voltage controlled oscillator (5), and a reference frequency of 12.5KHz oscillator (1) forming the PLL frequency synthesizer of the present invention are manufactured as a hybrid integrated circuit, and the input conditions are satisfied. By measuring the output of the voltage-controlled oscillator 5 according to the above, all experimental results such as output level, frequency range, unwanted wave, harmonic, and locking time were obtained as shown in Table 11 below.

TABLE 11

In addition, in the frequency synthesizer of the present invention manufactured as described above, the results of measuring the harmonics of the carrier when the output frequency is 35.7 MHz, 38.7 MHz, and 41.2 MHz are shown in FIGS. 13, 14, and 15, respectively. .

That is, the second harmonic was about 40 dB lower than the carrier level, and the third harmonic was about 55 dB lower than the carrier level. As a result, the harmonic suppression level not only satisfies the -40 dB or less specified in the small radio standard, but also after the output of the frequency synthesizer used as the local oscillator of the small radio passes through the lowpass filter following the final power amplifier stage. Is attenuated by more than 50 dB above the carrier level, and the effect on other communication systems such as interference with other radio equipment can be almost neglected.

In addition, the unwanted suppression level was about -60dB, which was quite satisfactory. In consideration of the interference problem between the pulse signal generated from the PLL logic part and the RF signal, the logic part of the frequency synthesizer and the voltage controlled oscillator 5 are mounted on different hybrid substrates, and sufficient shielding is provided for each module. (Shield) is provided, and excellent performance can be obtained by sufficiently separating the analog signal from the digital signal using separate DC power supplies.

In addition, as a result of measuring the control voltage of the voltage-controlled oscillator 5 during channel switching, it is shown in FIG. 16, which shows switching time and pull-in during channel switching from the lowest output frequency (35.7MHz) to the highest frequency (41.2MHz). ) Showing the characteristics. The measurement results show that the maximum switching time is about 10ms, which is much faster than the initial design target, and the speed is such that there is almost no problem in frequency operation due to channel switching.

In addition, the frequency stability test results showed that the frequency stability of current equipment using crystal oscillator is up to ± 40ppm at low temperature (-40 ℃) and high temperature (+ 70 ℃), and is better than ± 100ppm within the standard of small radio standard. Is satisfying.

Claims (6)

An oscillator 1 for generating an oscillation signal of 10.2 MHz, a divider 2 for dividing the oscillation signal of the oscillator 1 to generate a reference signal f _R of 12.5 KHz, and the reference signal f _R ) And a phase comparator 3 for generating a phase error voltage by comparing the frequency and phase of the feedback signal f _V and the phase error voltage output from the phase comparator 3, and after filtering, converts the voltage into a DC voltage. A loop filter 4, a voltage controlled oscillator 5 for generating a frequency f ₀ of an operating frequency range of 35.7-41.2 MHz under the control of a DC voltage output from the loop filter 4, and the voltage control A frequency divider (F ₀ ) output from the oscillator (5) is applied to the preparatory divider (6) and the A, N dividers (7) and (8) to apply the feedback signal (f _V ) to the phase comparator (3). And a frequency division controller 9 for controlling the frequency divider 6-8 and a channel selection encoder 10 for applying a channel selection signal to the A, N frequency dividers 7 and 8. Digital PLL (PLL) frequency synthesizer for small radios, characterized in that large-scale integrated circuit. 2. The logic circuit of claim 1, wherein the logic circuits of the phase comparator 3, the A, N dividers 7 and 8, the divide controller 9, and the channel select encoder 10 are composed of a single chip large scale integrated circuit. A digital integrated frequency (PLL) frequency synthesizer for a small radio, characterized in that a large scale integrated circuit. 2. A large integrated circuit (PLL) frequency synthesizer according to claim 1, characterized in that the loop filter (4) has its front end composed of two stages of RC low pass filters. 2. A large scale integrated circuit (PLL) frequency synthesizer for small radios as claimed in claim 1, characterized in that the pre-divider (6) is a 40/41 dual-modulus pre-divider which is an ECL element. The method of claim 1, wherein the A, N dividers (7), (8) are each configured to have a 6-bit divided value (A ₅ -A ₀ ) and 7-bit divided value (N ₆ -N ₀ ) Large PLL frequency synthesizer for small radios. Iteoseo to claim 1, wherein the channel selection encoder 10 has a rotary switch (RS ₁ -RS ₉₎ select the decimal operating frequency selection signal (S ₁ -S ₉₎ 2 4-bit binary number by a value of ( D ₀ -D ₃ ) converts the 10/4 encoder 11 and the operating frequency selection signal (P ₀ -P ₈ ) by selection of the dip switches DS ₀ -DS ₈ to 1 MHz units, 100 KHz units, Operating frequency selection code unit 21, 22, 23 for converting into 25KHz unit selection signal (M ₀ -M ₂ ), (M ₃ -M ₆ ), (M ₇ , M ₈ ) The channel selection signals CS ₀ -CS ₃ are added by adding the binary values D ₀ -D ₃ of the 10/4 encoder 11 to the selection signals M ₃ -M ₆ of the frequency selection coder 22. A carry generation unit for generating a carry signal C ₁ when the channel selection adding unit 24 to be outputted and the channel selection signals CS _{3 to} CS ₀ output from the channel selection adding unit 24 are _greater than " 1010 " 25), and a carry signal (C ₁₎ the addition of 1 MHz unit step increase the selection signal (X ₀ -X ₂₎ of the carry generating unit 25 to generate It is selected by adding the carry signal (C ₁₎ of the step increment section 26, and a channel selection signal of the carry generation unit 25 to the (CS ₀ -CS ₃₎ of the channel SELECT in acid addition (24) signals (B ₀ - A channel selection adder 27 for generating B ₃ ) and a carry generator for generating a carry signal C ₂ when the selection signals B ₃ -B ₀ of the channel selection adder 27 exceed " 101 " (28) and the N division value (N ₀ -N ₆ ) from the selection signal (X ₀ -X ₂ ) of the step increase section (26) and the carry signal (C ₂ ) of the carry generation section (28). The generated N division value generator 29, the selection signals B ₀ -B ₃ of the channel selection adder 27, and the selection signals M ₇ , M _{8 of} the operating frequency selection coder 23 are generated. A PLS frequency synthesizer for a small radio set, characterized in that it comprises an A division value generator (30) for generating an A division value (A ₀ -A ₅ ).

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