JPH0575143A - Electrostatic induction semiconductor devices - Google Patents

Abstract

PURPOSE:To provide an electrostatic induction semiconductor device capable of enhancing its serviceability dramatically by reducing on/off time without causing any increase in chip areas or difficult problems in a manufacturing process, cutting gate drive power, improving on-state characteristics and increasing the capacity of main electric current. CONSTITUTION:This is an electrostatic induction semiconductor device which is provided with a source region 6 on a surface portion of a semiconductor substrate on one side in such a fashion that it may be between a cathode region 2 and a gate region 4 while on the other side of the substrate, it is provided with an anode region 3 where a base region 5 is formed between the cathode region 2 and the anode region 3. A cathode electrode 7 is installed in such a fashion that it may be in contact with both the cathode region 2 and the source region 3. A groove 10 is formed on a surface portion of the semiconductor substrate where impurities are implanted into the inner peripheral surface of the groove, thereby forming this electrostatic induction semiconductor device.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a static induction semiconductor device.

[0002]

2. Description of the Related Art Conventionally, a surface gate type static induction semiconductor device used as a switching element has a structure shown in FIG. In the electrostatic induction semiconductor device 80, an n ⁺ type (second conductivity type) cathode region 82 and ap ⁺ type (first conductivity type) gate region 84 are formed on the surface of the n type semiconductor substrate 81 on one side. The region 82 is provided so as to be sandwiched between the gate regions 84. On the other hand, a p ⁺ type anode region 83 is provided on the other side of the semiconductor substrate 81, and the cathode region 8
An n ⁻ -type base region 85 is provided between the anode 2 and the anode region 83. The cathode electrode 87 is formed in the cathode region 82.
However, the anode electrode 88 is provided in the anode region 83 and the gate electrode 89 is provided in the gate region 84 so as to be in contact with each other.

The electrostatic induction semiconductor device 80 is adapted to be turned on / off (conducting / cutting off) by changing the potential barrier on the front surface of the cathode by a voltage signal applied to the gate electrode 89. However, this static induction semiconductor device 80 has drawbacks that the turn-off time is long and the gate drive power at turn-off is large. At the time of turn-off, the holes remaining in the base region 85 are not removed.
Although it enters 4 and disappears, it takes a long time to disappear and a gate current flows with the inflow of holes, but the amount of this current is unexpectedly large. In addition, in order to reduce the contact resistance of the cathode electrode 87 with respect to the cathode region and improve the reliability of the contact, it is necessary to minimize the insulating film and maximize the electrode region, but the gap between the electrodes becomes extremely narrow. High precision micro processing technology is required,
Manufacturing is difficult.

On the other hand, the electrostatic induction semiconductor device 9 shown in FIG.
0 has the advantage that the turn-off time is relatively short and the gate drive power at turn-off is relatively small. In the electrostatic induction semiconductor device 90, the n-type semiconductor substrate 9
1 A p ⁺ -type (first conductivity type) cathode region 92, a p ⁺ -type gate region 94, and an n ⁺ -type (second conductivity type) source region 96 are provided on the surface portion on one side. It is provided so as to be sandwiched between 92 and the gate region 94. On the other hand, a p ⁺ type anode region 93 is provided on the other side of the semiconductor substrate 91, and an n ⁻ type base region 95 is provided between the cathode region 92 and the anode region 93. An anode electrode 98 is provided in the anode region 93, a gate electrode 99 is provided in the gate region 94, and a cathode electrode 97 is provided in the cathode region 92 and the source region 96, respectively. ing.

The electrostatic induction semiconductor device 90 can be regarded as a short-circuited gate type structure in which the gate region on one side and the cathode electrode are short-circuited in the surface gate type electrostatic induction semiconductor device shown in FIG. .. Static induction semiconductor device 90
Also, a potential signal on the front surface of the cathode is changed by a voltage signal applied to the gate electrode 99 to turn it on / off (conducting / cutting off). The vertical type that controls the injection of electrons (carriers) from the source region 96 by changing the potential barrier on the front surface of the source region by the electrostatic induction action of the gate region 94 and forms a main current path that operates using the injected electrons as a base current. A pnp transistor, that is, a vertical pnp transistor including a cathode region (p) 92, a base region (n) 95 and an anode region (p) 93 is turned on / off to perform a switching operation.
Since the holes remaining in the base region 95 at the time of turn-off also flow to the cathode region 92, the accumulated holes disappear relatively quickly, the turn-off time is short, and the holes flowing to the cathode region 92 enter the gate region 94. Since the number of holes is reduced, the gate driving power at turn-off is relatively low.

Further, since the anode-cathode current flows through both the cathode region 92 and the source region 96, it is advantageous in terms of current capacity, and at the time of turn-on, a lateral pnp transistor, that is, a gate region (p) 94. Since the lateral pnp transistor composed of the base region (n) 95 and the cathode region (p) 92 becomes conductive and hole injection can be efficiently performed, it is also advantageous in terms of lowering the on-state voltage.

Further, in the electrostatic induction semiconductor device 90, the cathode electrode 97 extends to the source region 96, and since there is a sufficient electrode area, the contact resistance of the cathode electrode 97 is reduced and the contact reliability is improved. There is also an advantage that the improvement can be realized without requiring highly precise fine processing technology.

[0008]

However, in order to improve the practicability of the electrostatic induction semiconductor device 90, the turn-off time is shortened, the gate drive power is reduced, the on-characteristic is improved, and the main current is reduced. There is a further demand for increased capacity. Of course, in that case, it is also necessary that the contact resistance of the cathode electrode 97 can be reduced and the contact reliability can be improved without requiring a highly precise microfabrication technique.

As one measure to meet these requirements,
In the electrostatic induction semiconductor device 90, there is a method of increasing the pattern of the cathode region 92 to increase the surface area and deepen the depth of the impurity diffusion region. Since the contact area between the cathode region 92 and the cathode electrode 97 is increased, the main current capacity is increased, and at the same time, the property of extracting residual holes during the OFF operation is improved, the turn-off time is shortened, and the gate driving power is also reduced. Further, by making the cathode region 92 deeper, injected carriers from the gate region during ON operation can easily reach and the ON voltage can be reduced, and carry from the anode region 93 can easily reach, improving the ON characteristics. Will be done.

However, increasing the pattern of the cathode region 92 increases the chip area, and increasing the depth of the impurity diffusion region increases the difficulty of the diffusion process and increases the chip area due to lateral diffusion. It cannot be said that this is a countermeasure. In view of the above circumstances, the present invention, without increasing the chip area and the difficulty of the manufacturing process,
It is an object of the present invention to provide a highly practical static induction semiconductor device that can shorten the turn-off time, reduce the gate drive power, improve the ON characteristics, and increase the capacity of the main current all at once.

[0011]

In order to solve the above-mentioned problems, in a static induction semiconductor device of the present invention, a cathode region of a first conductivity type and a gate region of a first conductivity type are formed on a surface portion on one side of a semiconductor substrate. And a source region of the second conductivity type such that the source region is sandwiched between the cathode region and the gate region, and an anode region of the first conductivity type is provided on the other side of the semiconductor substrate. Is a base region of the second conductivity type, and a cathode electrode that contacts both the cathode region and the source region is provided, the cathode region has a groove formed in the surface portion of the semiconductor substrate. It is formed by introducing impurities into the inner peripheral surface of the groove.

The groove in the surface portion of the semiconductor substrate according to the present invention preferably has a depth (dimension) larger than width (dimension). This is because the gate region can be formed in a deep position even if the chip area is small. The electrostatic induction semiconductor device of the present invention is generally a thyristor mode switching drive type element, but is not a mere switching drive type but a transistor mode drive type element for continuously changing the current flowing between the anode and the cathode. May be

If the first conductivity type is p-type, the second
It goes without saying that the conductivity type is n-type, and conversely, when the first conductivity type is n-type, the second conductivity type is p-type.

[0014]

In the electrostatic induction semiconductor device of the present invention, the surface area of the cathode region can be increased without increasing the chip area. Since the entire inner surface of the groove is the surface of the cathode region, the surface area increases by the area of the side surface.And, since the surface area of the cathode region increases, the contact area with the cathode electrode also increases, and the main current capacity increases accordingly. , The residual hole extraction property during the OFF operation is improved, the turn-off time is shortened, and the gate drive power is also reduced.

Further, in the electrostatic induction semiconductor device of the present invention, the cathode region can be reached to a deep position without difficulty of the diffusion process and increase of the chip area due to lateral diffusion. This is because the diffusion process can be omitted for the depth of the groove, and therefore the diffusion process for a long time is not required.
Further, in the electrostatic induction semiconductor device of the present invention, the junction area of the cathode region (boundary area between the cathode region and the base region)
Is also wide. In other words, since the impurities are introduced through a wide diffusion window which is the entire inner surface of the groove, the junction area of the completed impurity diffusion region is widened.

As described above, when the cathode region reaches deep and the junction area is wide, the efficiency of arrival carriers injected from the gate region at the time of ON operation is improved and the ON voltage can be reduced. At the same time, carriers from the anode region can be reduced. Also, the arrival efficiency is improved, and the ON characteristics are improved. Since the cathode electrode is in contact with both the cathode region and the source region, the aluminum layer is not removed in the narrow gap between the cathode region and the source region, and the gap between the gate region and the source region is not removed. Since it is only necessary to remove the aluminum layer, it is not necessary to apply a particularly sophisticated fine processing technique. In this case, in addition, the inconvenience of focus variation when using an optical reading device is eliminated, and the reduction exposure projection device can be effectively used to perform appropriate resist processing and pattern processing without problems.

Further, it is possible to control the electric characteristics by adjusting the depth of the groove independently of the control of the electric characteristics by adjusting the size of the gate region, which is useful in the electrostatic induction semiconductor device of the present invention. Is increasing.

[0018]

Embodiments of the present invention will now be described in detail with reference to the drawings. FIG. 1 shows a main configuration of an electrostatic induction semiconductor device according to an embodiment. The electrostatic induction semiconductor device of the embodiment has p ^{+ +} on the surface portion on one side of the n-type semiconductor substrate 1.
The cathode region 2 of the type (first conductivity type), the gate region 4 of the p ⁺ type, and the source region 6 of the n ⁺ type (second conductivity type) are provided. These regions 2, 4, 6 are formed such that the source region 6 is sandwiched between the cathode region 2 and the gate region 4. On the other hand, a p ⁺ type anode region 3 is provided on the other side of the semiconductor substrate 1, and n is provided between the cathode region 2 and the anode region 3.
^- it has become a type of the base region 5. The anode region 5 is n
It is formed by diffusing p-type impurities from the back surface side of the type silicon wafer or stacking an n-type silicon layer on the p-type silicon layer. The impurity concentration in the base region 5 is 10 ¹³
cm ⁻³ to 10 ¹⁴ cm ⁻³ , and the impurity concentration in other n-type or p-type high-concentration impurity regions is about 10 ¹⁹ cm ⁻³ to 10 ²⁰ cm ⁻³ . The thickness of the base region 5 is determined in consideration of electrical characteristics such as breakdown voltage and on-voltage and workability at the time of manufacturing, but is about 100 μm in the case of breakdown voltage of 1000V class. When the electrostatic induction semiconductor device is viewed from above, for example, a strip-shaped cathode region is surrounded by a frame-shaped gate region, and a source region is provided between them. Of course, the strip-shaped gate region may be surrounded by the frame-shaped cathode region with the source region therebetween.

Further, this electrostatic induction semiconductor device is provided with an anode electrode 8 which contacts the anode region 3 and a gate electrode 9 which contacts the gate region 4, respectively, and contacts both the cathode region 2 and the source region 6. A cathode electrode 7 is provided. Each electrode 7-
9 is made of aluminum, for example. The cathode region 2 is formed by forming a groove 10 on the surface portion of the semiconductor substrate 1 and introducing impurities into the inner peripheral surface of the groove 10, and the cathode electrode 7 is formed on the inner surface of the groove 10. The contact with the cathode region 10 has various advantages as described above. The depth of the groove 10 is about 1
It is about 0 μm.

Since the cathode electrode 7 has a structure that contacts both the cathode region 2 and the source region 6, the aluminum layer is left without being removed in the narrow gap between the cathode region 2 and the source region 6 and the gate region 4 is not removed. Since it is only necessary to remove the aluminum layer in the gap between the source regions 6,
In particular, it does not require the application of advanced fine processing technology. As shown in FIG. 2, the cathode electrode 17 is not in contact with the source region 6, and a source electrode 18 that is in contact with the source region 6 is provided separately. Both electrodes 17 and 18 are electrically connected outside the device. With such a configuration, it is necessary to apply a high-level fine processing technique, and it is difficult to apply a reduction exposure projection apparatus, and it is difficult to perform appropriate resist processing.

The present invention is not limited to the above embodiment. For example, in FIG. 1, one in which p and n are reversed is another example.

[0022]

As described above, in the electrostatic induction semiconductor device of the present invention, the surface area of the cathode region can be increased without increasing the chip area, so that the main current capacity is increased and the turn-off time is shortened. And the gate drive power can be reduced, the cathode region can be reached to a deep position without difficulty of the diffusion process and the increase of the chip area due to the lateral diffusion, so that not only the ON characteristics can be improved, It is very practical and useful because it does not require the application of a highly sophisticated fine processing technique in the manufacturing process and the electric characteristics can be easily controlled by adjusting the depth of the groove.

[Brief description of drawings]

FIG. 1 is a cross-sectional view showing a configuration of a main part of an electrostatic induction semiconductor device of an example.

FIG. 2 is a cross-sectional view showing a main configuration of a static induction semiconductor device of a reference example.

FIG. 3 is a cross-sectional view showing a main part configuration of a conventional static induction semiconductor device.

FIG. 4 is a cross-sectional view showing a main part configuration of another conventional static induction semiconductor device.

[Explanation of sign]

 1 semiconductor substrate 2 cathode region 3 anode region 4 gate region 5 base region 6 source region 7 cathode electrode 10 groove

Claims (1)

[Claims] 1. A first conductivity type cathode region, a first conductivity type gate region, and a second conductivity type source region are provided on a surface portion of one side of a semiconductor substrate between a cathode region and a gate region. It is provided in a sandwiched form, and the first side
An electrostatic induction semiconductor device comprising a conductive type anode region, a second conductive type base region between the cathode region and the anode region, and a cathode electrode being in contact with both the cathode region and the source region. ,
The electrostatic induction semiconductor device is characterized in that the cathode region is formed by forming a groove on a surface portion of the semiconductor substrate and introducing impurities into an inner peripheral surface of the groove.