JP3271501B2 - MOS type GTO thyristor and driving method thereof - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor switching element having a MOS gate (metal-oxide film-semiconductor structure gate) and capable of controlling the conduction and interruption of a main current by a potential applied to the gate. GTO thyristor.

[0002]

2. Description of the Related Art As semiconductor switching elements using silicon, elements suitable for various application fields have been developed and commercialized. For example, in the field of information processing and telecommunications, IGBTs and C-MCTs are used for LSIs integrating several thousand elements, main circuits of industrial general-purpose inverters, and the like.
(Complementary MOS Contro
GTO (Gate) is used in the field of handling large electric power of trains and electric power systems.
(Turn-Off) thyristor, light-ignition thyristor, and the like. While research and development to further improve the performance of these devices is progressing, research and development to integrate specialized semiconductor switching devices in each field from the manufacturing stage has been developed, and You are on the stage.

[0003] The merits of integration are the use of highly controlled and controlled semiconductor manufacturing technology, high uniformity and reliability of products, and no need for a process of assembling individual parts, which leads to a reduction in total cost. It is smaller and can save space.

[0004] These features are intended to expand the application field without any modification, and one of them is a driver IC for a plasma display, which is expected to be applied to a large-screen wall-mounted television. The basic specifications of this driver IC, the breakdown voltage V _d of the output circuit side 200V, rated current I _d is 400mA
The power supply voltage of the digital circuit part controlling this is 5V
That is. Further, an output stage corresponding to the number of scanning lines on the display screen is required, and with the increase in screen size and definition, further higher withstand voltage and current of the driver IC are required.

As a key technology for integrating an output circuit and a digital circuit, an SOI (Serial) having an insulating layer disposed inside is used.
miconductor On Insulator or Silicon On Ins
There are two points: dielectric isolation technology using a substrate, and adoption of a voltage-driven bipolar device. The inventor has previously devised a driver IC for a plasma display using a horizontal MOS thyristor in Japanese Patent Application No. 7-99057.

FIG. 17 is a schematic sectional view showing the characteristics of the lateral MOS thyristor. Hereafter, unless otherwise specified, p or n is added before the name of a region or the like, and the majority carrier responsible for electric conduction is a region of a p-type semiconductor which is a hole, and n is an electron. And the region of the type semiconductor. First, the SOI in which the n region 21 is laminated on the support substrate 34 via the oxide film 35 is formed.
In order to separate a certain portion of the n region 21 from the other portion by using the substrate, a groove reaching the oxide film 35 inside the SOI substrate is provided, and the oxide film 22 is filled in the groove.
An isolation region is formed. On the part of the surface layer of the separated n region 21, n ⁺ buffer region 31 and p
A base region 27 is provided. Further, a p-emitter region 32 is formed on a surface layer in the n ⁺ buffer region 31, and an n-emitter region 28 is formed on the surface layer of the p base region 27 without protruding from the region. An anode electrode 33 is provided on the surface of the p emitter region 32, and a cathode electrode 30 is provided on the surface of the n emitter region 28. Also, on the exposed surface of the p base region 27,
A gate electrode 25 made of polycrystalline silicon is arranged via a gate oxide film 24 which is a thin insulating film.

A MOS thyristor having such features is referred to here as a Base-Floating-Thyri.
It is referred to as a sto (hereinafter abbreviated as BFT). A pnpn thyristor is formed inside the semiconductor from the anode electrode 33 to the cathode electrode 30. The trigger current for switching the BFT from the cutoff state to the conduction state can be supplied by the following method. The potential of the gate electrode 25 (hereinafter, referred to as gate potential) with respect to the potential of the cathode electrode 30 (hereinafter, referred to as cathode potential).
Is changed to a positive potential, electron-hole pairs are generated in the surface layer of the p base region 27 located below the gate electrode 25. The generated electrons are attracted to the positive potential of the gate electrode 25 and stop at the surface, forming a channel 37. On the other hand, holes move from the p base region 27 to the n emitter region 28.
And flows into the cathode electrode 30. The hole current, that is, the gate displacement current works as a trigger current of the thyristor. In order to secure a sufficient trigger current, the p base region 27 has a structure that does not directly contact the cathode electrode 30.

The inventor has also devised a driver IC for a plasma display using another improved BFT in Japanese Patent Application No. 7-21508. This improved BFT
18 is shown in FIG. In the improved BFT, in order to overcome the drawbacks caused by the structure of the conventional BFT, FIG.
The electrode arrangement shown in FIG. 8 is provided, and a small depletion-type p-channel MOSFET 38 is also provided. Since the p-channel type MOSFET 38 is a depletion type and is normally turned on, the hole current in the p base region is short-circuited to the cathode electrode to improve the noise immunity except when the BFT is to be turned on. Therefore, malfunction can be avoided. On the other hand, when the BFT is to be turned on, the p-channel MOSFET 38 is turned off and effectively used as a trigger current to keep a low on-voltage. With the above device configuration, the device size is W × L = 200 μm × 500 μm,
Anode current I _A = 400 mA [current density 400 A / c
m ² ] was achieved.

The above-mentioned BFT and the improved BFT are non-self-extinguishing types which cannot be switched from a conductive state to a cut-off state by a gate signal, but this is not a problem in application to a plasma display. It had been. However, this is an AC discharge (hereinafter, AC discharge).
Abbreviation) type. DC discharge (hereinafter abbreviated as DC) type plasma displays have also been developed.
In this case, since the electrodes inside the discharge tube are in contact with the internal gas, a discharge maintaining current flows after the discharge.
When the above-mentioned BFT and the improved BFT are used, there is no way to limit the magnitude of this current, and there is an extremely high risk of destruction of the element due to heat generation or destruction of the internal electrode of the discharge tube. As a countermeasure, when the operation of a device in which a load resistor is simply connected in series to limit the current was examined, the following problem was found.

One is by inserting a load resistor.
The change in voltage at the discharge terminal of the panel becomes slow. In order to avoid this, the firing voltage must be substantially increased. In addition, the variation in characteristics among panel manufacturing lots is relatively large, and it is necessary to frequently adjust the value of the load resistance, which makes it difficult to mass-produce the assembly line. (Since MOSFETs and IGBTs having pentode characteristics are adjusted by MOS resistance, such a problem does not occur.) Therefore, as a result of examining various proposed MOS-type thyristors, Emitter-Switched- T
HERISTOR (hereinafter abbreviated as EST) was found to be effective. The first reason is that, since it is a thyristor, the size of the element can be made smaller than that of the IGBT, and similarly to the IGBT, the current can be limited by the MOS gate potential. However, it has a pentode characteristic.

There are few examples of developing ESTs as horizontal devices, and it was expected that optimal design would be difficult. J. Other: IEEE E
Electron Device Lett. , 13 volumes,
12, pp. 615-617, 1992], a low breakdown voltage n-channel type M is provided on the cathode side.
An OSFET was formed and its characteristics were examined.

FIG. 19 is a sectional view of a prototype horizontal EST. There is an n region 41 formed on the p substrate 40 by epitaxial growth. A next diffusion region is formed selectively away from the surface. A p base region 47 and an n ⁺ buffer region 51 having relatively deep diffusion are formed. A high-concentration p ⁺ contact region 59 and an n source region 49 are arranged adjacent to a part of the surface layer of p base region 47, and n emitter region 48 extends over a relatively wide region several μm away from n source region 49. Is provided. In the surface layer of n ⁺ buffer region 51, p emitter region 52 is arranged. P base region 47 is connected to p substrate 40 via p ⁺ isolation region 60 which is a deep diffusion region. p ⁺ contact region 59 and n source region 4
A cathode electrode 50 is provided which is a metal electrode which has a good electrical contact by being in common contact with the surface of the anode electrode 9. Similarly, an anode electrode 53 is provided on the surface of the p emitter region 52.
Is arranged. On the continuous upper surface extending over the n-emitter region 48 / p-base region 47 / n-region 41 and the n-emitter region 48 / p-base region 47 / n-source region 49, a polycrystalline structure is formed via a thin gate oxide film 54 as an insulating film. Silicon first gate electrode 45 and second gate electrode 46
And these two gate electrodes are generally connected to one gate terminal and have the same electrical potential. The structure in which the p ⁺ isolation region 60 is provided using the p substrate 40 merely forms a junction-separated structure, and is not a structure unique to EST.

The operation principle of the EST is shown in FIGS.
(A) and (b) show. First, in FIG. 20, the gate voltage Vg is applied to the gate electrodes 45 and 46 from the state where the potential of the cathode electrode 50 is set as the reference potential and the potential of the anode electrode 53 is kept at the element breakdown voltage Vd. First gate electrode 45
Base region 4 located below and second gate electrode 46
The surface portion of 7 is inverted, and a first channel 57 connecting the n region 41 and the n emitter region 48 and a second channel 58 connecting the n source region 49 and the n emitter region 48 are formed. Then, electrons are drawn from the n source region 49 to the high potential on the anode side and flow into the n region 41 through the two channels 57 and 58 (→). Since the pn junction between p emitter region 52 and n ⁺ buffer region 51 is biased in the forward direction, holes flow from p emitter region 52 into n region 41 (→). Since holes are minority carriers, they recombine with surrounding electrons, but many fall into a depletion layer extending between the reverse-biased p base region 47 and the n region 41 and flow into the p base region 47 (→
). Most holes cross the p base region 47 and flow into the cathode electrode 50 via the p ⁺ contact region 59. The anode current I _A flowing through the circuit can be controlled by an electronic current through the two channels 57 and 58.
This state is almost the same operation state as the IGBT. (Hereinafter, referred to as IGBT mode.) As you increase the anode current I _A, the hole current is also increased through the p base region 47. A voltage drop occurs due to the current flowing in p base region 47 and the resistance component in p base region 47. Then, the n emitter region 48 and the p base region 4
7 has a built-in potential (approximately 0.7
Beyond V), some of the electrons flowing through the first channel 57 are injected from the n-emitter region 48 into the p-base region 47 and recombine with holes. When this recombination becomes remarkable, the electrons flowing through the first channel 57 disappear as shown in FIG. 21A, and all the electrons flowing into the n emitter region 48 flow into the p base region 47 (→), and most of them are positive. Recombines with the hole and transitions to the thyristor operating state. (Comparing the case where the current flows through the channel resistance of the first channel 57 and the case where the built-in potential required for the recombination is ensured, it depends on which consumes less energy.) The main thyristor is turned on. This state is called an EST mode. Since the current flowing through the recombination is equal to the magnitude of the electron current passing through the second channel 58, it can be controlled by the applied gate voltage.

In the case of the EST mode, since most of the entire current passes through the second channel 58, by turning it off, the device can be switched to the cutoff state. Therefore, E
ST is a voltage-controlled self-extinguishing thyristor having pentode characteristics similar to IGBTs. Further, when a large current flows, a phenomenon occurs in which electrons are injected from the n source region 49 into the p base region 47, and a parasitic thyristor composed of the n source region 49 / p base region 47 / n region 41 / p emitter region 52 is formed. It works. This is a latch-up state of the EST, and as shown in FIG. 21B, the electrons flowing through the second channel 58 have already disappeared, and the state cannot be controlled by the gate voltage. How to turn off the parasitic thyristor
The supply from the power supply must be cut off, and the thyristor becomes a non-self-extinguishing type thyristor (a two-terminal thyristor similar to the BFT). FIG. 22 is a schematic current-voltage characteristic diagram of the EST. .
The horizontal axis anode-cathode voltage V _AK, the vertical axis represents the anode current I _A, the parameter is a gate voltage V _g. For example, when the gate voltage is low, the voltage drop in the p base region is not sufficient, and there is no transition to the thyristor, so that the IGBT mode is maintained. When the gate voltage is increased, a portion where the current-voltage curve bends in the middle (a portion circled in the figure) appears, and a current larger than the IGBT can flow. Also, the magnitude of the current can be changed by changing the magnitude of the gate voltage.
This state corresponds to the EST mode. The current value at the boundary where the main thyristor operates (the boundary between the EST mode and the IGBT mode) will be referred to as the EST holding current here.

[0015] Ideally, even in the EST mode, I
Like the GBT, it is desired to secure a region where only a constant current flows even when the anode-cathode voltage V _AK is increased. However, even in the vertical EST, which is being developed,
There has been no report that an element having such a current-voltage characteristic has been developed. The total current is limited by the maximum current density of the second channel 58 in FIG. Since the second channel 58 is a low breakdown voltage MOSFET sandwiched between the high concentration n source region 49 and the n emitter region 48, the current density can be higher than that of the first channel 57. Devices that exceed the characteristics cannot be made.

When the point indicated by the symbol x in the current-voltage characteristic curve shown in FIG. 22 is reached, the parasitic thyristor is turned on, and jumps to another characteristic curve in which a large current flows while the V _AK drops rapidly.
This is a latch-up state. The current value at this time is referred to as a latching start current (x mark). When the latch-up occurs once, it cannot be controlled by the gate signal unless the anode current is reduced below the holding current (indicated by Δ in the figure: holding current of the parasitic thyristor).
In the application to the drive circuit of the DC plasma display, as described above, use in the latch-up state must be avoided.

[0017]

A variety of designs have been tried to produce a horizontal EST, but various problems have surfaced. [Problem 1] In order to switch from the IGBT mode to the EST mode, it is necessary to secure a voltage drop of about 0.7 V due to a hole current flowing through the p base region immediately below the n emitter. 47 must be set high or the length L _emit of the n emitter region 48 must be increased. However, the p-base resistance is M
Because of the threshold design of the OS, no significant change is possible, so there is no other way to achieve a substantial effect than to lengthen L _emit . In our horizontal EST prototype, L _{em it} = 20μ
m, the mode does not shift to the EST mode.
Some elements shift to T mode and others do not.
So, it has definitely moved. (However, Vg = 5V, room temperature) This is the drift length L which is a dimension for determining the element withstand voltage.
d (the distance between the p base and the p emitter), so that about three times the BFT,
The device area is about twice as large as the IGBT.

[Problem 2] The rated current I _A = 400 up to about 15 V to 20 V without turning on the parasitic thyristor.
Although it is desired to secure mA (current density is 300 to 400 A · cm ⁻² ), the prototype device has only 10 V at most and latches up. The literature was investigated, but it seems that even in the vertical structure under development, the latch-up occurs when the current density becomes so high. As described above, it is considered that most of the entire current has to pass through the lateral MOSFET, which increases the channel resistance and causes the parasitic thyristor to latch.

In view of the above problems, an object of the present invention is to provide a thyristor MOS type GTO thyristor which has a small device area and a large latching current and can be turned off.

[0020]

Means for Solving the Problems In addition, a vertical EST or the like has been prototyped. However, when the switching operation is repeated, local heat generation causes the prototype EST to be destroyed (cathode electrode side) or a gate electrode. When the potential of
Problems occurred when the parasitic thyristor was turned on (especially when the inductive component on the load side could not be ignored).

The present inventors have repeated studies using a two-dimensional device simulator with reference to literatures in order to analyze these phenomena and extract optimal design conditions. For example,
The relationship between the latching current and the width L _emit of the n emitter region,
The relationship between the latching current and the impurity concentration in the p-base region and the latch-up phenomenon of the parasitic thyristor were analyzed. As a result, the following was found regarding the conditions for securing the basic operation of the EST and the conditions for achieving a small horizontal EST.

First, as for the relationship between the latching current and the width L _emit of the n-emitter region, if the length of L _emit becomes longer, the IGBT
It was found that the latching current for switching from the mode to the EST mode was reduced. When L _emit is 3-4 times,
The latching current becomes 1/2 to 1/3. To control the anode current I _A, was changed gate voltage of the lateral MOSFET optionally, although a larger value from a small value is controllable, reducing the current value of a certain limit, the parasitic thyristor latching Sometimes. If the channel length of the MOSFET is shortened to suppress this phenomenon,
Gate voltage dependence is reduced. In order to increase the latching start current of the parasitic thyristor (reduce h _FE ), it is necessary to extend the high-concentration p region as much as possible to the end of the n source region. However, the similar phenomenon cannot be basically eliminated only by increasing the limit current value as a whole. Therefore, this seems to be an intrinsic property of EST. The lower the gate potential, the lower the latching start current. (Since the channel resistance and the resistance of the p-base region + the resistance of the high-concentration p-region are connected in parallel, the channel resistance increases and the current decreases. , Current flows.
Therefore, the voltage rises and the parasitic thyristor turns on. )
Accordingly, it has been found that in order to reduce the current, it is necessary to limit the current of the main thyristor and adjust the gate potential so as to stabilize this state.

In order to solve the above problems, the MOS of the present invention
The type GTO thyristor includes a second conductivity type base region, a second conductivity type emitter region, and a second conductivity type emitter region formed separately from each other on a part of a surface layer on one main surface of the first conductivity type semiconductor layer. An anode electrode provided in contact with the surface of the first conductive type source region formed on a part of the surface layer of the second conductive type base region; and a first conductive type source region of the second conductive type base region. A first conductivity type emitter region formed on a surface layer in a portion close to the second conductivity type emitter region; a cathode electrode provided in contact with the surface of the first conductivity type source region; On the gate oxide film on the surface exposed portion of the second conductivity type base region sandwiched between the one conductivity type semiconductor layer and the side having the end on the second conductivity type base region and near the second conductivity type emitter region A first gate electrode extending to Shall have a second gate electrode provided on the second conductivity type base region a gate oxide film on the exposed surface of the sandwiched conductive source region and a first conductivity type emitter region.

In this case, basically, a thyristor structure having a second conductivity type base region at a floating potential is formed, and a gate electrode is disposed above the surface of the thyristor via an insulating film. Will be. When the potential of the gate electrode is changed, a hole-electron pair is generated on the surface of the second conductivity type base region during generation and recombination. Among them, the electrons form a channel in the surface layer of the second conductivity type base region immediately below the gate electrode, and the holes are spread in the second conductivity type base region while the electrons are supplied from the first conductivity type emitter region. Rejoin. This recombination current has sufficient capacity as a trigger current for the main thyristor, so that the thyristor can be turned on. Further, a lateral MOSFET that connects the first conductivity type source region and the first conductivity type emitter region that does not directly contact the external electrode can be formed to limit the current during conduction. By combining these, a small MOS GTO thyristor having a self-extinguishing ability is formed.

In particular, it is preferable that the second conductivity type base region is formed so as to surround the second conductivity type emitter region. By arranging the anode electrode at the center and the cathode electrode at the outer periphery in this way, a horizontal MOSFE
Since the channel width below the gate electrode of T can be widened, the saturation characteristics can be achieved in a wide range, and the current density in the p base region can be made relatively small, there is an effect of reducing current concentration.

The two-conductivity-type base region formed on a part of the surface layer on one main surface of the first-conductivity-type semiconductor layer and the part of the surface layer on the second-conductivity-type base region are separated from each other. The formed first conductivity type source region, the first conductivity type emitter region, the cathode electrode provided in contact with the surface of the first conductivity type source region, and another main surface side surface of the first conductivity type semiconductor layer A second conductivity type emitter region formed in part of the layer, an anode electrode provided in contact with a surface of the second conductivity type emitter region, and a first conductivity type emitter region and the first conductivity type semiconductor layer; A first oxide layer provided on the gate oxide film on the exposed surface of the second conductive type base region and having an end on the second conductive type base region and extending to a side close to the first conductive type semiconductor layer; Sandwiched between the gate electrode, the first conductivity type source region and the first conductivity type emitter region. Or it may have a second gate electrode provided on the second-conductivity-type base region of the exposed surface on the gate oxide film was.

With such a configuration, the on-operation can be performed by the first gate electrode and the off-operation can be performed by the second gate electrode, and the emitter region of the second conductivity type is formed on another main surface. Good utilization efficiency of the area of the semiconductor substrate. Then, it is assumed that the MOSFET having the structure located in the second gate electrode and the lower layer portion is conductive in a thermal equilibrium state and is a depletion type which is turned off by a gate signal.

By doing so, before the main thyristor shifts to the conducting state, the channel of the lateral MOSFET has already been sufficiently opened, and it can be operated reliably. Another MOS-type GTO thyristor of the present invention includes a second conductive type base region, a second conductive type emitter region formed on a part of a surface layer on one main surface of a first conductive type semiconductor layer, and a second conductive type emitter region. An anode electrode provided in contact with the surface of the second conductivity type emitter region, and a second electrode formed on a part of the surface layer of the first conductivity type semiconductor layer between the second conductivity type base region and the second conductivity type emitter region. A common conductivity type well region, a first conductivity type source region formed on a part of a surface layer of the second conductivity type well region, and a common region on the surface of the second conductivity type well region and the first conductivity type source region. A first conductive type emitter region formed on a part of the surface layer of the second conductive type base region; a first conductive type emitter region and a first conductive type source region. Table of the second conductivity type base region and the first conductivity type semiconductor layer sandwiched It shall have a gate electrode formed on the gate oxide film on the surface of the exposed portion and the second conductivity-type well region.

The MOSFET portion including the second conductivity type base region and the first conductivity type emitter region which are not in direct contact with the external electrode, the second conductivity type well region and the first conductivity type semiconductor region source region. By performing the ON operation in the MOSFET portion including the second conductivity type base region and the first conductivity type emitter region,
The off operation can be performed in the MOSFET portion including the second conductivity type well region and the first conductivity type semiconductor region source region.

In particular, it is assumed that the second conductivity type well region is formed so as to surround the second conductivity type base region. A second conductivity type well region that is in such good electrical contact with the cathode electrode is formed on the anode electrode side, and a voltage substantially applied between both electrodes is applied to the second conductivity type p well region. By providing the depletion layer extending between the semiconductor regions of the first conductivity type, the surge current flowing into the base region of the second conductivity type can be reduced when the device is in the cutoff state, so that the surge current caused by disturbance such as surge noise can be reduced. Malfunction can be prevented. In addition, when the element is switched off, the current path of the thyristor is cut off by the depletion layer which spreads. Therefore, the rejection of minority carriers is prompt, and re-latch-up due to re-injection is unlikely to occur, thus improving the switching characteristics. Is done.

Preferably, the diffusion depth of the second conductivity type well region is deeper than that of the second conductivity type base region. In this case, the depletion layer between the second conductivity type p-well region and the first conductivity type semiconductor region when the element is in a cutoff state is likely to expand. Also, a part of the second conductivity type well region may be located below the second conductivity type base region.

In this case, the same operation as in the preceding paragraph is produced. The second conductivity type base region and the second conductivity type well region are connected by a second conductivity type connection region having a lower impurity concentration than the second conductivity type base region below the gate electrode and a shallower diffusion depth. It can also be. By doing so, the second conductivity type base region does not become a floating potential.

As a driving method of the MOS type GTO thyristor as described above, the same control signal is applied to the first gate electrode and the second gate electrode. By doing so, only one gate power supply is required, and the circuit can be simplified. Also, after giving a signal to the second gate electrode, a signal is given to the first gate electrode to delay generation of a channel below the first gate electrode from generation of a channel below the second gate electrode, and further to the first gate electrode. It is also possible to apply a reverse signal to the second gate electrode after giving the reverse signal to the above, thereby delaying the disappearance of the channel under the second gate electrode from the disappearance of the channel under the first gate electrode.

By doing so, the channel of the lateral MOSFET has already been sufficiently opened before the main thyristor shifts to the conducting state, and the device can be reliably operated.

[0035]

Embodiments of the present invention will be described below with reference to the drawings. [Embodiment] FIG. 1 is a sectional view showing the basic components of a MOS GTO thyristor according to a first embodiment of the present invention (hereinafter, referred to as an embodiment).

The n region 1 forming the MOS type GTO thyristor of the present invention is laminated on a supporting substrate 14 via an oxide film 15 in order to avoid interference of other elements formed on the semiconductor layer on the same supporting substrate. The n-type semiconductor layer is formed so as to be electrically separated from the region for forming other elements by the oxide film 2. The n region 1 is made of n-type silicon and has a specific resistance of 10 to 10.
40 Ω · cm, 3 to 30 μm in thickness, and oxide film 15 has a thickness of 0.5 to 3 μm. These values are determined according to device specifications such as withstand voltage.

On the surface of the n region 1, the thickness is 0.5 to 1 μm.
m and a thickness of 20 to 100 n
m, which is covered with the gate oxide film 4. Various impurities are introduced into portions not covered with the field oxide film, and a structure described below is formed on the surface layer of the n region 1. On the left side of the figure, a p base region 7 in which boron is diffused by a depth of about 2 to 5 μm is formed. Since boron is diffused by heat treatment, it also spreads in the lateral direction,
The p base region 7 also extends below the field oxide film 3 and the gate oxide film 4.

A part of the surface layer of the p base region 7 has a high concentration n emitter region 8 having a depth of at most 0.2 to 0.5 μm and an impurity concentration of 10 ²⁰ cm ^-3 or more. N source region 9 is arranged. N emitter region 8 is arranged closer to n region 1 than n source region 9. On the right side of the drawing, an n ⁺ buffer region 11 in which phosphorus is diffused is formed, and a p emitter region 12 formed by diffusion of boron is formed therein. These diffusion depths and impurity concentrations are determined according to the voltage-current characteristics of the thyristor.

On the surface of p base region 7 to the right of n emitter region 8 (closer to the exposed surface of n region 1), first gate electrode 5 of polycrystalline silicon is provided via gate oxide film 4. And a part thereof extends to above the field oxide film 3. However, the first gate electrode 5 has the n emitter region 8
, And stops on the p base region 7.
On the surface of p base region 7 sandwiched between n emitter region 8 and n source region 9, second gate electrode 6 is provided via gate oxide film 4. This second gate electrode 6
May extend slightly above n emitter region 8 and n source region 9. First gate electrode 5 and second gate electrode 6
Are connected in a cross section (not shown) and are kept at the same potential. (In some cases, the first gate electrode 5 and the second gate electrode 6 may be driven independently of each other.) On the surfaces of the p emitter region 12 and the n source region 9, a metal ( Generally, Al-Si-Cu)
The anode electrode 13 and the cathode electrode 10 are electrically in good contact with each other.

The boron concentration in the p base region 7 depends on the gate acid
Thyristor operation is ensured in consideration of the thickness of the passivation film 4 etc.
Has been adjusted to do. For example, the gate oxide film 4
In the case where the thickness is 30 nm,
The surface concentration of iodine is 1-3 × 10 ¹⁷cm^-3And the second gate
Immediately below the electrode 6, 2 to 7 × 10¹⁶cm^-3Good for
No.

In the case of a normal EST, IGBT, or the like, a channel must be formed in a surface layer immediately below by a voltage applied to the gate electrode. Therefore, as shown in the embodiment of FIG. It does not extend below the oxide film. However, in the present invention, it is not an absolutely necessary condition that the p base region 7 be disposed below the field oxide film 3. Also, normal EST
In the case of an IGBT or the like, the cathode electrode is in common contact with the p-base region and the n-emitter region, which are p-type regions. However, in the MOS GTO of the present invention, the cathode electrode 10 is It must not be in contact with n emitter region 8. This is not a problem because it can be realized only by adjusting the opening at the time of impurity ion implantation with a photoresist mask.

The MOS transistor according to the present invention having the basic configuration shown above
A type GTO thyristor is formed, and each electrode is connected to a digital circuit or an output terminal formed on another n region by a metal wiring. As a manufacturing method of the present invention, a standard LSI
Since it is only necessary to adjust each impurity introduction range using a resist mask or an LDD structure using a process technology,
It is possible to proceed at the same time as the digital circuit process whose conditions have already been determined.

FIGS. 2A and 2B are diagrams for explaining the operation principle of the MOS type GTO thyristor of the embodiment of FIG. First, in FIG. 2A, a power supply 61 is a DC power supply, and a discharge tube of a DC plasma display is assumed as a load 62 here. When no anode current flows, a capacitor and a constant current are used. Is flowing, it is assumed to be equivalent to the resistance. Power supply 61
Through the load 62 connected in series from the anode electrode 13
Is applied, and the cathode electrode 10 is grounded. The depletion layer spreads from the pn junction between the p base region 7 and the n region 1 due to the voltage between the anode and the cathode.

In this state, a positive voltage _Vg is applied to the first gate electrode 5 and the second gate electrode 6 with respect to the cathode electrode 10. Since this voltage _Vg is a control signal from a digital circuit, it is at most about 5V. At this time, an inversion layer 17 is formed on the surface layer of the p base region 7 below the first gate electrode 5. Since the first gate electrode 5 is located only halfway above the p base region 7, the inversion layer 17 does not become a channel. The electrons forming the inversion layer 17 are supplied from a hole-electron pair generated by a carrier generation / recombination process near the surface of the p base region 7. The generated electrons of the hole-electron pair are capacitively coupled to the positive charges accumulated on the first gate electrode 5 side, and thus are fixed to the inversion layer 17 as they are. Flows in the direction of.

In the conventional EST or IGBT, holes can flow from the p base region to the cathode electrode via the p contact region. However, in the MOS thyristor of the embodiment, the holes always exist between n and n. It must be recombined with the electrons jumping out of the emitter region 8 or the n source region 9. Since recombination with electrons from the n-source region 9 is not preferable, a sufficient channel 18 is formed below the second gate electrode 6. With the above-described boron surface concentration, the low breakdown voltage lateral MOSFET formed in the same portion is of a normally-on depletion type, so that holes generated immediately below the first gate electrode 5 The ratio of recombination with electrons from the n-emitter region 8 increases.

The flow of electrons that could not be recombined is accelerated in the depletion layer extending from the pn junction between p base region 7 and n region 1 and flows toward anode electrode 13. n
The emitter region 8 / p base region 7 / n region 1 is npn
Transistors are configured, and the impurity concentration is 1
0 ²⁰ or more / 10 ^{16-10 18/10 15} or less (however, the unit is cm ^-3), since has become a bipolar transistor having a high h _FE (current amplification factor), generated by the generation and recombination process It can be considered that a small hole current was amplified to a large electron current. The electrons flowing through the n region 1 play the role of the base current of the pnp transistor composed of the p base region 7 / n region 1 / p emitter region 12, and this is repeated to make the thyristor conductive [FIG. b)).

FIG. 3 shows the MOS GTO of the embodiment of FIG.
The dimensions near the cathode electrode 10 of the thyristor [FIG.
(A)] is compared with a conventional EST [FIG. (B)] and an improved BFT [FIG. (C)]. The contact width Lc between the cathode electrode and the n-source region, the drift length Ld related to the device withstand voltage, and the gate electrode width Lg were 10 μm, 30 μm, and 2 μm, respectively, and each device was designed the same. As is apparent from FIG.
In case of OS type GTO thyristor or EST, improved BF
Compared to T, two gate electrodes and an n-emitter region are required, so that the size increases by 5.8 μm and 32 μm, respectively. In particular, in the case of EST, as described above, the length of the n-emitter region is required to be as large as 30 μm. Therefore, when an arrangement of comb-shaped electrodes such as the improved BFT of FIG. Therefore, the MO of the embodiment
In the S-type GTO thyristor and the EST, the electrodes are preferably arranged concentrically.

FIG. 4A is an electrode arrangement of the MOS type GTO thyristor of the embodiment of FIG. 1, and FIG. 4B is a sectional view taken along line BB '. In the plan view of FIG. 4A, the structure below the cathode electrode 10 and the anode electrode 13 whose ends are indicated by thick lines is shown as being transparent. The contact portions between the hatched gate electrodes 5 and 6 and the surface of the semiconductor substrate indicated by dotted lines, the diffusion regions indicated by thin lines, and the like are seen. The outside of the double gate electrode is the first gate electrode 5, and the inside is the second gate electrode 6. The line between the double gate electrodes is one end of n emitter region 8. Of course, portions where the gate electrodes 5, 6 and the cathode electrode 10 overlap are insulated with an insulating film interposed therebetween. The gate electrode inside the double gate electrode is the gate electrode for the MOSFET. A cathode electrode 10 is provided at the center, and an anode electrode 13 is provided so as to surround it. The outer ring is the n region 1 where the MOS type GTO thyristor is formed.
Is an oxide film 2 that insulates and separates.

In the cross-sectional view of FIG.
It can be seen that a p-drain region 16 of the OSFET is provided, a p-base region 7 is formed outside the p-drain region 16 and a p-emitter region 12 is formed outside the p-base region 7. A p-channel MOSFET comprising a p-drain region 16, a p-base region 7 and a gate electrode thereover is a normally-on depletion type, which is intended to ensure noise immunity as in the improved BFT shown in FIG. It is.

In the MOS type GTO thyristor of this embodiment, the width W of the device was 155 μm. To match the device area with the improved BFT, the length L of the device was set to 645 μm. Similarly, in the case of the EST, a prototype was produced with W = 180 μm and L = 555 μm.
FIG. 5 shows the current-voltage characteristics of the prototype example. The horizontal axis anode-cathode voltage V _AK, the vertical axis is the anode current I _A, the parameter is a gate voltage V _g. FIG. 9 is a characteristic diagram obtained by resetting the gate voltages to 3 V, 4 V, and 5 V after setting the time for raising the gate voltage V _g from 0 V to 5 V to 0.1 μsec, similarly to the BFT. Unlike improved BFT, the value of the gate voltage V _g was reconfigured, it is possible to vary the anode current I _A. When V _g = 5 V, the latching start current is 39
5 Acm ^-2 (V _AK = 10.3 V). That is,
The rated current is almost reached.

In the case of the improved BFT shown in FIG.
= 200 μm, L = 500 μm, and the anode current I _A =
A rated current of 400 A · cm ⁻² (V _AK = 2.1 V) could be secured with a low on-voltage. In the case of EST, the anode current I _A = 280 A · cm ⁻² (V _AK = 8.
At 6 V), the parasitic thyristor was turned on. In order to satisfy the rated value by EST, about three times the area was required as described above. (In the case of a highly implanted bipolar element, it is difficult to calculate the device area for obtaining the rated current from the current density of the small element by proportional calculation.) FIG. 18 having a comb-shaped electrode arrangement The improved BFT has the largest area of actual thyristor operation among the above three devices, so that the rated current can be achieved with a low on-voltage. On the other hand, in the case of the MOS type GTO thyristor and the EST of the embodiment, since the thyristor operation area is small and a MOS resistance component is added, the ON voltage increases. In particular, the EST has a large area of the n-emitter region so as to shift to the EST mode. However, the thyristor operation works only at the end of the n-emitter region, and therefore the device area must be increased. all right. (In the case of the vertical EST, it contributes to the thyristor operation in the surface of the n-emitter region, but in the case of the horizontal type, it can be said that the efficiency of area utilization is poor because only the end portion is used.) The MOS type GTO thyristor of the embodiment having the characteristic prevents the current from flowing indefinitely in the application to the DC type plasma display,
Further, it is optimal because MOS gate driving can be performed with a small area.

In the above example, the first gate electrode 5 and the second gate electrode 6 are connected and driven by the same signal. However, in some cases, the two gate electrodes 5 and 6 may be driven independently of each other. It may be. When the MOS GTO thyristor having such a configuration is to be fired, a signal is first applied to the second gate electrode 6, a signal is applied to the first gate electrode 5 after the channel 18 is formed, and the inversion layer 17 is applied. If formed, it functions similarly to the above. In such a case, the impurity concentration of the p base region 7 immediately below the two gate electrodes 5 and 6 may be the same, which facilitates manufacturing.

[Embodiment] In the MOS type GTO thyristor of the embodiment, when the switching operation is repeated, a parasitic thyristor may be turned on or an element may be destroyed in some cases. This phenomenon is a common problem, which is also seen in ESTs prototyped for comparison.

In order to investigate the cause of this problem, the surface temperature of the element was measured using a surface temperature measuring device utilizing infrared rays. A normal element is not suitable for such observation because its surface is covered with a metal electrode having good heat conductivity. Therefore, a sample was prepared in which the silicon surface was easy to observe via an interlayer insulating film or the like with a minimum metal wiring pattern. or,
The switching conditions were such that a resistive load was connected at the rated current and voltage, and the pulse width, number of times, and duty were selected under conditions where the phenomenon was easy to observe.

As a result, it was found that the temperature of the second gate electrode 6 on the side of the n-emitter region 8 and at the curved portion was more likely to rise than the others. Since the same portion has a shape that spreads in a fan shape toward the anode electrode 13 side, the current is:
It will flow into a curved lateral MOSFET with a short channel width. Therefore, it is considered that the current density is higher than others and heat is easily generated. When the temperature rises, the firing condition of the thyristor is alleviated, so that the latch-up easily occurs, and it is considered that the above-described problem has occurred.

Usually, in such a case, a structure in which the thyristor or MOSFET in the curved portion does not function is adopted. However, in the case of having a concentric electrode structure as shown in FIG. So we can't take it. If the cause of element destruction is also due to this curved structure, concentric electrode arrangement is not suitable for practical use, and 200 V
MOS type GTO thyristor of ~ 600V is IGBT
Can be expected to be inferior.

Therefore, the present inventors changed the load from a resistive load to a capacitive load (50 pF) and maintained Vg = 3 V after applying a trigger gate signal of 5 V, so that the parasitic thyristor always operates under the condition. The switching operation was repeated, and similar observations were made. Such a condition is equivalent to the operation state of the AC type plasma display, and since the parasitic thyristor operates immediately, the temperature rise due to current concentration of the lateral MOS is considered to be slight. The result is that the temperature rise is kept low, and the temperature distribution unevenness of the entire device is
(In this evaluation, the switching conditions were adjusted so that the in-plane temperature variation appeared remarkably.
Although a simple comparison is not possible, in the previous evaluation, the temperature difference was 5 ° C.
In contrast, the switching of the parasitic thyristor was 2 ° C. or less. ). 150 times the load capacity
The peak current was set to pF and a little more than twice the rated current was allowed to flow. As in the case of the highest temperature in the curved portion, the device was not destroyed.

From this, it can be determined that the thyristor portion is at a level that can withstand the current concentration, and the main cause of the above-mentioned problem is that the current density of the lateral MOSFET is increased only in the curved portion, and heat is generated due to the increase in parasitic current. It was concluded that thyristor latch-up and device destruction occurred. Therefore, without changing the element area,
In order to increase the channel width of the FET, a structure in which a cathode electrode and a gate electrode are arranged on a concentric outer peripheral portion and an anode electrode is provided inside.

FIG. 6A is a plan view of a MOS type GTO thyristor according to a second embodiment of the present invention (referred to as an embodiment), and FIG. 6B is a cross-sectional view taken along the line CC '. In the plan view of FIG. 6 (a), the electrode below the end indicated by a thick line is transparent and the structure below the electrode is shown. The hatched gate electrodes 5 and 6 and the contact portions with the semiconductor substrate surface indicated by the dotted lines are seen. The outside of the double gate electrode is the second gate electrode 6, and the inside is the first gate electrode 5. As shown in this figure,
The cathode electrode 10 can be extended above the gate electrode via an insulating film. An anode electrode 13 is provided at the center, and a cathode electrode 10 is provided so as to surround it. In the lower right and left corners of the figure, the p-channel MOSFET p
The electrode contact of the drain region 16 can be seen.

In the sectional view of FIG. 6B, it can be seen that the p-emitter region 12 is formed at the center and the p-base region 7 is formed outside the p-emitter region 12. In this section, a p-channel MOS
The p drain region of the FET is not seen. Thereby, the lateral MOSF which is curved as compared with the case of the embodiment shown in FIG.
The channel width of the ET has increased 2.5 times (the radius of curvature has been increased from 22 μm to 55 μm). In addition, the depletion-type p-channel MOSFET may be arranged at the corner of the element, so that the layout design is facilitated.

FIG. 7 shows the current-voltage characteristics of the device of the embodiment. Compared with FIG. 5, the following differences are observed. First, when Vg = 3V, IA = 110 _A · cm ⁻²
Although the influence of the MOS resistance appeared from the vicinity, in FIG.
The effect is seen from around I _A = 250 _A · cm ⁻² . As described above, a large current flows with a low on-voltage as a whole. Also, the difference between the current which can be passed in the same V _AK at Vg = 3V and 5V is, in the case of FIG. 5, there were about 200A · cm ^-2, 7, anode current by about 100A · cm ^-2 and the gate voltage The difference between them became smaller. Furthermore, V _AK when the latching start current, that there was about 10V, in case of arranging a cathode electrode and a gate electrode on an outer peripheral portion was improved wider range indicating approximately 18V next saturation characteristics.

When a switching operation test was carried out on the device of the embodiment having improved characteristics, no problems such as turning on the parasitic thyristor and, in some cases, destruction of the device occurred. This is an effect of increasing the channel width of the lateral MOSFET and consequently keeping the current density of the device low. Therefore, even in a horizontal EST based on the same principle, characteristics can be improved by the same effect.

In the MOS type GTO thyristor of the embodiment, since the EST and the trigger mechanism are different, the increase in the device area can be small. In addition, in order to secure a wide saturation characteristic area and to operate the element reliably, a lateral MOS
The FET is of a normally-on depletion type, and is located on the outer periphery including the cathode electrode in the case of concentric electrode arrangement so that a wide channel width can be secured at the same time. According to the present invention, a MOS-type GTO thyristor that solves [Problem 1] and [Problem 2] described in the problem can be realized.

[Embodiment] FIG. 8 is a sectional view showing the basic components of a MOS GTO thyristor according to a third embodiment of the present invention (hereinafter, referred to as an embodiment). This example is a so-called vertical element in which two main electrodes of a GTO thyristor are formed on different main surfaces of a semiconductor substrate. That is, the p-base region 7 and the n-emitter region 8 and the n-source region 9 therein are formed in the surface layer on one side of the n-region 1 in the same manner as in the embodiment. On the other side, an n ⁺ buffer region 11 and a p emitter region 12 are formed. The first gate electrode 5 and the second gate electrode 6 are provided as in the embodiment. The same applies to the cathode electrode 10. The anode electrode 13 is in contact with the surface opposite to the cathode electrode 10. These diffusion depths and impurity concentrations are determined according to the voltage-current characteristics of the thyristor.

The first gate electrode 5 and the second gate electrode 6 are connected in a cross section (not shown) and are kept at the same potential. (In some cases, the first gate electrode 5 and the second gate electrode 6 may be driven independently of each other.) In this case, a curvature portion where the p emitter region 12 and the p base region 7 face each other There was no current concentration and there was a large amount of latch-up capability.

[Embodiment] In the embodiment and the first embodiment, a first gate electrode, a second gate electrode and a depletion type p-channel MOSFET are used for operating the device.
And three gate electrodes are required. These are necessary for generating the trigger current, controlling the anode current, and avoiding malfunction in the cutoff state, respectively. As can be seen from the electrode arrangement in the plan views shown in FIGS. 4 and 6, the gate electrode has a complicated shape. Therefore, there is a problem that layout design and condition setting of impurity introduction are complicated. This is the same as in the case of the EST, but also leads to the loss of the degree of freedom in optimizing the element design.

A MOS GT having another structure capable of eliminating the complexity of the embodiment and improving the switching speed
O thyristor was devised. FIG. 9 is a sectional view of a MOS type GTO thyristor according to a fourth embodiment (hereinafter, referred to as an embodiment) of the present invention. Portions having the same function as in the embodiment of FIG. 1 are denoted by the same reference numerals. The differences from the embodiment will be mainly described. A p-well region 19 is formed on the side closer to the p-anode region 12 of the p-base region 7 formed on a part of the surface layer of the n-region 1 and separated from the p-base region 7. Although the n emitter region 8 is formed in the surface layer of the p base region 7 in the same manner, the n source region 9 is the p well region 19
Is formed inside. From n emitter region 8 to p base region 7, n region 1, p well region 19, n source region 9
The gate electrode 5 is provided on the gate oxide film 4 over the surface of the substrate. Further, a cathode electrode 10 is provided in common contact with the surfaces of n source region 9 and p well region 19. The major difference from the embodiment is that the second gate electrode is eliminated and the gate electrode 5 has both functions of the first gate electrode and the second gate electrode of the embodiment. The point is that the n source region 9 that has been inside the 7 has been moved into the p well region 19, and that the cathode electrode 10 is also in contact with the surface of the p well region 19.

The surface concentration of the p well region 19 depends on the cathode concentration.
The part in contact with the electrode 10 is 10²⁰cm^-3That's it,
Immediately below the gate oxide film 4, 10¹⁷
cm ^-3(However, the thickness of the gate oxide film is about 30
nm). This value corresponds to the gate oxidation of p base region 7.
It is equal to or slightly higher than the impurity concentration just below the film 4 (at most 5 ×
10¹⁶cm^-3Degree) lower. In addition, p-well area
The arrangement and shape of the region 19 are as shown in FIG.
The arrangement is closer to the p anode region 12 than to the p region 7.

FIGS. 10A and 10B are diagrams for explaining the operation principle at the time of turn-on in the embodiment. Since the gate electrode 5, the cathode electrode 10, and the lower part thereof are important, a cross section of the same part is shown, but it is assumed that the anode electrode and the lower part structure are present on the right side not drawn. First, in FIG. 10A, the potential of the cathode electrode 10 is set as a reference potential, and the potential of the gate electrode 5 is changed from 0V to 5V. Positive charges are supplied to and accumulated in the gate electrode 5 from the gate power supply 63. In order to balance the positive charges, electrons are accumulated in the surface portions of the p base region 7 and the p well region 19 immediately below the gate electrode 5 to form a channel 18 having a reversed polarity. Electron sources are considered to be from the generation of hole-electron pairs by the generation-recombination process on the surface of the p-type semiconductor, or from the n-type region where electrons connected by the channel 18 are majority carriers. Can be In the present invention, since holes generated in the generation-recombination process play an important role, it is desirable to increase the time change rate of the gate potential so that this process can sufficiently occur. The holes generated in the p-well region 19 move in the p-well region 19 and exit to the cathode electrode 10. On the other hand, holes generated in the p base region 7 diffuse into the p base region 7 and shift in a direction to increase the potential of the region. At this point, the n-emitter region 8 is electrically connected to the n-source region 9 via the two channels 18 and the n-region 1 (connected by electrons of the same kind of carriers). Therefore, the n source region 9
Electrons flow into the n-emitter region 8 and recombine with holes diffused in the p-base region 7. The electrons that cannot be recombined penetrate through the p base region 7 and are injected into the n region 1, and further flow to the right side of the anode electrode 13. The process up to this point is the n emitter region 8 / p base region 7 /
This is a process in which the npn transistor including the n region 1 is turned on.

Almost simultaneously, the electrons flowing from the n source region 9 to the n region 1 through the channel 18 move directly to the anode electrode 13 side, and the holes are formed at the p emitter region 12 / n region 1 boundary as in the operation of the IGBT. Urges injection. The holes injected into the n region 1 flow into the p base region 7 or the p well region 19, but pass through the p base region 7 which has been subjected to the conductivity modulation. Since the electric resistance is smaller than that flowing through the resistance R _well portion, a large amount flows into the p base region 7 side. As a result, the thyristor composed of the pnp transistor composed of the p emitter region 12 / n region 1 / p base region 7 and the above-mentioned npn transistor shifts to the conductive state (FIG. 10B). The anode current I _A, it means that flow through most n source region 9 and the n emitter region 8 and the two points of the channel 18 connecting the can be controlled by voltage applied to the gate electrode 5.

In the case of this embodiment, since the channel through which the anode current flows has already been formed at the time when the thyristor shifts to the conducting state, the timing of the two gate signals is adjusted as in the embodiment, In addition, there is no need to particularly consider the use and manufacturing of a depletion type n-channel MOSFET. Initially, in the example, there was a concern that a large amount of electrons flowed in from the n-type semiconductor portion, the generation ratio of hole-electron pairs was reduced, and as a result, the thyristor trigger current was insufficient. Therefore,
A small area of the device (for example, p-channel type MO in BFT)
A MOS capacitor for triggering is provided as a supplement to the portion where the SFET is formed. However, in the device size we prototyped, the volume of the p-base could be reduced, so that there was no particular need. When the specification condition of the element is changed, it is considered that an auxiliary trigger MOS capacitance may be required in some cases. However, basically, only one type of gate electrode is required and layout design is facilitated.

FIG. 11 shows a horizontal MOS transistor of the embodiment shown in FIG.
4 shows a current-voltage characteristic of a type GTO thyristor. The size is W = 155 μm, L = 645 μm, and the cathode electrode is arranged on the outer periphery. Compared to FIG. 7, it can be said that the on-state voltage is high overall and the gate voltage dependency is remarkable. The most significant difference is that the parasitic thyristor virtually no longer latches up.
The parasitic thyristor is composed of an n-source region 9 / p-well region 19 / n-region 1 / p-emitter region 12. To operate, a hole current needs to flow in the p-well region 19. is there. However, it does not flow in the steady state. Even if it flows, the configuration of the same portion may be exactly the same as that of the IGBT, and the conditions under which this parasitic thyristor does not function are already well known.

In this manner, the latch-up is free,
MO that is smaller than IGBT and EST and has excellent saturation characteristics
An S-type GTO thyristor could be provided. IGB
In the case of T, a base current is supplied via a high breakdown voltage type MOSFET, and as a result, a drain current which is a main current is controlled. Although the main current need not all pass through the MOSFET as in the MOS type GTO thyristor of the present invention, the reason why the channel width must be widened is that the current density of the high breakdown voltage type MOSFET is low. is there. On the other hand, in the MOS type GTO thyristor of the present invention, although the anode current of the main current passes through the MOSFET with a low breakdown voltage, the total channel width may be shorter than that of the IGBT. This seems seemingly contradictory,
The conclusion is that the current density of the low breakdown voltage MOSFET is high. The saturation drain current I _Dsat due to the channel portion is calculated by a simple calculation method.

[0074] drift velocity of carriers in the channel v _s
If is not saturated,

[0075]

I _Dsat = W _ch μ _n C _O (V _G −V _th ) ² / 2L _ch [A] ── (a) Here, W _ch and L _ch are the channel width and channel length (unit: cm) of the MOSFET. μ _n is the electron mobility in the channel in silicon, typically one half that in silicon, and μ _n = 750 [cm ² · V ⁻¹
. S ^-1 ]. C _O is the MOS capacitance capacity per unit area. If the gate oxide film thickness d _Ox is 30 nm and the relative permittivity ε _Ox of the oxide film is _3.5 to 4.0,

[0076]

[Number 2] _{C O = ε Ox · ε 0} / d Ox = 1.03~1.1
8 × 10 ⁻⁷ [F · cm ⁻² ] (ε ₀ : dielectric constant in vacuum). V _G and V _th are respectively the gate voltage applied to the gate threshold voltage. Further, if the drift velocity v _s of the carrier has reached the saturation, v _s =
Using 9 × 10 ⁶ [cm · s ^-1 ],

[0077]

Equation 3] represented by _{I Dsat = W ch v s C} O (V g -V th) (A) ─── (b). In the prototype device, W _ch = 1340 μm,
(Cathode 55 + 490) _Lch = 1.2 μm and V
_By substituting _g = 5V and _Vth = 1V into the respective equations, the calculation yields about I _Dsat = 737 _{mA in} the case of the equation (a).
In the case of the equation (b), it is about 530 mA.

[0078] In practical devices, mu _n and v _s using the above calculations, but is not necessarily the optimum value, even down 20%, 400 meters
It turns out that about A can be secured. From such an estimation, it can be seen that in the case of the present invention, the capability of the low breakdown voltage MOSFET is sufficiently exhibited. It is considered that the reason why the performance can be sufficiently exhibited as compared with the high withstand voltage type is that the drain resistance is small and the externally applied voltage is applied to both ends of the channel layer, so that the saturation current is reached at a low on-voltage. In the present invention, since the conductivity modulation is sufficiently applied so that the thyristor operation can be continued without supplying a current from the outside, it can be realized. Incidentally, according to the result of the simulation, the density of holes injected into the n region is 10 ¹⁷ to 10 ¹⁸ cm ^-3 in the case of a general IGBT, but is 10 ²⁰ cm ^-3 in the case of the present invention. I know it will reach.

As described above, the device area can be reduced by the conductivity modulation superior to the IGBT.
On the other hand, a problem has emerged that the turn-off speed is inferior to IBGT. As described above, even in the case of the EST, a common problem has occurred. If this is not solved, the range of application is extremely limited. Switching speed control by a lifetime killer, which is often used in the past, is difficult to apply in the field of power ICs that simultaneously manufacture logic circuits, and causes an increase in steady-state loss in semiconductor switching elements such as industrial general-purpose inverters. It is feared that there is a fear that the merit of thyristor cannot be obtained.

Therefore, in the MOS type GTO thyristor,
It is required to control the switching speed (particularly at the time of turn-off) by another method other than the lifetime killer. As a method thereof, in the embodiment, as shown in FIG. 9, the p-well region 19 is arranged closer to the anode side than the p-base region 7. In the horizontal type shown in FIG. 9, it is important that the p-well region 19 is provided so as to surround the p-base region 7, and that the p-well region 19 is further diffused deeply to reduce the remaining width of the n-region 1.

When the voltage V _AK is applied between the anode and the cathode, the depletion layer expands naturally at the junction between the p-well region 19 and the n-region 1 to obtain a desired element breakdown voltage. P base region 7 not in direct contact with the electrode
Then, a depletion layer is also formed in n region 1. However, p
As a structure surrounding the p base region 7 with the well region 19, the p base region 7 therebelow is electrically separated by a depletion layer extending between the p well region 19 and the n region 1.

To explain this effect in the case of the process (turn-off) from the conduction state to the interruption state, FIG.
A description will be given using (a), (b) and (c). First,
An OFF signal is input to the gate electrode 5 (that is, V _g
= 0) and the channel 18 for flowing the anode current to the external electrode
Disappears. Therefore, a steady current cannot flow any more, and n emitter region 8 and p emitter region 12
Injection of minority carriers from the substrate is stopped. However, since the p base region 7 and the n region 1 have been sufficiently subjected to conductivity modulation, excess minority carriers remain [FIG. 12 (a)].

As the device breakdown voltage increases, electrons 81 as minority carriers in p base region 7 flow into n region 1 having a higher potential, and recombine with holes 82 as minority carriers in n region 1. Go and cancel. Since the volume of the p base region 7 is small, this process ends relatively quickly. As V _AK gradually increases, the depletion layer 83 gradually expands. It mainly spreads at the junction between the p-well region 19 and the n-region 1, and the surrounding holes 82 drop toward it, and pass through the p-well region 19 to form the cathode electrode 1.
Flows to zero. Since the holes 82 flow to a lower potential, the holes 82 are also injected into the p base region 7 which is a floating potential. As a result, although a depletion layer is formed to some extent, since there is no path to the outside, the potential including the n-emitter region 8 rises, and the potential and the expansion of the depletion layer are balanced with the injection amount of the holes 82. Figure (b).

In an IGBT or the like having a low conductivity modulation level, the depletion layer spreads relatively smoothly in this process, holes are swept out one after another, and the current is cut off. Since the hole concentration is extremely high, the phenomenon does not progress and the turn-off time is required. However, in the case of the embodiment having the shape and arrangement of the p-well region 19 shown in FIG.
The area 1 is divided [(c) in the figure].

In this state, p-base region 7, which is a floating potential, is shielded by depletion layer 83, so that it is not directly affected by the anode potential. Therefore, the power for raising the potential of the same portion is weakened. By the injection of holes, the function of expanding the depletion layer becomes remarkable. Adjacent p-well region 1
When integrated with the depletion layer extending from 9, all holes flow out to the cathode electrode 10. FIG.
In the state shown in FIG. 3C, the p-well region 1 is substantially removed.
This is the same as the reverse recovery process of the diode composed of the 9 / n region 1. The general time required for the reverse recovery process of the diode is several tens of times without particularly introducing a lifetime killer.
0 nsec. Even if the concentration of the remaining minority carriers is high, the structure is simple, so that the three-terminal element IBG
Turn-off time is shorter than T or bipolar transistor. Therefore, the remaining holes 82 are rejected at high speed. This has the same effect whether the SOI substrate uses the dielectric isolation technology or the embedded epitaxial substrate uses the junction isolation technology.

FIG. 13 shows the MOS type GT of the embodiment shown in FIG.
Anode current (I) when the O-thyristor is turned off
_A ) The waveform is shown. In order to confirm the effect, the case where the depth of the p-well region 19 was changed to 3 μm, 5 μm, and 7 μm was compared and shown by a dashed line, a broken line, and a solid line, respectively. Here, the depth of p base region 7 is 2 μm. A resistance load through which the same current flows was connected to each element, and the time when the gate signal was changed from ON (5 V) to OFF (0 V) was started. Both to about 0.3μsec three elements, the change in I _A is the delay time without. Inside the element, it is considered that the process up to FIG. After that,
I _A starts to decrease. From this point on, there is a difference in behavior between the three elements, and the 7 μm element decreases relatively smoothly, but the 3 μm and 5 μm elements change slowly.
This process is considered to be at the stage of FIG. 12B, and it can be estimated that a change is observed in the waveform due to a difference in the way the depletion layer spreads. The boundary between the processes in FIGS. 12B and 12C cannot be clearly determined from the current waveform, but is considered to be a point that decreases with a constant time constant.
It can be estimated between 2 and 0.5 μsec. The device of 7 [mu] m, so likely to be blocked by the depletion layer, by the 0.5 .mu.sec, has reached 10% or less of I _A of the initial value (which defines the time and the switching time.). In other devices, it took time for the depletion layer to expand, and as a result, the switching time was 1.0 μsec or more.

When the depth of the p-well region 19 is increased, the path through which a current flows becomes narrower, so that the on-voltage tends to increase. There was no adverse effect and the switching time could be reduced. With the configuration shown in FIG. 9, [Problem 1] and [Problem 2] have been solved, and a MOS GTO thyristor with a short switching time has been realized.

[Embodiment] FIG. 14 is a sectional view of a MOS type GTO thyristor according to a fifth embodiment (referred to as an embodiment) of the present invention. The parts that work the same as in the embodiment of FIG.
The same numbers are used. The difference from the embodiment of FIG. 9 is that the p well region 19 is not only deeper than the p base
The point is that it extends below the base region 7.

In the structure of the embodiment shown in FIG. 9, the depletion layer spreads along the characteristicly shaped p well region 19 and shields the p base region 7 to replace a simple diode structure. High-speed switching is possible, and turn-off characteristics can be improved. FIGS. 15A to 15E are cross-sectional views showing a procedure for manufacturing the p-well region 19 having the unique shape shown in FIG.

After the screen oxide film 70 is formed on the n-region 1, the thermal nitride film 71 is laminated, and then the photoresist 72 is patterned and etched to remove unnecessary portions of the thermal nitride film 71, and the same resist pattern is formed. Boron ions 74, which are p-type impurities, are ion-implanted into the mask.
[FIG. 15A]. Then, after removing the photoresist 72 and the screen oxide film 70 in the portion damaged by the ion implantation, a heat treatment for diffusion and oxidation of the implanted boron is performed. In the part without the thermal nitride film 71, p
As well region 19 is formed, thick field oxide film 3 grows on the surface. Since the oxidizing agent hardly reaches the silicon surface in the portion where the thermal nitride film 71 remains, almost no oxide film grows (this is a normal LOCOS process). The remaining thermal nitride film 71 is removed, and phosphorus ions 75, which are n-type impurities, are introduced by an ion implantation apparatus through the exposed screen oxide film 70 [FIG. The implantation amount needs to exceed the concentration of boron diffused in the lateral direction and return to the n-type.

Thereafter, the screen oxide film 70 is removed again, and heat treatment for impurity diffusion and oxidation is performed. The oxidation at this time may be such that a thin screen oxide film is formed again. Since the portion where phosphorus is diffused becomes n-type, a prototype of p-well region 19 having a unique shape shown in FIG. 9 is formed. Boron ions 74 are implanted again [FIG.
The injection amount needs to be higher than the above boron concentration and return to the n-type.

When the screen oxide film 70 is removed again and heat treatment for impurity diffusion and oxidation is performed, the p base region 7 is formed. Next, arsenic ions 76
And the same steps are repeated [FIG. By performing the heat treatment, an n-emitter region 8 is formed. At this time, the n source region 9 may be formed in the p well region 19 at the same time.

Then, after removing the oxide film in the active region, a gate oxide film 4 is formed, polycrystalline silicon is deposited, and then the gate electrode 5 is formed by etching into an electrode shape. Thereafter, the cathode electrode 10 is formed by sputtering and patterning the Al-Si alloy. [FIG. (E)]. FIG.
Is a manufacturing method that can reduce the variation in element characteristics as much as possible because the thyristor portion can be formed by self-alignment at low cost. When manufactured by this procedure, irregularities are formed on the silicon surface below the gate electrode 5 as shown in the cross-sectional view. This is a boundary portion between a portion where the thick field oxide film 3 is grown and a portion where the thick field oxide film 3 is not formed, which is not always preferable from the viewpoint of the reliability of the gate oxide film 4. The silicon surface at the boundary of the film has irregularities, and a highly reliable gate oxide film can be formed as seen in an extreme case such as a trench MOS.

[Embodiment] FIG. 16 shows another embodiment of the MOS type GTO thyristor according to the present invention. The difference from the embodiment is that the p well region 19 and the p base region 7 are connected by a low concentration and shallow p ⁻ region 20.
It is desirable that the surface of p ⁻ region 20 be covered with gate electrode 5 via gate oxide film 4. Even if there is a portion that protrudes from the gate electrode, the p well region 19 and the p base region 7 must not be connected to each other over the protruding p ⁻ region 20.

This method uses a method between the p base region 7 and the n region 1.
In the case of a structure in which the depletion layer spreads in the
This is effective when the depth of the region is 3 μm or the like. Real
In the structure of the embodiment, the avalanche near p base region 7 is used.
When a current is generated, the rejected current (carrier)
Since there is no flow destination, the element may be destroyed
(Weak avalanche capability.) [Similar phenomenon is withstand pressure
Adopts a floating guard ring structure
You can also see when. Improperly designed and several
The rotating diffusion layer is a depletion layer that extends inside silicon.
Pn on the silicon surface as a result
The joint breaks. In order to solve this problem, in the embodiment, a floating potential is used.
P base region 7 ^-The structure connected in the area 20
You. It should be noted that p^-Area 2
0 is caused by the electric field effect of the gate electrode 5 present above.
Since it is possible to easily deplete, in this case,
The source region 7 becomes a floating potential and operates in the same manner as in the embodiment.
It can be driven.

As described above, the devices according to these inventions are devices combining the functions of EST and BFT which are conventionally known. In order to apply to the exemplified application, etc., it is necessary to have sufficient self-extinguishing ability, and the following points must be considered and designed. (1) The size and arrangement of the MOS capacitance are determined so that the thyristor shifts to the conductive state with a small trigger current.

(2) Before the thyristor shifts to the conducting state, the impurity concentration, the thickness of the gate oxide film, and the like are determined so that the lateral MOSFET is in the ON state. (3) In order to secure a saturation region, the channel width of a high performance (high current density) lateral MOSFET is made as large as possible. (4) The expansion of the depletion layer inside the element is used so as to avoid malfunction and increase the switching capability. (The effect of the junction type FET is used.) It is not easy to optimize while keeping these balances, and the inventors repeated simulation techniques and trial production many times to determine conditions suitable for application. Therefore, if the area of the element or the withstand voltage greatly changes, the above numerical values naturally change, but may be changed in accordance with the above design points.

[0098]

As described above, the MOS type G of the present invention is used.
The TO thyristor makes use of the advantages of each of the conventional MOS thyristors and has a device structure that compensates for the disadvantages, and has the following effects. (1) Since the configuration is such that ignition can be performed by charging current to the MOS capacitance, the MOS transistor is small and has a large current capacity.
A type GTO thyristor is obtained.

(2) A junction field effect transistor (J-FET) is provided by utilizing a depletion layer extending from the p-well region, and the switching characteristics particularly at the time of turn-off can be improved. (3) By devising the arrangement of the electrodes, current concentration can be alleviated, and latch-up or destruction of the element due to temperature rise can be prevented.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view of a MOS GTO thyristor according to an embodiment.

FIGS. 2A and 2B are explanatory diagrams showing the operation principle of the MOS GTO thyristor shown in FIG. 1;

3 (a) to 3 (c) are dimensional comparison diagrams of main parts of an embodiment and a conventional element, respectively.

4A is an electrode arrangement diagram of an embodiment, and FIG. 4B is a cross-sectional view taken along line BB ′.

FIG. 5 is a current-voltage characteristic diagram of an example.

FIG. 6A is an electrode layout view of a MOS GTO thyristor of an embodiment, and FIG. 6B is a cross-sectional view taken along line CC ′.

FIG. 7 is a current-voltage characteristic diagram of an example.

FIG. 8 is a sectional view of a MOS GTO thyristor according to an embodiment.

FIG. 9 is a cross-sectional view of a MOS-type GTO thyristor of an embodiment.

FIGS. 10 (a) and (b) show a MOS type G according to an embodiment;
Sectional view showing operation principle of TO thyristor

FIG. 11 is a current-voltage characteristic diagram of an example.

FIGS. 12A to 12C are explanatory diagrams of an OFF operation of the embodiment.

FIG. 13 is a current waveform diagram at the time of off in the embodiment.

FIG. 14 is a sectional view of a MOS GTO thyristor according to an embodiment;

FIGS. 15 (a) to (e) show the MOS type G of the embodiment.
Sectional drawing of a part of the manufacturing process of the TO thyristor in order of process

FIG. 16 is a sectional view of a MOS GTO thyristor according to an embodiment.

FIG. 17 is a sectional view of a conventional MOS thyristor (BFT).

FIG. 18 (a) is an electrode arrangement diagram of an improved BFT, and (b)
Is a sectional view taken along line AA '

FIG. 19 is a sectional view of a conventional EST.

FIG. 20 is a diagram illustrating the operation of a conventional EST

21 (a) and (b) show a conventional E following FIG.
ST operation explanation diagram

FIG. 22 is a current-voltage characteristic diagram of a conventional EST.

[Explanation of symbols]

1, 21, 41 n region 2, 22, 42 oxide film 3 field oxide film 4, 24, 44 gate oxide film 5, 25, 45 gate electrode or first gate electrode 6, 26, 46 second gate electrode 7, 27 p base region 8, 28, 48 n emitter region 9, 29, 49 n source region 10, 30, 50 cathode electrode 11, 31, 51 n ⁺ buffer region 12, 32, 52 p emitter region 13, 33, 53 anode region 14, 34 support substrate 15, 35 oxide film 16 p drain region 17, 37 inversion layer 18 channel 19 p well region 20 p ⁻ region 40 p substrate 57 first channel 58 second channel 59 p ⁺ contact region 60 p ⁺ isolation Area 61 Power supply 62 Load 63 Gate power supply 70 Screen oxide film 71 Nitride film 72 Photoresist 7 4 Boron ion 75 Phosphorus ion 76 Arsenic ion 81 Electron 82 Hole 83 Depletion layer

Claims (11)

(57) [Claims] A second conductivity type base region formed separately from each other on a part of a surface layer on one main surface of the first conductivity type semiconductor layer;
A second conductivity type emitter region, an anode electrode provided in contact with the surface of the second conductivity type emitter region, and a first conductivity type source region formed on a part of the surface layer of the second conductivity type base region, A first conductivity type emitter region formed on a surface layer of a portion of the second conductivity type base region closer to the second conductivity type emitter region than the first conductivity type source region, and provided in contact with a surface of the first conductivity type source region. On the gate oxide film on the exposed surface of the second conductive type base region sandwiched between the cathode electrode and the first conductive type emitter region and the first conductive type semiconductor layer,
A first gate electrode having an end on the second conductivity type base region and extending to a side close to the second conductivity type emitter region, and being sandwiched between a first conductivity type source region and a first conductivity type emitter region; And a second gate electrode provided on a gate oxide film on a surface exposed portion of the second conductivity type base region. 2. The MOS type GTO thyristor according to claim 1, wherein a second conductivity type base region is formed so as to surround the second conductivity type emitter region. 3. A two-conductivity-type base region formed on a part of a surface layer on one main surface of a first-conductivity-type semiconductor layer and a part of a surface layer on a second-conductivity-type base region. The formed first conductivity type source region, the first conductivity type emitter region, the cathode electrode provided in contact with the surface of the first conductivity type source region, and another main surface side surface of the first conductivity type semiconductor layer A second conductivity type emitter region formed in part of the layer, an anode electrode provided in contact with the surface of the second conductivity type emitter region, and a first conductivity type emitter region and the first conductivity type semiconductor layer; A first oxide layer having an end on the second conductivity type base region and extending to a side close to the first conductivity type semiconductor layer on the gate oxide film on the exposed surface of the second conductivity type base region; Between the gate electrode, the first conductivity type source region and the first conductivity type emitter region MOS type GTO thyristor and having a second gate electrode provided on the second-conductivity-type base region on a gate oxide film on the exposed surface of. 4. A MOSFET having a structure located in a second gate electrode and a lower layer portion thereof is of a depletion type which conducts in a thermal equilibrium state and is turned off by a gate signal. The MOS-type GTO thyristor according to any one of the above. 5. A second conductive type base region and a second conductive type emitter region formed on a part of a surface layer on one main surface of a first conductive type semiconductor layer, and contact with a surface of the second conductive type emitter region. An anode electrode provided, a second conductivity type well region formed in a part of the surface layer of the first conductivity type semiconductor layer between the second conductivity type base region and the second conductivity type emitter region, The first conductivity type source region formed in a part of the surface layer of the second conductivity type well region, and provided in common contact on the surfaces of the second conductivity type well region and the first conductivity type source region. A cathode electrode, a first conductivity type emitter region formed on a part of the surface layer of the second conductivity type base region, and a second conductivity type sandwiched between the first conductivity type emitter region and the first conductivity type source region. Base region, first conductive type semiconductor layer surface exposed portion and second conductive type well region MOS type G to the gate electrode provided on the gate oxide film on the surface of the characterized in that it has a
TO thyristor. 6. The MOS type GTO thyristor according to claim 5, wherein a second conductivity type well region is formed so as to surround the second conductivity type base region. 7. The MOS-type GTO thyristor according to claim 5, wherein the diffusion depth of the second conductivity type well region is deeper than that of the second conductivity type base region. 8. The MOS type GTO thyristor according to claim 7, wherein a part of the second conductivity type well region is below the second conductivity type base region. 9. The second conductivity type base region and the second conductivity type well region are formed by a second conductivity type connection region having a lower impurity concentration and a lower diffusion depth than the second conductivity type base region below the gate electrode. 10. The MOS GTO thyristor according to claim 5, wherein the MOS GTO thyristor is connected. 10. The method of driving a MOS GTO thyristor according to claim 1, wherein the same control signal is applied to the first gate electrode and the second gate electrode. 11. A signal is applied to the first gate electrode after a signal is applied to the second gate electrode to delay generation of an inversion layer under the first gate electrode from generation of an inversion layer under the second gate electrode.
Further, the reverse signal is applied to the first gate electrode, and then the reverse signal is applied to the second gate electrode to delay the disappearance of the inversion layer under the second gate electrode more than the disappearance of the inversion layer under the first gate electrode. The M according to any one of claims 1 to 4, wherein
A method for driving an OS type GTO thyristor.