JPH0574951B2 - - Google Patents
Info
- Publication number
- JPH0574951B2 JPH0574951B2 JP59214814A JP21481484A JPH0574951B2 JP H0574951 B2 JPH0574951 B2 JP H0574951B2 JP 59214814 A JP59214814 A JP 59214814A JP 21481484 A JP21481484 A JP 21481484A JP H0574951 B2 JPH0574951 B2 JP H0574951B2
- Authority
- JP
- Japan
- Prior art keywords
- transparent conductive
- conductive film
- amorphous silicon
- film
- silicon layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 229910021417 amorphous silicon Inorganic materials 0.000 claims description 22
- 239000000758 substrate Substances 0.000 claims description 15
- 239000004065 semiconductor Substances 0.000 claims description 8
- 239000011810 insulating material Substances 0.000 claims 1
- 238000009792 diffusion process Methods 0.000 description 11
- 238000000034 method Methods 0.000 description 6
- 239000012535 impurity Substances 0.000 description 4
- 238000010030 laminating Methods 0.000 description 3
- 238000010248 power generation Methods 0.000 description 3
- 229910021419 crystalline silicon Inorganic materials 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000011521 glass Substances 0.000 description 2
- 230000035515 penetration Effects 0.000 description 2
- 238000002230 thermal chemical vapour deposition Methods 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 229910006404 SnO 2 Inorganic materials 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- WABPQHHGFIMREM-UHFFFAOYSA-N lead(0) Chemical group [Pb] WABPQHHGFIMREM-UHFFFAOYSA-N 0.000 description 1
- 230000031700 light absorption Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/02—Details
- H01L31/0224—Electrodes
- H01L31/022466—Electrodes made of transparent conductive layers, e.g. TCO, ITO layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/02—Details
- H01L31/0236—Special surface textures
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
- Y02E10/00—Energy generation through renewable energy sources
- Y02E10/50—Photovoltaic [PV] energy
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は透明導電膜面に光の反射防止用の凹凸
を形成した光起電力装置に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Industrial Field of Application] The present invention relates to a photovoltaic device in which a transparent conductive film has irregularities for preventing reflection of light.
光起電力装置は通常ガラス等の透光性絶縁基板
上に透明導電膜、非晶質半導体層、裏面電極膜を
この順序で積層形成して構成してあり、光を透光
性絶縁基板、透明導電膜を通して非晶質半導体層
に入射させ、生起された電力を前記透明導電膜及
び裏面電極膜に接続したリード線を通じて外部に
取り出すようになつている。
A photovoltaic device is usually constructed by laminating a transparent conductive film, an amorphous semiconductor layer, and a back electrode film in this order on a transparent insulating substrate such as glass. The electric power is made incident on the amorphous semiconductor layer through the transparent conductive film, and the generated electric power is extracted to the outside through a lead wire connected to the transparent conductive film and the back electrode film.
ところで上記した如き光起電力装置においては
光が透光性絶縁基板、透明導電膜通過の際、その
表面で夫々光が反射され、発電効率が低下すると
いう問題があつた。 However, in the photovoltaic device as described above, when light passes through the transparent insulating substrate and the transparent conductive film, the light is reflected by the respective surfaces, resulting in a reduction in power generation efficiency.
このため従来にあつては透光性絶縁基板の受光
面に反射防止膜を形成する方法、或いは透光性絶
縁基板面及び透明導電膜面の双方、又は透明導電
膜面のみを凹凸化して表面反射率を低下させる方
法等が採用されている。 For this reason, the conventional method is to form an antireflection film on the light-receiving surface of a light-transmitting insulating substrate, or by making both the light-transmitting insulating substrate surface and the transparent conductive film surface, or only the transparent conductive film surface, uneven. Methods such as lowering the reflectance have been adopted.
ところで上述した如く、例えば透明導電膜面に
凹凸を形成する構成とした場合、凹凸は0.5〜1μ
ｍ程度であるが、凸部が大き過ぎて透明導電膜上
に積層形成した非晶質シリコン層、即ちpin構造
の場合は透明導電膜とｉ層、ｎ層及び裏面電極膜
と接触して短絡を生じ、逆に効率の低下、歩留り
の低下を招く外、透明導電膜の成分であるSn、
Ｏが非晶質シリコン層へ拡散し、特性の低下を招
くという問題があつた。
By the way, as mentioned above, for example, when the structure is such that unevenness is formed on the surface of the transparent conductive film, the unevenness is 0.5 to 1 μm.
However, in the case of an amorphous silicon layer laminated on a transparent conductive film, that is, a pin structure, the convex portion is too large and comes into contact with the transparent conductive film, the I layer, the N layer, and the back electrode film, causing a short circuit. In addition to causing a decrease in efficiency and yield, Sn, which is a component of the transparent conductive film,
There was a problem in that O diffused into the amorphous silicon layer, leading to deterioration of characteristics.
第３図は、従来装置における透明導電膜から非
晶質シリンコン層への拡散の結果を示すグラフで
あり、横軸に深さを、また縦軸に不純物濃度をと
つて示してある。グラフ中ａ線はSnの、またｂ
線はＯの各拡散濃度をとつて示してある。このグ
ラフから明らかなようにSn、Ｏともにその拡散
の程度が大きい。 FIG. 3 is a graph showing the results of diffusion from a transparent conductive film to an amorphous silicon layer in a conventional device, with the horizontal axis representing depth and the vertical axis representing impurity concentration. The a line in the graph is Sn, and the b line is
The lines are shown for each diffusion concentration of O. As is clear from this graph, the degree of diffusion of both Sn and O is large.
本発明はかかる事情に鑑みなされたものであつ
て、その目的とするところは基板上に形成された
表面が凹凸化された透明導電膜と、該膜を下地と
して積層形成される非晶質シリコン半導体層との
間に、ノン・ドープで且つ絶縁性の、SiC、TiC、
WC、またはBPを素材とする少なくとも１又は
複数の膜を全体として10〜100Å積層することで
上記凹凸の程度を緩和し、これに上記非晶質シリ
コン半導体層を積層形成することにより、短絡防
止、並びに透明導電膜から非晶質シリコン半導体
層へのSn、Ｏ等の不純物の拡散を防止し光起電
力特性を格段に向上させ得るようにした光起電力
装置を提供するにある。
The present invention has been made in view of the above circumstances, and its objectives are to provide a transparent conductive film formed on a substrate with an uneven surface, and an amorphous silicon layer formed using the film as a base. Non-doped and insulating SiC, TiC,
By stacking at least one or more films made of WC or BP with a total thickness of 10 to 100 Å, the degree of unevenness can be alleviated, and by stacking the amorphous silicon semiconductor layer on top of this, short circuits can be prevented. The present invention also provides a photovoltaic device which can prevent impurities such as Sn and O from diffusing from a transparent conductive film to an amorphous silicon semiconductor layer, thereby significantly improving photovoltaic characteristics.
本発明に係る光起電力装置は透光性基板と、該
基板上に形成された、表面に凹凸を有する光の反
射防止用の透明導電膜と、上記表面上に積層され
た、その凹凸の程度を緩和するように膜厚を10〜
100Åとする、ノン・ドープで且つ絶縁性の、
SiC、TiC、WC、又はBPを素材とする１又は複
数の膜と、該膜上に積層された非晶質シリコン半
導体層、とからなることを特徴とする。 A photovoltaic device according to the present invention includes a light-transmitting substrate, a transparent conductive film for preventing reflection of light having an uneven surface formed on the substrate, and a transparent conductive film formed on the substrate with an uneven surface layered on the surface. The film thickness is set to 10~10 to reduce the degree of
Non-doped and insulating, with a thickness of 100 Å.
It is characterized by consisting of one or more films made of SiC, TiC, WC, or BP, and an amorphous silicon semiconductor layer stacked on the films.
以下本発明をその実施例を示す図面に基づき具
体的に説明する。第１図は本発明に係る光起電力
装置（以下本発明装置という）の断面構造図であ
り、図中１はガラス等で形成した透光性絶縁基
板、２はSnO2、或いはIn2O3等を素材とする透明
導電膜、３はSiC、TiC、WC又はBPのいずれか
を素材とする１、又は複数の膜、４は非晶質半導
体層たる非晶質シリコン層、５はAl等を素材と
する裏面電極膜を示している。
DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be specifically described below based on drawings showing embodiments thereof. FIG. 1 is a cross-sectional structural diagram of a photovoltaic device according to the present invention (hereinafter referred to as the device of the present invention), in which 1 is a transparent insulating substrate made of glass or the like, and 2 is SnO 2 or In 2 O. 3 is one or more films made of SiC, TiC, WC or BP, 4 is an amorphous silicon layer which is an amorphous semiconductor layer, 5 is Al The figure shows a back electrode film made of materials such as .
透明導電膜２は透光性絶縁基板１と接する側は
平坦面であるが、反対側、即ち非晶質シリコン層
を積層すべき側は凹凸化されており、この凹凸化
された面にSiC、TiC、WC、又はBPを素材とす
る10〜100Åの厚さの膜３が１又は複数層積層形
成されている。 The transparent conductive film 2 has a flat surface on the side in contact with the transparent insulating substrate 1, but the opposite side, that is, the side on which the amorphous silicon layer is to be laminated, is roughened, and SiC is deposited on this roughened surface. , TiC, WC, or BP and has a thickness of 10 to 100 Å, one or more films 3 are stacked.
膜３の形成手段は熱CVD法、光CVD法、グロ
ー放電法等、特に限定するものではないが、例え
ば熱CVD法によりBPを素材とする膜３を透明導
電膜２上に形成する場合は透明導電膜２を形成し
た透光性絶縁基板１を1000℃前後に加熱しつつ
B2H6＋PH3の成長ガスを通流せしめることによ
り成長せしめる。 The method for forming the film 3 is not particularly limited, such as a thermal CVD method, a photo CVD method, a glow discharge method, etc., but for example, when the film 3 made of BP is formed on the transparent conductive film 2 by a thermal CVD method, While heating the transparent insulating substrate 1 on which the transparent conductive film 2 is formed to around 1000°C.
Growth is performed by flowing a growth gas of B 2 H 6 +PH 3 .
SiC、TiC、WC、BPはいずれも本来的に絶縁
機能を備える外、耐熱性、硬さに優れ、例えば非
晶質シリコン層をグロー放電により形成するよう
な場合、透明導電膜の損傷を防止し得、また光学
的バンドギヤツプが大きく光の吸収が小さいとい
う特性を有している。膜３を積層形成した状態で
は透明導電膜２の凹凸面の凹凸状態は若干緩和さ
れた状態となつており、この面上に非晶質シリコ
ン層４を積層形成せしめることにより、凸部が非
晶質シリコン層４を突き抜けることが防止され、
また仮令突き抜けて形成された場合もその絶縁性
により短絡が防止される。なお非晶質シリコン層
４はpin型、nip型のいずれの構造であつてもよ
い。 SiC, TiC, WC, and BP all inherently have an insulating function and are excellent in heat resistance and hardness, and are used to prevent damage to transparent conductive films, for example, when forming an amorphous silicon layer by glow discharge. It also has the characteristics of a large optical bandgap and low light absorption. In the state in which the film 3 is laminated, the unevenness of the uneven surface of the transparent conductive film 2 is slightly relaxed, and by laminating the amorphous silicon layer 4 on this surface, the convex portions are made non-uniform. Penetration through the crystalline silicon layer 4 is prevented,
Furthermore, even if the wire is formed to penetrate through the wire, short circuits are prevented due to its insulating properties. Note that the amorphous silicon layer 4 may have either a pin type or nip type structure.
膜３上には従来と同様に非晶質シリコン層を積
層形成するが、この非晶質シリコン層４をグロー
放電法によりBP製膜３上に積層形成する場合に
ついてその形成条件の一例を示すと次のとおりで
ある。透光性絶縁基板１の温度を200〜350℃に設
定し、SiH4＋CH4又はC2H4、又はC2H6等を成分
とする成長ガスをガス圧0.1〜1Torrで通流しつ
つRFパワー10〜100Wでグロー放電を行なわせ、
成長を行う。 An amorphous silicon layer is laminated on the film 3 in the same manner as in the past, and an example of the formation conditions when this amorphous silicon layer 4 is laminated on the BP film 3 by the glow discharge method will be shown. and as follows. The temperature of the transparent insulating substrate 1 was set at 200 to 350°C, and RF was applied while flowing a growth gas containing SiH 4 + CH 4 or C 2 H 4 or C 2 H 6 at a gas pressure of 0.1 to 1 Torr. Glow discharge is performed with a power of 10 to 100W,
Do growth.
このようにして得た光起電力装置は短絡が確実
に防止され、また透明導電膜成分であるSn、Ｏ
の非晶質シリコン層への拡散も大幅に低減せしめ
得ていることが確認された。 The thus obtained photovoltaic device is reliably prevented from short-circuiting, and also has transparent conductive film components such as Sn and O.
It was confirmed that the diffusion of into the amorphous silicon layer could also be significantly reduced.
第２図はIMA（イオンマイクロアナライザ）を
用いて非晶質シリコン層へのSn、Ｏの拡散プロ
フアイルを調べた結果を示すグラフであり、横軸
には透明導電膜の凹凸面から非晶質シリコン層４
側への深さを、また縦軸には不純物濃度（対数：
任意目盛）をとつて示してある。グラフ中ａ線は
Snの、またｂ線はＯの拡散濃度を示している。
このグラフから明らかな如く本発明にあつては
Sn、Ｏのいずれの拡散濃度も格段に低減されて
いることが解る。 Figure 2 is a graph showing the results of investigating the diffusion profile of Sn and O into an amorphous silicon layer using an IMA (ion microanalyzer). quality silicon layer 4
The depth to the side is shown, and the vertical axis shows the impurity concentration (logarithm:
(arbitrary scale). The a line in the graph is
The Sn and b lines indicate the O diffusion concentration.
As is clear from this graph, in the present invention,
It can be seen that the diffusion concentrations of both Sn and O are significantly reduced.
なお、表面反射率も０〜10％程度であつて、従
来装置が30〜40％であつたのと比較して格段に低
減されていることも確認された。 It was also confirmed that the surface reflectance was about 0 to 10%, which was much lower than the 30 to 40% of the conventional device.
以上の如く本発明装置にあつては透明導電膜と
非晶質シリコン層との境界での反射率の低減を図
ると同時に透明導電膜成分のSn、Ｏ等の不純物
が非晶質半導体層へ拡散するのも抑制出来て、発
電効率の向上を寄与するところ多大であるなど、
本発明は優れた効果を奏するものである。
As described above, in the device of the present invention, the reflectance at the boundary between the transparent conductive film and the amorphous silicon layer is reduced, and at the same time impurities such as Sn and O, which are components of the transparent conductive film, are transferred to the amorphous semiconductor layer. It also suppresses diffusion and greatly contributes to improving power generation efficiency.
The present invention has excellent effects.
とりわけ、凹凸化した透明導電膜面上に、この
凹凸化した面を覆うようにノン・ドープで且つ絶
縁性の膜を10〜100Å積層することで、この凹凸
状態の程度を若干緩和し、これにより凸部におけ
る非晶質シリコン層への突き抜けを抑圧する一方
で、その凹凸形状による発電効率の向上を確保す
ることができることとなる。 In particular, by laminating a non-doped insulating film of 10 to 100 Å on the uneven surface of the transparent conductive film so as to cover the uneven surface, the degree of the unevenness can be slightly alleviated. This makes it possible to suppress penetration of the convex portion into the amorphous silicon layer, while ensuring improvement in power generation efficiency due to the uneven shape.
第１図は本発明装置の断面構造図、第２図は本
発明装置における透明導電膜から非晶質シリコン
層への拡散の結果を示すグラフ、第３図は従来装
置における透明導電膜から非晶質シリコン層への
拡散の結果を示すグラフである。
１……透光性絶縁基板、２……透明導電膜、３
……膜、４……非晶質シリコン層、５……裏面電
極膜。
Fig. 1 is a cross-sectional structural diagram of the device of the present invention, Fig. 2 is a graph showing the results of diffusion from the transparent conductive film to the amorphous silicon layer in the device of the present invention, and Fig. 3 is a graph showing the results of diffusion from the transparent conductive film to the amorphous silicon layer in the conventional device. 3 is a graph showing the results of diffusion into a crystalline silicon layer. 1...Transparent insulating substrate, 2...Transparent conductive film, 3
...Membrane, 4...Amorphous silicon layer, 5...Back electrode film.
Claims (1)
に凹凸を有する光の反射防止用の透明導電膜と、
上記表面上に積層された、その凹凸の程度を緩和
するように膜厚を10〜100Åとする、ノン・ドー
プで且つ絶縁性の、SiC、TiC、WC、又はBPを
素材とする１又は複数の膜と、該膜上に積層され
た非晶質シリコン半導体層と、からなることを特
徴とする光起電力装置。1. A transparent substrate, a transparent conductive film formed on the substrate and having an uneven surface for preventing reflection of light,
One or more non-doped and insulating materials made of SiC, TiC, WC, or BP, which are laminated on the above surface and have a film thickness of 10 to 100 Å to reduce the degree of unevenness. 1. A photovoltaic device comprising: a film; and an amorphous silicon semiconductor layer stacked on the film.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59214814A JPS6193672A (en) | 1984-10-12 | 1984-10-12 | Photovoltaic device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59214814A JPS6193672A (en) | 1984-10-12 | 1984-10-12 | Photovoltaic device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6193672A JPS6193672A (en) | 1986-05-12 |
| JPH0574951B2 true JPH0574951B2 (en) | 1993-10-19 |
Family
ID=16661960
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP59214814A Granted JPS6193672A (en) | 1984-10-12 | 1984-10-12 | Photovoltaic device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6193672A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2012195620A (en) * | 2007-02-16 | 2012-10-11 | Mitsubishi Heavy Ind Ltd | Method for manufacturing photoelectric conversion device and photoelectric conversion device |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4829020A (en) * | 1987-10-23 | 1989-05-09 | The United States Of America As Represented By The United States Department Of Energy | Substrate solder barriers for semiconductor epilayer growth |
| JP2706113B2 (en) * | 1988-11-25 | 1998-01-28 | 工業技術院長 | Photoelectric conversion element |
| JPH03136283A (en) * | 1989-10-20 | 1991-06-11 | Sanyo Electric Co Ltd | Photovoltaic device |
| WO2013065557A1 (en) * | 2011-11-01 | 2013-05-10 | 三菱電機株式会社 | Thin-film solar battery cell, method for manufacturing same, and integrated thin-film solar battery |
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|---|---|---|---|---|
| JPS55108780A (en) * | 1979-02-14 | 1980-08-21 | Sharp Corp | Thin film solar cell |
| JPS5857756A (en) * | 1981-10-01 | 1983-04-06 | Agency Of Ind Science & Technol | Amorphous silicon solar battery |
| JPS58192387A (en) * | 1982-04-27 | 1983-11-09 | ア−ルシ−エ− コ−ポレ−シヨン | Photocell |
-
1984
- 1984-10-12 JP JP59214814A patent/JPS6193672A/en active Granted
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS55108780A (en) * | 1979-02-14 | 1980-08-21 | Sharp Corp | Thin film solar cell |
| JPS5857756A (en) * | 1981-10-01 | 1983-04-06 | Agency Of Ind Science & Technol | Amorphous silicon solar battery |
| JPS58192387A (en) * | 1982-04-27 | 1983-11-09 | ア−ルシ−エ− コ−ポレ−シヨン | Photocell |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2012195620A (en) * | 2007-02-16 | 2012-10-11 | Mitsubishi Heavy Ind Ltd | Method for manufacturing photoelectric conversion device and photoelectric conversion device |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6193672A (en) | 1986-05-12 |
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