JPH0793447B2 - Photoelectric conversion element - Google Patents
Photoelectric conversion elementInfo
- Publication number
- JPH0793447B2 JPH0793447B2 JP61053020A JP5302086A JPH0793447B2 JP H0793447 B2 JPH0793447 B2 JP H0793447B2 JP 61053020 A JP61053020 A JP 61053020A JP 5302086 A JP5302086 A JP 5302086A JP H0793447 B2 JPH0793447 B2 JP H0793447B2
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor layer
- amorphous semiconductor
- conductive film
- transparent conductive
- electrode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
- Y02E10/00—Energy generation through renewable energy sources
- Y02E10/50—Photovoltaic [PV] energy
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- Photovoltaic Devices (AREA)
Description
本発明は、透明絶縁基板上に透明導電膜よりなる第一の
電極と、その電極上にPINまたはPN接合を少なくとも一
つ有し、光の入射により光起電力を発生する非晶質半導
体層と、その半導体上に第二の電極（裏面電極）を有す
る光電変換素子に関する。The present invention is an amorphous semiconductor layer which has a first electrode made of a transparent conductive film on a transparent insulating substrate and at least one PIN or PN junction on the electrode, and which generates a photoelectromotive force by incidence of light. And a photoelectric conversion element having a second electrode (back surface electrode) on the semiconductor.
アモルファス・シリンのような非晶質半導体を用いた光
電変換素子の従来技術の例を第２図に示す。平坦な表面
を有するガラス基板１の上にITO,SnO2等の透明導電膜２
を電子ビーム蒸着法、または熱CVD法で１層または２層
に形成することが知られている。この場合、透明導電膜
２の結晶粒を成長させることにより、その表面に径が0.
1〜0.5μｍ程度で深さ0.1〜0.4μｍの凹凸を生ずる。こ
の透明導電膜の上部にPIN接合を有する非晶質半導体層
３のＰ膜31,I膜32,N膜33を積層する。この時，透明導電
膜２の表面の凹凸の深さが0.2未満の場合には非晶質半
導体層の表面の凹凸が積層過程において緩和されるため
に、深さが浅くなってしまう。特に前記非晶質半導体層
を0.5μｍ以上に厚く積層する場合には、凹凸の深さは
0.05μｍ以下となってしまうため、裏面金属電極４との
界面での十分な散乱効果を期待することは出来ず、入射
光を非晶質半導体層３に十分に閉じこめることが出来な
い。逆に、表面凹凸の深さが0.2μｍ以上の場合には、
透明導電膜２の上に形成される非晶質半導体層３にピン
ホールの発生する可能性が増大すること、および透明導
電膜２の表面の凸部５の力学的強度が小さくなり、非晶
質半導体層３堆積時にこの部分で折れてしまい素子の信
頼性が損なわれること、さらに表面凹凸深さの増大とと
もに透明導電膜２の光吸収量が増大してまうことなどの
問題があり、この種の光電変換素子の製造歩留りを大き
く引下げていた。FIG. 2 shows an example of a prior art photoelectric conversion element using an amorphous semiconductor such as amorphous sillin. A transparent conductive film 2 such as ITO or SnO 2 is formed on a glass substrate 1 having a flat surface.
Is known to be formed into one layer or two layers by an electron beam evaporation method or a thermal CVD method. In this case, by growing the crystal grains of the transparent conductive film 2, the diameter of the surface is reduced to 0.
Irregularities with a depth of 0.1 to 0.4 μm occur at about 1 to 0.5 μm. A P film 31, an I film 32, and an N film 33 of the amorphous semiconductor layer 3 having a PIN junction are laminated on the transparent conductive film. At this time, if the depth of the irregularities on the surface of the transparent conductive film 2 is less than 0.2, the irregularities on the surface of the amorphous semiconductor layer are alleviated in the stacking process, and the depth becomes shallow. In particular, when the amorphous semiconductor layer is stacked to a thickness of 0.5 μm or more, the depth of the unevenness is
Since the thickness is 0.05 μm or less, a sufficient scattering effect at the interface with the back surface metal electrode 4 cannot be expected, and the incident light cannot be sufficiently confined in the amorphous semiconductor layer 3. On the contrary, when the depth of the surface irregularities is 0.2 μm or more,
The possibility that pinholes are generated in the amorphous semiconductor layer 3 formed on the transparent conductive film 2 is increased, and the mechanical strength of the projections 5 on the surface of the transparent conductive film 2 is reduced, so that the amorphous semiconductor layer 3 is amorphous. There are problems such as breakage at this portion during deposition of the quality semiconductor layer 3 to impair the reliability of the element, and further increase in the amount of light absorption of the transparent conductive film 2 as the depth of the surface irregularities increases. The production yield of various types of photoelectric conversion elements was greatly reduced.
本発明は、裏面電極の非晶質半導体層側の界面における
光散乱効果を利用してPIN接合あるいはPN接合を有する
非晶質半導体層内部における光路長を増すことにより短
絡電流を増大させるための非晶質半導体層と裏面電極と
の界面の凹凸を、基板側の透明電極を形成する透明導電
膜の表面の凹凸によらないで形成して、製造歩留りを高
くすることのできる光電変換素子を提供することを目的
とする。The present invention aims to increase the short circuit current by increasing the optical path length inside the amorphous semiconductor layer having a PIN junction or a PN junction by utilizing the light scattering effect at the interface of the back electrode on the amorphous semiconductor layer side. A photoelectric conversion element capable of increasing the manufacturing yield by forming the unevenness of the interface between the amorphous semiconductor layer and the back electrode without depending on the unevenness of the surface of the transparent conductive film forming the transparent electrode on the substrate side. The purpose is to provide.
上記の目的を達成するために、本発明によれば、透明絶
縁性基板上に、透明電極と、非晶質半導体層と、裏面電
極とを積層してなる光電変換素子において、裏面電極が
金属裏面電極と透明導電膜とより成り、且つ、この透明
導電膜が、その非晶質半導体層と接する側がほぼ平坦
に、その金属裏面電極と接する側が凹凸形状に形成され
て成ると共に、透明電極の非晶質半導体層と接する側の
表面が、平坦面もしくは裏面電極を成す透明導電膜の凹
凸形状よりも浅い凹凸形状を有する面であることとす
る。これにより、基板上の透明電極を形成する透明導電
膜の表面を深い凹凸形状とすることがないため、非晶質
半導体層成膜時の透明電極表面の損傷ならびに非晶質半
導体層におけるピンホールの発生が起こらない。 〔発明の実施例〕 以下に図を引用して本発明の実施例ならびに本発明の基
礎となる例について説明する。第２図を含めて各図にお
ける共通部分には同一符号が付されている。 先ず、本発明の基礎となる例である第１図について説明
する。 第１図においては、ガラス基板１の上にSnO2またはITO
などを主な成分とする透明電極である透明導電膜２が18
00〜2000Åの厚さに形成され、その透明導電膜２の上に
はＰ膜31,I膜32,N膜33からなるPIN接合（もしくはNIP接
合）を有する、IV族元素に水素またはフッ素等を添加し
た非晶質半導体層３を、0.5〜2.0μｍの厚さで積層し、
その非晶質半導体層３の最後に形成されたＮ膜33の表面
をエッチング処理することにより凹凸を生じせしめ、そ
の後、アルミ，銀等の高反射性金属から裏面電極４およ
び端子電極41を蒸着またはスパッタリング等によって形
成する。前記の凹凸の形状は、NaOH,KOH,ヒドラジン等
を用いて形成できるが、エッチングの条件により深さを
0.01〜1.0μm,径を0.1〜1.5μｍ程度の範囲で制御する
ことが可能である。基板１から入射した光６が裏面電極
４との界面で反射される時に散乱を受ける度合い（散乱
度）を、Ｎ膜33表面の凹凸の深さ0.3μｍにおいて凹凸
径を変化させた場合に波長λの関数として表した線図を
第６図に示す。この構成によれば、非晶質半導体層３表
面の凹凸の粗さを散乱させたい光の波長に合わせて変化
させることにより、ガラス基板１より入射した光６は、
非晶質半導体層３と金属の裏面電極４との界面において
散乱を受けるため、垂直に入射方向に戻る光は減少し、
さらに散乱光のうち入射角の大きいものの大部分は、非
晶質半導体層３と透明導電膜２および透明導電膜２とガ
ラス基板１の間の界面で反射されるため、非晶質半導体
層３から出ていくまでに進む距離が大きく増加し、非晶
質半導体層３内部における光の吸収量が増加し、その光
電変換素子の短絡電流を増大させることが可能となる。
非晶質半導体としてａ−Si:Hを用いた場合、ソーラーシ
ミュレーターAM1,100mW/cm2下で裏面の凹凸が存在しな
い場合の短絡電流密度が14mA/cm2であるのに対して、凹
凸が存在する場合は、16.5mA/cm2の短絡電流を得ること
ができた。 第３図に本発明の第一の実施例を示す。第１図のものと
相違する点は、PIN（またはNIP）接合を有する非晶質半
導体層３を積層した後に、これをエッチングすることな
く、その上にSnO2.またはITO等を主な成分とする透明導
電膜７を形成する点にある。その際に、この透明導電膜
の結晶粒の成長を促進することにより、深さが0.01〜0.
7μm,径が0.1〜1.3μｍの凹凸を生じさせることができ
る。または、一旦平面に透明導電膜を形成した後に、エ
ッチング処理を施すことにより、透明導電膜７の表面
に、深さが0.01〜1.0μm,粒径0.1〜1.5μｍの凹凸を生
じさせることもできる。この透明導電膜７の上部にアル
ミ，銀等の金属の裏面電極４を蒸着，スバッタリング等
の方法で形成する。この構成によれば、第１図において
は裏面での散乱が非晶質半導体層３と金属裏面電極４と
の間で起きたのに対して、本実施例においては、透明導
電膜７と金属裏面電極４との間で散乱が起きる点が異な
っており、散乱度は第１図の例と同様に凹凸の形状の関
数である。 本実施例によれば、第１図の例の構成と比べて、Ｎ膜33
をエッチング処理する必要がなく、プロセスが簡単化さ
れる利点がある。さらに、第１図の例においては、Ｎ膜
33と金属裏面電極４との界面で反射された光が、Ｎ膜33
の内、その厚さが厚い部分で吸収されてしまい、短絡電
流がさして増大しない懸念もあるが、本実施例によれ
ば、Ｎ膜33は薄い平坦な膜なので、そのような問題が生
じることはない。 第４図は、さらに別の本発明の基礎となる例を示すもの
で、ガラス基板１のITOやSnO2等を主成分とする透明電
極である透明導電膜２を形成する際、この透明導電膜の
結晶粒の成長を促進することにより、透明導電膜２の表
面に深さ0.01〜0.18μm,粒径が0.1〜1.5μｍの凹凸を生
じせしめ、その上部にPINまたはNIP接合を有するIV族元
素に水素またはフッ素等を添加した非晶質半導体層３を
0.2〜2.0μｍの厚さで積層する。この非晶質半導体を積
層する過程において横方向の膜厚差緩和が生じるため
に、積層された非晶質半導体層３の表面は透明導電膜２
の表面の凹凸を十分に反映せず、十分な散乱面にはなら
ない。そこで非晶質半導体層３の表面をプラズマエッチ
ング処理することより、その表面に深さが0.01〜1.0μ
m,粒径が0.1〜1.5μｍの凹凸を生ぜしめることができ
る。さらに、その上に金属電極４を蒸着またはスパッタ
リング等によって形成する。この構成によれば、ガラス
基板１から入射した光６は、透明導電膜２と非晶質半導
体層３との界面（第一散乱面）で第一次の散乱を受け
る。さらに入射光は、非晶質半導体層３と裏面電極４と
の界面（第二散乱面）で第二次の散乱を受ける。散乱度
は、第６図に示すように凹凸の深さと粒径により大きく
変化するが、この例においては、第一散乱面と第二散乱
面との凹凸の形状を任意かつ独立に調整することが可能
なために、太陽光線のように広いスペクトル域を有する
光に対しては、第一散乱面と第二散乱面との凹凸形状を
変化させることによって、全波にわたって散乱度を上
げ、全体としての光の光路長を伸ばすことにより非晶質
半導体層内部での光の吸収量を増加させ、光電変換素子
の短絡電流を大きく向上させることが可能となる。第７
図に、非晶質半導体層としてアモルファスシリコンを用
い、第一散乱面の凹凸を深さ0.18μm,粒径を0.3μｍ、
第二散乱面の凹凸を深さ0.2μm,粒径を0.5μｍとした場
合およびいずれの散乱面も持たない場合の光電変換素子
の出力特性を、それぞれ曲線71および72で示す。裏面電
極の金属には銀を用いている。散乱面を持つ場合は、短
絡光電流密度として20mA/cm2が得られている。 第５図に本発明の第二の実施例を示す。この実施例にお
いては、第二散乱面を第３図の実施例と同様に透明導電
膜７により形成する点において、第４図の例とは異なっ
ている。 この第５図の実施例の場合も、第３図の実施例の場合と
同様に、Ｎ膜33をエッチング処理する必要がなく、プロ
セスが簡単化される利点がある。また、第４図の例にお
いては、Ｎ膜33と金属裏面電極４との界面で反射された
光が、Ｎ膜33の内、その厚さが厚い部分で吸収されてし
まい、短絡電流がさして増大しない懸念もあるが、本実
施例によれば、Ｎ膜33は薄い平坦な膜なので、そのよう
な問題が生じることはない。さらに、透明導電膜２と非
晶質半導体層３との界面（第一散乱面）の凹凸は、非晶
質半導体層にピンホールが発生する恐れがあることか
ら、さほど大きくできないが、透明導電膜７と裏面電極
４との界面（第二散乱面）の凹凸の大きさには制約は無
いので、第一散乱面の凹凸より第二散乱面の凹凸を大き
くすることが好ましい。 〔発明の効果〕 本発明によれば、上記の構成を採用した結果、反射光の
散乱度を高くして非晶質半導体層内の光路長を伸ばし、
層内における光の吸収量を増加させて光電変換素子の短
絡光電流を向上させることが可能となった。また、基板
上の透明導電膜の結晶粒の成長を過度にする必要がない
ので、非晶質半導体層に障害が生じることはなく、製造
歩留りの低下を阻止して、高い良品率を得ることができ
る。In order to achieve the above object, according to the present invention, in a photoelectric conversion element formed by stacking a transparent electrode, an amorphous semiconductor layer, and a back electrode on a transparent insulating substrate, the back electrode is made of metal. The transparent conductive film is composed of a back electrode and a transparent conductive film, and the transparent conductive film is formed so that the side in contact with the amorphous semiconductor layer is substantially flat and the side in contact with the metal back electrode is formed in an uneven shape. The surface in contact with the amorphous semiconductor layer is a flat surface or a surface having an uneven shape shallower than the uneven shape of the transparent conductive film forming the back electrode. As a result, the surface of the transparent conductive film forming the transparent electrode on the substrate is not formed into a deep uneven shape, so that the transparent electrode surface is damaged during the formation of the amorphous semiconductor layer and pinholes in the amorphous semiconductor layer are formed. Does not occur. [Examples of the Invention] Examples of the present invention and examples forming the basis of the present invention will be described below with reference to the drawings. Common parts in each drawing, including FIG. 2, are designated by the same reference numerals. First, FIG. 1 which is an example which is the basis of the present invention will be described. In FIG. 1, SnO 2 or ITO is placed on the glass substrate 1.
18 is the transparent conductive film 2 which is a transparent electrode whose main component is
It has a thickness of 00 to 2000Å and has a PIN junction (or NIP junction) consisting of a P film 31, an I film 32, and an N film 33 on the transparent conductive film 2. The amorphous semiconductor layer 3 to which is added is laminated to a thickness of 0.5 to 2.0 μm,
The surface of the N film 33 formed at the end of the amorphous semiconductor layer 3 is subjected to an etching treatment to generate irregularities, and then the back electrode 4 and the terminal electrode 41 are vapor-deposited from a highly reflective metal such as aluminum or silver. Alternatively, it is formed by sputtering or the like. The shape of the unevenness can be formed using NaOH, KOH, hydrazine, etc.
It is possible to control the diameter within the range of 0.01 to 1.0 μm and the diameter within the range of 0.1 to 1.5 μm. The degree to which the light 6 incident from the substrate 1 is scattered when it is reflected at the interface with the back electrode 4 (scattering degree) is the wavelength when the uneven diameter is changed at the uneven depth of 0.3 μm on the surface of the N film 33. A diagram expressed as a function of λ is shown in FIG. According to this configuration, the light 6 incident from the glass substrate 1 is changed by changing the roughness of the irregularities on the surface of the amorphous semiconductor layer 3 in accordance with the wavelength of the light to be scattered.
Since the light is scattered at the interface between the amorphous semiconductor layer 3 and the metal back electrode 4, the light that returns to the incident direction in the vertical direction decreases,
Further, most of the scattered light having a large incident angle is reflected at the interfaces between the amorphous semiconductor layer 3 and the transparent conductive film 2 and between the transparent conductive film 2 and the glass substrate 1, so that the amorphous semiconductor layer 3 The distance traveled from the inside to the outside greatly increases, the amount of light absorbed inside the amorphous semiconductor layer 3 increases, and the short-circuit current of the photoelectric conversion element can be increased.
When a-Si: H is used as the amorphous semiconductor, the short-circuit current density is 14 mA / cm 2 when there is no unevenness on the back surface under the solar simulator AM1,100 mW / cm 2 , whereas the unevenness is When present, a short circuit current of 16.5 mA / cm 2 could be obtained. FIG. 3 shows a first embodiment of the present invention. The difference from FIG. 1 is that after the amorphous semiconductor layer 3 having a PIN (or NIP) junction is laminated, SnO 2 or ITO or the like is the main component on the amorphous semiconductor layer 3 without being etched. Is to form the transparent conductive film 7. At that time, by promoting the growth of crystal grains of the transparent conductive film, the depth is 0.01 to 0.
Irregularities with a diameter of 7 μm and a diameter of 0.1 to 1.3 μm can be generated. Alternatively, the transparent conductive film may be once formed on a flat surface and then subjected to etching treatment to form irregularities having a depth of 0.01 to 1.0 μm and a particle size of 0.1 to 1.5 μm on the surface of the transparent conductive film 7. . A backside electrode 4 made of a metal such as aluminum or silver is formed on the transparent conductive film 7 by a method such as vapor deposition and sputtering. According to this configuration, scattering on the back surface occurs between the amorphous semiconductor layer 3 and the metal back surface electrode 4 in FIG. 1, whereas in this embodiment, the transparent conductive film 7 and the metal back surface electrode 4 are used. The difference is that scattering occurs between the back surface electrode 4 and the back surface electrode 4, and the scattering degree is a function of the shape of the unevenness as in the example of FIG. According to this embodiment, compared with the configuration of the example of FIG.
There is an advantage that the process is simplified because there is no need to perform etching treatment on the. Furthermore, in the example of FIG.
The light reflected at the interface between the metal 33 and the metal back surface electrode 4 is the N film 33.
Among them, there is a concern that the thick film may be absorbed by the thick part and the short-circuit current may not increase, but according to the present embodiment, since the N film 33 is a thin and flat film, such a problem may occur. There is no. FIG. 4 shows another example which is the basis of the present invention. When the transparent conductive film 2 which is a transparent electrode containing ITO, SnO 2 or the like as a main component of the glass substrate 1 is formed, the transparent conductive film 2 is formed. By promoting the growth of crystal grains of the film, irregularities having a depth of 0.01 to 0.18 μm and a grain size of 0.1 to 1.5 μm are formed on the surface of the transparent conductive film 2, and a group IV pin having a PIN or NIP junction is formed on the surface. Amorphous semiconductor layer 3 in which hydrogen or fluorine is added to the element
Laminate with a thickness of 0.2 to 2.0 μm. Since the film thickness difference in the lateral direction is relaxed in the process of stacking the amorphous semiconductors, the surface of the stacked amorphous semiconductor layers 3 is transparent.
It does not sufficiently reflect the unevenness of the surface and does not become a sufficient scattering surface. Therefore, the surface of the amorphous semiconductor layer 3 is plasma-etched so that the surface has a depth of 0.01 to 1.0 μm.
Asperities with m and particle size of 0.1 to 1.5 μm can be produced. Further, the metal electrode 4 is formed thereon by vapor deposition, sputtering or the like. According to this configuration, the light 6 incident from the glass substrate 1 undergoes primary scattering at the interface (first scattering surface) between the transparent conductive film 2 and the amorphous semiconductor layer 3. Further, the incident light undergoes secondary scattering at the interface (second scattering surface) between the amorphous semiconductor layer 3 and the back electrode 4. The degree of scattering greatly changes depending on the depth and particle size of the unevenness as shown in FIG. 6, but in this example, the shapes of the unevenness of the first scattering surface and the second scattering surface can be adjusted arbitrarily and independently. Therefore, for light with a wide spectral range such as sunlight, by changing the uneven shape of the first scattering surface and the second scattering surface, the scattering degree is increased over the entire wave, By extending the optical path length of light as described above, the amount of light absorbed inside the amorphous semiconductor layer can be increased, and the short-circuit current of the photoelectric conversion element can be greatly improved. 7th
In the figure, amorphous silicon is used as the amorphous semiconductor layer, and the unevenness of the first scattering surface has a depth of 0.18 μm and a grain size of 0.3 μm.
Curves 71 and 72 show the output characteristics of the photoelectric conversion element in the case where the unevenness of the second scattering surface is 0.2 μm in depth, the particle size is 0.5 μm, and no scattering surface is provided. Silver is used as the metal of the back electrode. With a scattering surface, a short-circuit photocurrent density of 20 mA / cm 2 was obtained. FIG. 5 shows a second embodiment of the present invention. This embodiment differs from the example of FIG. 4 in that the second scattering surface is formed by the transparent conductive film 7 as in the embodiment of FIG. In the case of the embodiment shown in FIG. 5, as in the case of the embodiment shown in FIG. 3, there is an advantage that the N film 33 need not be etched and the process is simplified. Further, in the example of FIG. 4, the light reflected at the interface between the N film 33 and the metal back surface electrode 4 is absorbed by the thick portion of the N film 33, which causes a short circuit current. According to the present embodiment, the N film 33 is a thin and flat film, but such a problem does not occur, although there is a concern that it will not increase. Further, the unevenness of the interface (first scattering surface) between the transparent conductive film 2 and the amorphous semiconductor layer 3 cannot be increased so much because a pinhole may be generated in the amorphous semiconductor layer. Since the size of the unevenness on the interface (second scattering surface) between the film 7 and the back electrode 4 is not limited, it is preferable to make the unevenness on the second scattering surface larger than the unevenness on the first scattering surface. [Advantages of the Invention] According to the present invention, as a result of adopting the above configuration, the degree of scattering of reflected light is increased and the optical path length in the amorphous semiconductor layer is extended,
It has become possible to improve the short-circuit photocurrent of the photoelectric conversion element by increasing the amount of light absorbed in the layer. Further, since it is not necessary to excessively grow the crystal grains of the transparent conductive film on the substrate, the amorphous semiconductor layer is not hindered, the production yield is prevented from lowering, and a high yield rate is obtained. You can
第１図は本発明の基礎となる例の断面図、第２図は従来
例の断面図、第３図は本発明の第一の実施例の断面図、
第４図は本発明の基礎となる別の例の断面図、第５図は
本発明の第二の実施例の断面図、第６図は反射面の凹凸
径をパラメータとした、光の散乱度と波長との関係線
図、第７図は第４図に示した例と従来例との、出力特性
線図である。 1:ガラス基板、2,7:透明導電膜、3:非晶質半導体層、4:
金属裏面電極。FIG. 1 is a sectional view of an example which is a basis of the present invention, FIG. 2 is a sectional view of a conventional example, and FIG. 3 is a sectional view of a first embodiment of the present invention.
FIG. 4 is a cross-sectional view of another example which is the basis of the present invention, FIG. 5 is a cross-sectional view of the second embodiment of the present invention, and FIG. 6 is the scattering of light with the uneven diameter of the reflecting surface as a parameter. FIG. 7 is an output characteristic diagram of the relationship shown in FIG. 4 and the conventional example. 1: glass substrate, 2, 7: transparent conductive film, 3: amorphous semiconductor layer, 4:
Metal back electrode.
Claims (1)
半導体層と、裏面電極とを積層してなる光電変換素子に
おいて、裏面電極が金属裏面電極と透明導電膜とより成
り、且つ、この透明導電膜が、その非晶質半導体層と接
する側がほぼ平坦に、その金属裏面電極と接する側が凹
凸形状に形成されて成ると共に、透明電極の非晶質半導
体層と接する側の表面が、平坦面もしくは裏面電極を成
す透明導電膜の凹凸形状よりも浅い凹凸形状を有する面
であることを特徴とする光電変換素子。1. A photoelectric conversion device comprising a transparent insulating substrate, a transparent electrode, an amorphous semiconductor layer, and a back electrode laminated on a transparent insulating substrate, wherein the back electrode comprises a metal back electrode and a transparent conductive film. Further, the transparent conductive film is formed such that the side in contact with the amorphous semiconductor layer is substantially flat and the side in contact with the metal back surface electrode is formed in an uneven shape, and the surface of the transparent electrode in contact with the amorphous semiconductor layer is formed. Is a surface having a flat surface or an uneven shape that is shallower than the uneven shape of the transparent conductive film that forms the back electrode.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61053020A JPH0793447B2 (en) | 1986-03-11 | 1986-03-11 | Photoelectric conversion element |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61053020A JPH0793447B2 (en) | 1986-03-11 | 1986-03-11 | Photoelectric conversion element |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS62209872A JPS62209872A (en) | 1987-09-16 |
| JPH0793447B2 true JPH0793447B2 (en) | 1995-10-09 |
Family
ID=12931215
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61053020A Expired - Fee Related JPH0793447B2 (en) | 1986-03-11 | 1986-03-11 | Photoelectric conversion element |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0793447B2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102822991A (en) * | 2010-04-05 | 2012-12-12 | 三菱电机株式会社 | Substrate for photoelectric conversion device, method for manufacturing the substrate, thin film photoelectric conversion device, method for manufacturing the device, and solar cell module |
Families Citing this family (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0423149U (en) * | 1990-06-13 | 1992-02-26 | ||
| US5045908A (en) * | 1990-09-25 | 1991-09-03 | Motorola, Inc. | Vertically and laterally illuminated p-i-n photodiode |
| EP1100130B3 (en) * | 1998-06-01 | 2008-10-29 | Kaneka Corporation | Silicon-base thin-film photoelectric device |
| EP1766690A1 (en) * | 2004-07-07 | 2007-03-28 | Saint-Gobain Glass France S.A. | Photovoltaic solar cell and solar module |
| JP2009260270A (en) * | 2008-03-26 | 2009-11-05 | Nippon Synthetic Chem Ind Co Ltd:The | Solar cell substrate and solar cell |
| US20110108118A1 (en) * | 2008-07-07 | 2011-05-12 | Mitsubishi Electric Corporation | Thin-film solar cell and method of manufacturing the same |
| WO2010023867A1 (en) * | 2008-08-25 | 2010-03-04 | 株式会社エバテック | Thin-film solar cell and manufacturing method therefore and substrate for thin-film solar cell |
| JP2013004805A (en) * | 2011-06-17 | 2013-01-07 | Jx Nippon Oil & Energy Corp | Photoelectric conversion element |
| JP2013004535A (en) * | 2011-06-10 | 2013-01-07 | Jx Nippon Oil & Energy Corp | Photoelectric conversion element |
| CN103597603A (en) * | 2011-06-10 | 2014-02-19 | 吉坤日矿日石能源株式会社 | Photoelectric conversion element |
| JP6788657B2 (en) * | 2016-03-10 | 2020-11-25 | 株式会社カネカ | Solar cell module |
-
1986
- 1986-03-11 JP JP61053020A patent/JPH0793447B2/en not_active Expired - Fee Related
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102822991A (en) * | 2010-04-05 | 2012-12-12 | 三菱电机株式会社 | Substrate for photoelectric conversion device, method for manufacturing the substrate, thin film photoelectric conversion device, method for manufacturing the device, and solar cell module |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS62209872A (en) | 1987-09-16 |
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