JPH0574186A - Integrated circuit - Google Patents

Abstract

PURPOSE:To reduce the number of terminals for test use which are installed at an LSI chip with a built-in ROM. CONSTITUTION:When address changeover circuits 3, 4 select a signal from a test address terminal 2 by means of an indication signal from a test indication terminal 1, the same address is given to ROMs 10, 11. Data which have been read out form the ROMs 10, 11 are input respectively to a data comparison circuit 5. A comparison result is output to the outside of an LSI 7 from a noncoincidence-result output terminal 6.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention is used as an LSI chip having a ROM therein. The present invention relates to an LSI chip capable of reducing the number of test terminals.

[0002]

2. Description of the Related Art Conventionally, this type of microprogram is
In a test of an LSI that is built in the OM and executes instructions, data must be confirmed by reading all words. Therefore, in the case of a ROM storing a microprogram, a ROM test mode is provided and the ROM address is incremented by one. An enormous amount of test patterns are used to read all words unless they have the means.

In order to confirm the read data, it is necessary to output the data to an external terminal of the LSI and observe the data. Therefore, observation terminals for the data width are provided.

The number of observation terminals increases with the expansion of the data width of the microinstruction, and on the contrary, L
Since SI has a limited number of physical terminals, data has been divided into two to be output and tested, and many test patterns are still used.

[0005]

As described above, the integrated circuit according to the prior art requires observation terminals for the data width in order to confirm the data read from the built-in ROM, and the number of test observation terminals cannot be reduced. There's a problem.

The present invention solves such a problem, and an object thereof is to provide an integrated circuit in which the number of test terminals can be reduced.

[0007]

The first object of the present invention is to provide a built-in ROM, a ROM address counter for supplying an address signal to an address input of the ROM, a test address terminal, and an address input of the ROM. In an integrated circuit including an address switching circuit that is switched and connected to either a ROM address counter or the test address terminal, and a test instruction terminal that inputs a control signal of the address switching circuit, the ROM and the address switching circuit are provided. The same circuit is provided in two systems, the signal of the test address terminal is commonly connected to the inputs of the two address switching circuits, and the data comparison circuits of the read outputs of the two ROMs and the disagreement between the data comparison circuits are output. And a mismatch result output terminal.

A second aspect of the present invention is a built-in ROM and an RO which supplies an address signal to an address input of this ROM.
M address counter, test address terminal, RO
An integrated circuit having an address switching circuit for switching and connecting the address input of M to either the ROM address counter or the test address terminal, and a test instruction terminal for inputting a control signal of the address switching circuit, wherein the ROM Test expected value data terminal for inputting the expected value of the read output, a data comparison circuit for comparing the signal of the test expected value data terminal with the read output of the ROM, and a mismatch result for outputting a mismatch of the data comparison circuit. And an output terminal.

[0009]

When the integrated circuit has two ROMs,
By the instruction input from the test instruction terminal, the two address switching circuits select the signal from the test address terminal in advance and give the same address to the two ROMs.
The data read from the OM is input to the data comparison circuit, and the comparison result is output from the mismatch result output terminal to the outside of the integrated circuit. As a result, the number of test terminals can be significantly reduced.

Further, in the case of an integrated circuit incorporating one ROM, the address switching circuit selects a signal from the test address terminal by an instruction input from the test instruction terminal,
An address is given to the ROM, the data read from this ROM and the data input from the test expected value data terminal are input to the data comparison circuit, and the comparison result is output from the mismatch result output terminal to the outside of the integrated circuit. It In this case as well, the number of test terminals can be greatly reduced.

[0011]

Embodiments of the present invention will now be described with reference to the drawings.

(First Embodiment) FIG. 1 is a block diagram showing the configuration of the first embodiment of the present invention.

The first embodiment of the present invention has two ROMs 10 and 11 for storing the same data therein, and has two test instruction terminals 1, a test address terminal 2 and two when a true signal is input to the test instruction terminal 1. Address switching circuits 3 and 4 for giving the addresses input from the test address terminal 2 to the ROMs 10 and 11, and two ROMs 10 and 1.
Data comparison circuit 5 for comparing the data read from 1
And a mismatch result output terminal 6 for outputting the comparison result as a mismatch signal to a specific LSI terminal, ROM address counters 8 and 9, and ROM data decoders 12 and 13.

A signal for instructing a normal operation or a ROM test operation to the address switching circuits 3 and 4 is input to the test instruction terminal 1, and an m-bit signal to the address switching circuits 3 and 4 is input to the test address terminal 2. Signal is input.

The address switching circuit 3 selects the signal from the ROM address counter 8 in the normal operation, the signal from the test address terminal 2 in the ROM test operation, and the ROM 10 according to the instruction signal from the test instruction terminal 1.
An m-bit address signal is input to. Further, the address switching circuit 4 selects the signal from the ROM address counter 9 during the normal operation by the instruction signal from the test instruction terminal 1 and selects the signal from the test address terminal 2 during the ROM test operation.
Signal is input, and an m-bit address signal is input to the ROM 11.

The data comparison circuit 5 includes a ROM 10 and a ROM.
N bits of data are respectively inputted from 11 and bits of the same weight of these two data are operated by exclusive OR, and the operation result of n bits of data is operated by OR to obtain the data of the same address. If even 1 bit does not match, true is output.

The mismatch result output terminal 6 outputs the comparison result of the data comparison circuit 5 to the outside of the LSI 7. ROM
The address counter 8 stores the microinstruction address to be executed, gives the m-bit address signal to the ROM 10 by the address switching circuit 3, and the ROM address counter 9 stores the microinstruction address to be executed, and the address switching circuit. 4, an m-bit address signal is given to the ROM 11.

The ROM 10 contains the same microprogram as the ROM 11, and the address switching circuit 3 supplies m
Input the address of the bit, ROM data decoder 12
The n-bit micro instruction is output to
The same microprogram as OM10 is built in, and an m-bit address is input from the address switching circuit 4 and RO
An n-bit micro instruction is output to the M data decoder 13. The ROM data decoder 12 reads the microinstruction to be executed from the ROM 10 and decodes the instruction, and RO
The M data decoder 13 reads a micro instruction to be executed from the ROM 11 and decodes the instruction.

During normal operation, the ROMs 10 and 11 are
Addresses are provided by independent ROM address counters 8 and 9, respectively, and analyzed by ROM data decoders 12 and 13 to operate independently.

The LSI 7 is operated by an instruction from the test instruction terminal 1.
In the test state of the ROMs 10 and 11, the signals from the test address terminal 2 are selected by the address switching circuits 3 and 4, and the same address is given to the ROMs 10 and 11. The data read from the ROMs 10 and 11 are input to the data comparison circuit 5, and the comparison result is output to the mismatch result output terminal 6. When the start address and the final address of the ROM 10 or 11 are given from the test address terminal 2, the ROM 10 and 11 are
It is confirmed whether or not there is a mismatch for all the data of all the words.

(Second Embodiment) FIG. 2 is a block diagram showing the configuration of the second embodiment of the present invention.

In the second embodiment, one ROM 29 for storing the same data is built in, and true is input to the test instruction terminal 21, the test address terminal 22, the test expected value data terminal 23, and the test instruction terminal 21. An address switching circuit 24 that gives an address input from the test address terminal 22 to the ROM 29 at some times, a data comparison circuit 25 that compares the data input from the test expected value data terminal 23 with the output data from the ROM 29, and their comparison. A mismatch result output terminal 26 for outputting the result as a mismatch signal to a specific LSI terminal, a ROM address counter 28, and a ROM data decoder 30 are provided.

A test instructing a normal operation or a ROM test operation of the address switching circuit 24 is input to the test instruction terminal 21, and an m-bit signal to the address switching circuit 24 is input to the test address terminal 22. The n-bit signal to the data comparison circuit 25 is directly input to the test expected value data terminal 23.

The address switching circuit 24 selects the signal from the ROM address counter 28 during the normal operation by the instruction signal from the test instruction terminal 21, and selects the signal from the test address terminal 22 during the ROM test operation.
An m-bit address signal is input to M29.

The data comparison circuit 25 inputs n-bit data from the ROM 29 and the test expected value data terminal 23, respectively, calculates bits of the same weight of two data by exclusive OR, and at the same time, outputs n-bit data. The operation result of is calculated by a logical sum, and true is output if the data at the same address has even one bit mismatch.

The mismatch result output terminal 26 outputs the comparison result of the data comparison circuit 25 to the outside of the LSI 27.
The ROM address counter 28 stores the microinstruction address to be executed, and the address switching circuit 24 stores the R instruction.
An m-bit address signal is given to the OM 29.

The ROM 29 has an address switching circuit 24.
An m-bit address is input, and an n-bit micro instruction is output to the ROM data decoder 30. The ROM data decoder 30 reads a micro instruction to be executed from the ROM 29 and decodes the instruction.

During normal operation, the ROM 29 is operated by being given an address by the ROM address counter 28 and analyzed by the ROM data decoder 30.

The test instruction terminal 21 causes the LSI 27 to
In the test state of M29, the address switching circuit 24
Selects the signal from the test address terminal 22 by
An address is given to the OM 29. The data read from the ROM 29 and the data input from the test expected value data terminal 23 are input to the data comparison circuit 25,
When the start address and the final address of the ROM 29 are given, it is confirmed whether or not there is a mismatch in all the data of all the words of the ROM 29.

[0030]

As described above, according to the present invention, the number of test terminals can be reduced.

[Brief description of drawings]

FIG. 1 is a block diagram showing the configuration of a first embodiment of the present invention.

FIG. 2 is a block diagram showing the configuration of a second embodiment of the present invention.

[Explanation of symbols]

 1, 21 Test instruction terminal 2, 22 Test address terminal 3, 4, 24 Address switching circuit 5, 25 Data comparison circuit 6, 26 Mismatch result output terminal 7, 27 LSI 8, 9, 28 ROM address counter 10, 11, 29 ROM 12, 13, 30 ROM data decoder 23 Test expected value data terminal

Claims (2)

[Claims] 1. A built-in ROM and an R for supplying an address signal to an address input of the ROM.
An OM address counter, a test address terminal, an address switching circuit for switching and connecting the address input of the ROM to either the ROM address counter or the test address terminal, and a test instruction for inputting a control signal of the address switching circuit. In the integrated circuit having a terminal, the same circuit as the ROM and the address switching circuit is provided in two systems, and the signal of the test address terminal is commonly connected to the inputs of the two address switching circuits. An integrated circuit comprising a read output data comparison circuit and a mismatch result output terminal for outputting a mismatch of the data comparison circuit. 2. A built-in ROM and an R for supplying an address signal to an address input of the ROM
An OM address counter, a test address terminal, an address switching circuit for switching and connecting the address input of the ROM to either the ROM address counter or the test address terminal, and a test instruction for inputting a control signal of the address switching circuit. An integrated circuit having a terminal, a test expected value data terminal for inputting an expected value of the read output of the ROM, and a data comparison circuit for comparing a signal of the test expected value data terminal with the read output of the ROM, An integrated circuit having a mismatch result output terminal for outputting a mismatch of the data comparison circuit.