JPH0573342B2 - - Google Patents

Info

Publication number
JPH0573342B2
JPH0573342B2 JP63295413A JP29541388A JPH0573342B2 JP H0573342 B2 JPH0573342 B2 JP H0573342B2 JP 63295413 A JP63295413 A JP 63295413A JP 29541388 A JP29541388 A JP 29541388A JP H0573342 B2 JPH0573342 B2 JP H0573342B2
Authority
JP
Japan
Prior art keywords
input
output
pellet
terminal
terminals
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP63295413A
Other languages
Japanese (ja)
Other versions
JPH02142154A (en
Inventor
Koji Murakami
Takashi Kimura
Kazuo Endo
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tokyo Shibaura Electric Co Ltd filed Critical Tokyo Shibaura Electric Co Ltd
Priority to JP63295413A priority Critical patent/JPH02142154A/en
Publication of JPH02142154A publication Critical patent/JPH02142154A/en
Publication of JPH0573342B2 publication Critical patent/JPH0573342B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
    • H01L2224/49113—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting different bonding areas on the semiconductor or solid-state body to a common bonding area outside the body, e.g. converging wires
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49175—Parallel arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01014—Silicon [Si]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/0132—Binary Alloys
    • H01L2924/01322—Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/156—Material
    • H01L2924/15786—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
    • H01L2924/15787—Ceramics, e.g. crystalline carbides, nitrides or oxides

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Description

【発明の詳細な説明】 ［発明の目的］ （産業上の利用分野） この発明は半導体装置に係り、特に高周波電力
増幅用のMOS型電界効果トランジスタに関する。DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Application Field) The present invention relates to a semiconductor device, and particularly to a MOS field effect transistor for high frequency power amplification.

（従来の技術） MOS型電界効果トランジスタは熱暴走しにく
い等の利点があり、複数のトランジスタの並列に
接続することによつて必要な出力電力を容易に確
保することができるため、電力増幅陽としてバイ
ポーラ型トランジスタに代わつて用いられるよう
になつてきた。(Prior technology) MOS type field effect transistors have the advantage of being less prone to thermal runaway, and the necessary output power can be easily secured by connecting multiple transistors in parallel, making it possible to use power amplification systems. As a result, they have come to be used in place of bipolar transistors.

第５図は高周波電力増幅用としてMOS型電界
効果トランジスタ（以下、MOS FETと称する）
を用いた従来の半導体装置の斜視図である。１１
はMOS FETペレツトであり、金属パツケージ
１２内に装着されている。１３は入力端子、１４
は出力端子であり、MOS FETペレツト１１に
設けられた入力パツド１５、出力パツド１６のそ
れぞれと複数の金属線１７によつて配線されてい
る。端子１３及び１４は絶縁基板１８によつて金
属パツケージ１２からは絶縁されている。また、
この入力端子１３及び出力端子１４以外の端子は
接地端子１９であり、金属パツケージ１２と導通
している。 Figure 5 shows a MOS field effect transistor (hereinafter referred to as MOS FET) used for high frequency power amplification.
1 is a perspective view of a conventional semiconductor device using a semiconductor device; 11
is a MOS FET pellet, which is mounted inside a metal package 12. 13 is an input terminal, 14
is an output terminal, which is wired by a plurality of metal wires 17 to each of an input pad 15 and an output pad 16 provided on the MOS FET pellet 11. Terminals 13 and 14 are insulated from metal package 12 by an insulating substrate 18. Also,
Terminals other than the input terminal 13 and output terminal 14 are ground terminals 19 and are electrically connected to the metal package 12.

上記構成の半導体装置の等価回路を第６図に示
す。上記MOS FETペレツト１１は複数のMOS
FET２０によつて構成されており、これらすべ
てのMOS FET２０のソースは共通に接続され
て接地されており、かつ何個かごとにゲート及び
ドレインがそれぞれ共通接続され、各共通ゲート
が前記パツド１５に、各共通ドレインが前記パツ
ド１６にそれぞれ接続されている。そして、各パ
ツド１５及び１６は前記各金属線１７によつて前
記入力端子１３、出力端子１４にそれぞれ共通に
接続されている。また、MOS FETペレツト１
１の共通ソースはペレツト裏面から接地電極とし
て取出され、第４図に示すように金属パツケージ
１２に接着される。 FIG. 6 shows an equivalent circuit of the semiconductor device having the above structure. The above MOS FET pellet 11 consists of multiple MOS
The sources of all these MOS FETs 20 are commonly connected and grounded, and the gates and drains of each MOS FET 20 are commonly connected, and each common gate is connected to the pad 15. , each common drain is connected to the pad 16, respectively. The pads 15 and 16 are commonly connected to the input terminal 13 and the output terminal 14 by the metal wires 17, respectively. Also, MOS FET pellet 1
One common source is taken out from the backside of the pellet as a ground electrode and is bonded to a metal package 12 as shown in FIG.

ところで、従来装置では第５図に示すように入
力端子１３及び出力端子１４のそれぞれ両側に接
地端子１９を配置するようにしているので、両端
子１３，１４の幅は小さくなつている。これに対
し、ペレツト１１は、第６図に示すように、複数
個のMOS FET２０で構成されているため、そ
の幅は大きくなつている。また、ペレツト自体の
熱抵抗を低減させるためにもその幅を大きくする
必要がある。一方、MOS FETペレツト１１で
は、各MOS FET２０のペレツト内の位置に基
づく動作の不均一を避けるためと、金属線１７が
互いに重ならないようにするための目的から、入
力パツド１５及び出力パツド１６は図示のように
複数個に分けて配列されている。従つて、ペレツ
ト１１の入力パツド１５及び出力パツド１６と入
力端子１３及び出力端子１４とを接続する場合
に、パツド１５，１６の位置により、前記金属線
１７の長さに差が生じる。この結果、入出力電力
の位相差が発生して電力損失が生じる。この位相
差は周波数が高くなるほど大きくなり、これに伴
つて電力損失が増大する。 By the way, in the conventional device, as shown in FIG. 5, the ground terminals 19 are arranged on both sides of the input terminal 13 and the output terminal 14, so the widths of both terminals 13 and 14 are reduced. On the other hand, since the pellet 11 is composed of a plurality of MOS FETs 20 as shown in FIG. 6, its width is large. Further, in order to reduce the thermal resistance of the pellet itself, it is necessary to increase its width. On the other hand, in the MOS FET pellet 11, the input pad 15 and the output pad 16 are arranged in order to avoid uneven operation based on the position of each MOS FET 20 within the pellet, and to prevent the metal lines 17 from overlapping each other. As shown in the figure, they are divided into a plurality of pieces and arranged. Therefore, when connecting the input pad 15 and output pad 16 of the pellet 11 to the input terminal 13 and output terminal 14, the length of the metal wire 17 varies depending on the position of the pads 15 and 16. As a result, a phase difference occurs between input and output power, resulting in power loss. This phase difference becomes larger as the frequency becomes higher, and power loss increases accordingly.

（発明が解決しようとする課題） 従来装置では金属パツケージ以外に入出力端子
の両側に接地端子を設けるようにしているため
に、入出力端子の幅が狭くなり、ペレツト上の入
出力パツドと、入出力端子とを接続する金属線の
長さが不均一となり、この結果、入出力電力間に
位相差が発生し、電力損失が大きくなるという欠
点がある。(Problems to be Solved by the Invention) In the conventional device, ground terminals are provided on both sides of the input/output terminal other than the metal package, so the width of the input/output terminal becomes narrow, and the input/output pad on the pellet, The disadvantage is that the lengths of the metal wires connecting the input and output terminals are non-uniform, resulting in a phase difference between the input and output power, resulting in increased power loss.

この発明は上記事情を考慮してなされたもので
あり、その目的は、半導体ペレツト上の電極パツ
ドと入出力端子との接続部分に生じる位相差を抑
え、入出力電力間の電力損失を小さくする半導体
装置を提供することにある。 This invention was made in consideration of the above circumstances, and its purpose is to suppress the phase difference that occurs at the connection between the electrode pad on the semiconductor pellet and the input/output terminal, and to reduce the power loss between input and output power. The purpose of the present invention is to provide semiconductor devices.

［発明の構成］ （課題を解決するための手段） この発明の半導体装置は、ソースが共通に接続
された複数のMOS型電界効果型トランジスタを
備え、一方面は接地電極面となり、他方面は複数
個の入力電極及び出力電極がそれぞれ配列する半
導体ペレツト、基台部及びこの基台部と一体的に
形成された凸部からなり、上記凸部には上記半導
体ペレツトが装着される接地電極用の領域がある
金属性の外囲器と、上記凸部の周縁部上に固着さ
れた絶縁性基板と、上記絶縁性基板上において上
記半導体ペレツトの長辺の長さと同等、もしくは
それ以上の領域でこの半導体ペレツトの長辺に対
し互いに対向するように接着されそれぞれ端部ま
で同じ幅で伸びる入力端子及び出力端子と、上記
入力端子及び出力端子それぞれと上記半導体ペレ
ツトの入力電極と出力電極それぞれとを接続する
各配線距離が均等な複数の配線とから構成され
る。[Structure of the Invention] (Means for Solving the Problems) A semiconductor device of the present invention includes a plurality of MOS field effect transistors whose sources are commonly connected, one surface serving as a ground electrode surface and the other surface serving as a ground electrode surface. It consists of a semiconductor pellet on which a plurality of input electrodes and output electrodes are arranged, a base part, and a convex part formed integrally with the base part, and the convex part is used for a ground electrode on which the semiconductor pellet is attached. an insulating substrate fixed on the peripheral edge of the convex portion, and an area on the insulating substrate that is equal to or longer than the length of the long side of the semiconductor pellet. An input terminal and an output terminal are bonded to face each other on the long sides of the semiconductor pellet and each extend to the end with the same width, and each of the input terminal and output terminal is connected to the input and output electrodes of the semiconductor pellet, respectively. It consists of a plurality of wires with equal distance between each wire.

（作用） 半導体ペレツトの裏面より接続を持つ金属パツ
ケージ自体のみを接地端子とし、他には接地端子
を持たない構成にすることにより、入出力端子が
幅広く取れる。これにより、ペレツト上の電極パ
ツドと入出力端子との接続線の長さを均等にし、
その部分での入出力電力の位相差を抑える。(Function) A wide range of input/output terminals can be obtained by making the metal package itself, which is connected from the back side of the semiconductor pellet, the only grounding terminal and having no other grounding terminals. This makes the lengths of the connection lines between the electrode pads on the pellet and the input/output terminals equal, and
Suppress the phase difference between input and output power in that area.

（実施例） 以下、図面を参照してこの発明を実施例により
説明する。(Examples) Hereinafter, the present invention will be explained by examples with reference to the drawings.

第１図はこの発明を高周波電力増幅用として
MOS型電界効果トランジスタ（以下、MOS
FETと称する）を用いた半導体装置に実施した
場合の斜視図である。１はMOS FETペレツト
である。また、２はCu系合金からなる金属パツ
ケージであり、両端部に取付け用の孔が設けられ
た基台部と、この基台部と一体的に形成され、ペ
レツト１が装着される溝を持つた凸部分から構成
されている。上記MOS FETペレツト１はこの
金属パツケージ２の溝内に納められ、Al−Si共
晶半田によつて接着されている。３は入力端子、
４は出力端子であり、パツケージ２の凸部分の周
辺上に接着されたセラミツク基板５上に互いに対
向するように、ろう付けにより接着されている。
この入出力端子３，４はMOS FETペレツト１
上に設けられた複数の入力パツド６、出力パツド
７のそれぞれとアルミニウム配線８によつて最短
距離で配線されている。 Figure 1 shows this invention applied to high frequency power amplification.
MOS field effect transistor (hereinafter referred to as MOS
FIG. 2 is a perspective view of a semiconductor device using a semiconductor device (referred to as FET). 1 is a MOS FET pellet. In addition, 2 is a metal package made of a Cu-based alloy, and has a base part with holes for mounting at both ends, and a groove formed integrally with this base part, into which the pellet 1 is installed. It is made up of convex parts. The MOS FET pellet 1 is placed in the groove of the metal package 2 and bonded with Al--Si eutectic solder. 3 is the input terminal,
Reference numeral 4 designates output terminals, which are bonded by brazing to a ceramic substrate 5 bonded on the periphery of the convex portion of the package 2 so as to face each other.
These input/output terminals 3 and 4 are MOS FET pellet 1
A plurality of input pads 6 and output pads 7 provided above are connected to each other by aluminum wiring 8 at the shortest distance.

この発明の装置では周波数770MHz以上で出力
50Wを達成するため、MOS FETペレツト１は
幅（図中Ａ）が８mmのもの使用している。この
MOS FETペレツト１は、ソース電極は裏面か
ら取りだすソース接地型である。そこで、パツケ
ージ２が接地端子を兼ねており、他には接地端子
を設けていない。従つて、入力端子３、出力端子
４は共に幅広く取ることができる。従来、この幅
は3.2mm程度であつたが、ここではMOS FETペ
レツト１の幅（図中Ａ）よりも広い10mmの端子を
設けている。この入出力端子３，４とMOS
FETペレツト１上に設けられているパツド６，
７とをそれぞれ接続するアルミニウム配線８は同
じ長さ、断面形状の例えば直径50μｍのものを使
用する。 The device of this invention outputs at a frequency of 770MHz or higher.
In order to achieve 50W, a MOS FET pellet 1 with a width (A in the figure) of 8 mm is used. this
The MOS FET pellet 1 is a source-grounded type in which the source electrode is taken out from the back side. Therefore, the package cage 2 also serves as a ground terminal, and no other ground terminal is provided. Therefore, both the input terminal 3 and the output terminal 4 can be wide. Conventionally, this width was about 3.2 mm, but here the terminal is 10 mm wider than the width of the MOS FET pellet 1 (A in the figure). These input/output terminals 3 and 4 and MOS
Pad 6 provided on FET pellet 1,
The aluminum wires 8 that connect the wires 7 and 7 are of the same length and cross-sectional shape, for example, 50 μm in diameter.

このように、パツケージ２以外は接地端子を設
けず、入出力端子を共に幅広い構成にすることに
より、MOS FETペレツト１の入出力パツド６，
７と入出力端子３，４とは同じ長さ、同じ断面形
状のアルミニウム配線８により接続することがで
きる。従つて、従来のような入出力電力の位相差
は極めて小さくなり、電力損失を防ぐことができ
る。 In this way, by not providing a grounding terminal except for the package 2, and by making the input and output terminals have a wide configuration,
7 and the input/output terminals 3 and 4 can be connected by aluminum wiring 8 having the same length and the same cross-sectional shape. Therefore, the phase difference between input and output power as in the conventional case becomes extremely small, and power loss can be prevented.

上記実施例装置では従来装置と比較して周波数
700〜900MHzにおいて、出力電力が31.1％増加
し、ドレイン効率も28.0％の特性改善を達成する
ことができた。 The above example device has a higher frequency than the conventional device.
From 700 to 900MHz, the output power increased by 31.1% and the drain efficiency improved by 28.0%.

第２図は他の実施例を示す斜視図であり、上記
入出力端子３，４をそれぞれ２個に分割したもの
である。この実施例では、入力端子３1と３2との
間及び出力端子４1と４2との間にはセラミツク基
板５とのろう付けの際に使用された金属膜（例え
ばAu）９が残存しており、分割された端子は互
いに導通している。このようにすれば１つの端子
の幅が小さくでき、装置への取付け、配線等の適
宜が図れる。しかも、第１図実施例と同様の効果
が得られる。 FIG. 2 is a perspective view showing another embodiment, in which the input/output terminals 3 and 4 are each divided into two. In this embodiment, a metal film (for example, Au) 9 used during brazing with the ceramic substrate 5 remains between the input terminals 3 1 and 3 2 and between the output terminals 4 1 and 4 2 . The divided terminals are electrically connected to each other. In this way, the width of one terminal can be made small, and attachment to the device, wiring, etc. can be made as appropriate. Moreover, the same effects as in the embodiment of FIG. 1 can be obtained.

第３図はこの発明のもう１つの他の実施例であ
り、上記第２図実施例の残存している金属膜（例
えばAu）９をその後の工程で除去し、セラミツ
ク基板５を露出させたものである。これにより、
入力端子３1と３2との間及び出力端子４1と４2と
の間は絶縁される。このようにすれば、例えば第
４図に示すようなプツシユプル増幅回路を構成す
るときの適宜が図れる。図示しないドライバーか
らトランスT1を介して入力端子３1と３2に相補な
信号電圧が供給されると２組のMOS FET２０
が交互にオンしてバイアス電圧Ｖにより出力端子
４1と４2間に接続されたトランスT2を介して負荷
Ｒに増幅された出力が得られる。この場合、第１
図の実施例と同様に入力端子３1，３2と出力端子
４1，４2と間の入出力電力の位相差は極めて小さ
くなり、プツシユプル動作時における電力損失が
大幅に改良される。 FIG. 3 shows another embodiment of the present invention, in which the remaining metal film (for example, Au) 9 of the embodiment of FIG. 2 is removed in a subsequent process to expose the ceramic substrate 5. It is something. This results in
Insulation is provided between input terminals 3 1 and 3 2 and between output terminals 4 1 and 4 2 . In this way, it is possible to suitably configure a push-pull amplifier circuit as shown in FIG. 4, for example. When complementary signal voltages are supplied to input terminals 3 1 and 3 2 from a driver (not shown) via a transformer T 1 , two sets of MOS FETs 20
are alternately turned on, and an amplified output is provided to the load R via the transformer T 2 connected between the output terminals 4 1 and 4 2 by the bias voltage V. In this case, the first
Similar to the embodiment shown in the figure, the phase difference between the input and output power between the input terminals 3 1 , 3 2 and the output terminals 4 1 , 4 2 becomes extremely small, and the power loss during push-pull operation is greatly improved.

なお、この発明は上記実施例に限定されるもの
ではなく、種々の変形が可能である。例えば第２
図、第３図において、入力端子３及び出力端子４
をそれぞれ２個に分割した場合について説明した
が、この端子数は限定せず、入出力パツドとの接
続線の長さ、断面形状が均一にできればよい。ま
た、上記実施例では入出力パツドと各端子との接
続はアルミニウム線により行つたが、その種類も
長さ、断面形状が均一であれば限定はされない。 Note that this invention is not limited to the above embodiments, and various modifications are possible. For example, the second
In Fig. 3, input terminal 3 and output terminal 4
Although the case where each of the terminals is divided into two has been described, the number of terminals is not limited as long as the length and cross-sectional shape of the connection line with the input/output pad can be made uniform. Further, in the above embodiment, the connection between the input/output pad and each terminal was made using aluminum wire, but the type of wire is not limited as long as the length and cross-sectional shape are uniform.

［発明の効果］ 以上詳述したようにこの発明によれば、入出力
電力間の電力損失を小さくする半導体装置を提供
することができる。[Effects of the Invention] As detailed above, according to the present invention, it is possible to provide a semiconductor device that reduces power loss between input and output power.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図はこの発明に係る半導体装置の斜視図、
第２図及び第３図はそれぞれこの発明の他の実施
例による斜視図、第４図は第３図装置の応用例を
示す等価回路図、第５図は従来の半導体装置の斜
視図、第６図は第５図の等価回路図である。 １……MOS FETペレツト、２……金属パツ
ケージ、３……入力電極、４……出力電極、５…
…セラミツク基板、６……入力パツド、７……出
力パツド、８……アルミニウム配線。 FIG. 1 is a perspective view of a semiconductor device according to the present invention;
2 and 3 are perspective views according to other embodiments of the present invention, FIG. 4 is an equivalent circuit diagram showing an example of application of the device shown in FIG. 3, FIG. 5 is a perspective view of a conventional semiconductor device, and FIG. FIG. 6 is an equivalent circuit diagram of FIG. 5. 1...MOS FET pellet, 2...metal package, 3...input electrode, 4...output electrode, 5...
...Ceramic board, 6...Input pad, 7...Output pad, 8...Aluminum wiring.

Claims (1)

【特許請求の範囲】 １ ソースが共通に接続された複数のMOS型電
界効果型トランジスタを備え、一方面は接地電極
面となり、他方面は複数個の入力電極及び出力電
極がそれぞれ配列する半導体ペレツトと、 基台部及びこの基台部と一体的に形成された凸
部からなり、上記凸部には上記半導体ペレツトが
接着される接地電極用の領域がある金属性の外囲
器と、 上記凸部の周縁部上に固着された絶縁性基板
と、 上記絶縁性基板上において上記半導体ペレツト
の長辺の長さと同等、もしくはそれ以上の領域で
この半導体ペレツトの長辺に対し互いに対向する
ように接着されそれぞれ端部まで同じ幅で伸びる
入力端子及び出力端子と、 上記入力端子及び出力端子それぞれと上記半導
体ペレツトの入力電極と出力電極それぞれとを接
続する各配線距離が均等な複数の配線と を具備したことを特徴とする半導体装置。 ２ 前記入力端子及び出力端子のうち少なくとも
入力端子がその幅方向で複数の部分に分割されて
いる請求項１記載の半導体装置。 ３ 前記分割された端子が互いに電気的に分離さ
れている請求項２記載の半導体装置。[Claims] 1. A semiconductor pellet comprising a plurality of MOS field effect transistors whose sources are commonly connected, one surface serving as a ground electrode surface, and the other surface having a plurality of input electrodes and output electrodes arranged respectively. and a metal envelope comprising a base portion and a convex portion integrally formed with the base portion, the convex portion having a region for a ground electrode to which the semiconductor pellet is bonded; an insulating substrate fixed on the peripheral edge of the convex portion, and an area on the insulating substrate that is equal to or longer than the long side of the semiconductor pellet and facing each other with respect to the long side of the semiconductor pellet. an input terminal and an output terminal each extending to the end with the same width; and a plurality of wirings having equal wiring distances connecting each of the input terminal and output terminal to each of the input electrode and output electrode of the semiconductor pellet. A semiconductor device characterized by comprising: 2. The semiconductor device according to claim 1, wherein at least one of the input terminal and the output terminal is divided into a plurality of parts in its width direction. 3. The semiconductor device according to claim 2, wherein the divided terminals are electrically isolated from each other.
JP63295413A 1988-11-22 1988-11-22 Semiconductor device Granted JPH02142154A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP63295413A JPH02142154A (en) 1988-11-22 1988-11-22 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP63295413A JPH02142154A (en) 1988-11-22 1988-11-22 Semiconductor device

Publications (2)

Publication Number Publication Date
JPH02142154A JPH02142154A (en) 1990-05-31
JPH0573342B2 true JPH0573342B2 (en) 1993-10-14

Family

ID=17820283

Family Applications (1)

Application Number Title Priority Date Filing Date
JP63295413A Granted JPH02142154A (en) 1988-11-22 1988-11-22 Semiconductor device

Country Status (1)

Country Link
JP (1) JPH02142154A (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6129143A (en) * 1984-07-20 1986-02-10 Hitachi Ltd Semiconductor device

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6129143A (en) * 1984-07-20 1986-02-10 Hitachi Ltd Semiconductor device

Also Published As

Publication number Publication date
JPH02142154A (en) 1990-05-31

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