JPH0572781B2 - - Google Patents

Info

Publication number
JPH0572781B2
JPH0572781B2 JP59097017A JP9701784A JPH0572781B2 JP H0572781 B2 JPH0572781 B2 JP H0572781B2 JP 59097017 A JP59097017 A JP 59097017A JP 9701784 A JP9701784 A JP 9701784A JP H0572781 B2 JPH0572781 B2 JP H0572781B2
Authority
JP
Japan
Prior art keywords
timing
circuit
pulse
signal
read
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP59097017A
Other languages
English (en)
Japanese (ja)
Other versions
JPS60240237A (ja
Inventor
Toshio Ootsu
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Electric Co Ltd filed Critical Nippon Electric Co Ltd
Priority to JP59097017A priority Critical patent/JPS60240237A/ja
Publication of JPS60240237A publication Critical patent/JPS60240237A/ja
Publication of JPH0572781B2 publication Critical patent/JPH0572781B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/06—Synchronising arrangements
    • H04J3/062—Synchronisation of signals having the same nominal but fluctuating bit rates, e.g. using buffers
    • H04J3/0626—Synchronisation of signals having the same nominal but fluctuating bit rates, e.g. using buffers plesiochronous multiplexing systems, e.g. plesiochronous digital hierarchy [PDH], jitter attenuators

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
JP59097017A 1984-05-15 1984-05-15 タイミング整合回路 Granted JPS60240237A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP59097017A JPS60240237A (ja) 1984-05-15 1984-05-15 タイミング整合回路

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59097017A JPS60240237A (ja) 1984-05-15 1984-05-15 タイミング整合回路

Publications (2)

Publication Number Publication Date
JPS60240237A JPS60240237A (ja) 1985-11-29
JPH0572781B2 true JPH0572781B2 (enrdf_load_stackoverflow) 1993-10-13

Family

ID=14180593

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59097017A Granted JPS60240237A (ja) 1984-05-15 1984-05-15 タイミング整合回路

Country Status (1)

Country Link
JP (1) JPS60240237A (enrdf_load_stackoverflow)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63224538A (ja) * 1987-03-14 1988-09-19 Fujitsu Ltd 同期制御回路

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5915582B2 (ja) * 1978-09-08 1984-04-10 沖電気工業株式会社 デイジタル位相同期方式
JPS56110147A (en) * 1980-02-05 1981-09-01 Nec Corp Buffer memory circuit

Also Published As

Publication number Publication date
JPS60240237A (ja) 1985-11-29

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