JPS60240237A - タイミング整合回路 - Google Patents

タイミング整合回路

Info

Publication number
JPS60240237A
JPS60240237A JP59097017A JP9701784A JPS60240237A JP S60240237 A JPS60240237 A JP S60240237A JP 59097017 A JP59097017 A JP 59097017A JP 9701784 A JP9701784 A JP 9701784A JP S60240237 A JPS60240237 A JP S60240237A
Authority
JP
Japan
Prior art keywords
pulse
read
timing
circuit
input signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP59097017A
Other languages
English (en)
Japanese (ja)
Other versions
JPH0572781B2 (enrdf_load_stackoverflow
Inventor
Toshio Otsu
大津 敏雄
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP59097017A priority Critical patent/JPS60240237A/ja
Publication of JPS60240237A publication Critical patent/JPS60240237A/ja
Publication of JPH0572781B2 publication Critical patent/JPH0572781B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04JMULTIPLEX COMMUNICATION
    • H04J3/00Time-division multiplex systems
    • H04J3/02Details
    • H04J3/06Synchronising arrangements
    • H04J3/062Synchronisation of signals having the same nominal but fluctuating bit rates, e.g. using buffers
    • H04J3/0626Synchronisation of signals having the same nominal but fluctuating bit rates, e.g. using buffers plesiochronous multiplexing systems, e.g. plesiochronous digital hierarchy [PDH], jitter attenuators

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
JP59097017A 1984-05-15 1984-05-15 タイミング整合回路 Granted JPS60240237A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP59097017A JPS60240237A (ja) 1984-05-15 1984-05-15 タイミング整合回路

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59097017A JPS60240237A (ja) 1984-05-15 1984-05-15 タイミング整合回路

Publications (2)

Publication Number Publication Date
JPS60240237A true JPS60240237A (ja) 1985-11-29
JPH0572781B2 JPH0572781B2 (enrdf_load_stackoverflow) 1993-10-13

Family

ID=14180593

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59097017A Granted JPS60240237A (ja) 1984-05-15 1984-05-15 タイミング整合回路

Country Status (1)

Country Link
JP (1) JPS60240237A (enrdf_load_stackoverflow)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63224538A (ja) * 1987-03-14 1988-09-19 Fujitsu Ltd 同期制御回路

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5538633A (en) * 1978-09-08 1980-03-18 Oki Electric Ind Co Ltd Digital phase synchronization system
JPS56110147A (en) * 1980-02-05 1981-09-01 Nec Corp Buffer memory circuit

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5538633A (en) * 1978-09-08 1980-03-18 Oki Electric Ind Co Ltd Digital phase synchronization system
JPS56110147A (en) * 1980-02-05 1981-09-01 Nec Corp Buffer memory circuit

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63224538A (ja) * 1987-03-14 1988-09-19 Fujitsu Ltd 同期制御回路

Also Published As

Publication number Publication date
JPH0572781B2 (enrdf_load_stackoverflow) 1993-10-13

Similar Documents

Publication Publication Date Title
KR940008295B1 (ko) 반도체메모리
US5068849A (en) Cyclic data transmission method
US4056851A (en) Elastic buffer for serial data
GB2210231A (en) Synchroniser for television audio and video signals
US4002846A (en) Multiplexed digital transmission system with means for channel insertion and extraction
US3984643A (en) Method and apparatus for establishing a plurality of simultaneous conferences in a PCM switching system
US4581732A (en) Time-space-time switching network using a closed-loop link
US4105869A (en) Time-division multiplex digital transmission system with intermediate stations adapted to transit insert and extract digital channels
US4147894A (en) Time division multiplex communication device comprising a switching matrix between C/E buffers and control circuits
US6349101B1 (en) Cell buffer circuit for an ATM cells to SDH-based data conversion system
US4792966A (en) Arrangement for synchronizing a byte clock derived from a data bit stream with a byte-oriented processing clock of a terminal equipment
US3881064A (en) Pulse code modulation time division switching system
JPS60240237A (ja) タイミング整合回路
US6529510B1 (en) ATM switching apparatus and method thereof
CA2021348C (en) Elastic store memory circuit
JP2703377B2 (ja) バッファ装置
US7248663B2 (en) Apparatus and method for transforming data transmission speed
JP3009745B2 (ja) 信号情報のチャンネル同期交換の方法
US5740212A (en) Delay circuit of PCM data
JPS5915582B2 (ja) デイジタル位相同期方式
KR100208371B1 (ko) 데이터전송 프레임의 포맷과 전송장치 및 그 송신제어방법
JP2770375B2 (ja) 伝送遅延位相補償回路
KR0131552B1 (ko) 데이타 클럭신호의 지연회로
US4975911A (en) Interface circuit for data transmission between a microprocessor system and a time-division-multiplexed system
JP2776133B2 (ja) 送端切替方式