JPS60240237A - タイミング整合回路 - Google Patents
タイミング整合回路Info
- Publication number
- JPS60240237A JPS60240237A JP59097017A JP9701784A JPS60240237A JP S60240237 A JPS60240237 A JP S60240237A JP 59097017 A JP59097017 A JP 59097017A JP 9701784 A JP9701784 A JP 9701784A JP S60240237 A JPS60240237 A JP S60240237A
- Authority
- JP
- Japan
- Prior art keywords
- pulse
- read
- timing
- circuit
- input signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000000034 method Methods 0.000 claims abstract description 3
- 238000010586 diagram Methods 0.000 description 6
- 230000007274 generation of a signal involved in cell-cell signaling Effects 0.000 description 6
- 238000006243 chemical reaction Methods 0.000 description 3
- 230000006870 function Effects 0.000 description 3
- HTXDPTMKBJXEOW-UHFFFAOYSA-N iridium(IV) oxide Inorganic materials O=[Ir]=O HTXDPTMKBJXEOW-UHFFFAOYSA-N 0.000 description 1
- 210000002784 stomach Anatomy 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04J—MULTIPLEX COMMUNICATION
- H04J3/00—Time-division multiplex systems
- H04J3/02—Details
- H04J3/06—Synchronising arrangements
- H04J3/062—Synchronisation of signals having the same nominal but fluctuating bit rates, e.g. using buffers
- H04J3/0626—Synchronisation of signals having the same nominal but fluctuating bit rates, e.g. using buffers plesiochronous multiplexing systems, e.g. plesiochronous digital hierarchy [PDH], jitter attenuators
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Synchronisation In Digital Transmission Systems (AREA)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59097017A JPS60240237A (ja) | 1984-05-15 | 1984-05-15 | タイミング整合回路 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59097017A JPS60240237A (ja) | 1984-05-15 | 1984-05-15 | タイミング整合回路 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS60240237A true JPS60240237A (ja) | 1985-11-29 |
| JPH0572781B2 JPH0572781B2 (enrdf_load_stackoverflow) | 1993-10-13 |
Family
ID=14180593
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP59097017A Granted JPS60240237A (ja) | 1984-05-15 | 1984-05-15 | タイミング整合回路 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS60240237A (enrdf_load_stackoverflow) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63224538A (ja) * | 1987-03-14 | 1988-09-19 | Fujitsu Ltd | 同期制御回路 |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5538633A (en) * | 1978-09-08 | 1980-03-18 | Oki Electric Ind Co Ltd | Digital phase synchronization system |
| JPS56110147A (en) * | 1980-02-05 | 1981-09-01 | Nec Corp | Buffer memory circuit |
-
1984
- 1984-05-15 JP JP59097017A patent/JPS60240237A/ja active Granted
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5538633A (en) * | 1978-09-08 | 1980-03-18 | Oki Electric Ind Co Ltd | Digital phase synchronization system |
| JPS56110147A (en) * | 1980-02-05 | 1981-09-01 | Nec Corp | Buffer memory circuit |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63224538A (ja) * | 1987-03-14 | 1988-09-19 | Fujitsu Ltd | 同期制御回路 |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0572781B2 (enrdf_load_stackoverflow) | 1993-10-13 |
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