JPH0572765B2 - - Google Patents

Description

[Detailed Description of the Invention] [Field of Application of the Invention] The present invention comprises a circuit for obtaining a delayed signal in digital signal processing using a random access memory, the number of stages is variable, and the number of stages can be specified externally. This is what I did.

[Prior art]

Delay circuits are often used in digital signal processing. For example, in image processing, by delaying the signal from a scanning input device by a time corresponding to one scanning line, information on vertically adjacent points can be extracted in parallel, which is useful for processing various two-dimensional patterns. It is used. Shift registers are generally used to delay digital information. At this time, it is desirable to be able to arbitrarily change the number of shift register stages in accordance with changes in input devices to be coupled or changes in processing clocks.
For this purpose, a commonly thought method would be to prepare a shift register with the maximum number of stages, select one of the stages, and extract and output the signal. However, this method has problems such as a large number of connections between the shift register and the general selection circuit, and an increase in the scale of the selection circuit. On the other hand, in another example shown in the Journal of the Institute of Electronics and Communication Engineers Vol. 62, No. 4, page 461, 1,
It has a shift register of length 2, 2 ² ,…, 2 ⁿ ,
The required number of stages is expressed in binary numbers, with each digit being “0” and “1”.
In response to this, the shift registers are made with shift registers that can be switched to any number of stages by controlling whether or not to bypass each shift register, and by connecting them. However, constructing these circuits using existing standard integrated circuits requires a large number of integrated circuit elements. Furthermore, when attempting to configure these circuits in one integrated circuit, it is advantageous to use a charge coupled device;
If a bipolar circuit is used to achieve even higher speeds, the shift register becomes a circuit that requires a relatively large area.

[Purpose of the invention]

An advantage of the present invention is to provide a delay circuit configuration that is suitable for integration and allows the number of shift stages to be set arbitrarily.

[Summary of the invention]

For this reason, the present invention uses a highly integrated random access memory, scans addresses at specified intervals, and repeats reading and writing to the memory, thereby achieving the same function as a shift register. I decided to have it. Additionally, a buffer was installed to align the input/output timing and maintain the output.

In other words, one aspect of the configuration of the present invention is that the input buffers 5-1 to 5-4 temporarily hold input data in synchronization with a clock, and the input data held in the input buffers are delayed by a predetermined time with respect to the clock. A random access memory 7 that writes input data to a designated address in synchronization with a delayed clock and then reads input data written to an address next to the designated address within at least one cycle of the clock.
-1 to 4) and output buffers 6-1 to 6-4 for temporarily holding the read data, and the output of the output buffer is input to the input buffer. a plurality of delay circuits connected in cascade, a delay means 9 for generating the delayed clock by delaying the clock for a predetermined time within one cycle of the clock, and periodically generating a count value; After the random access memory writes the input data to the specified address using the predetermined count value as the specified address, it increments the predetermined count value and sets the incremented count value as the next specified address. a counter 8 configured to do this; further comprising means 12 for setting the cycle of the counter value; a delay for inputting data read from the random access memory; delaying the read data; and inputting the read data to the output buffer. Adjustment means 33-1 to 33-3 are provided in at least one of the plurality of delay circuits, and means 31 is provided for controlling whether or not the delay adjustment means delays.

〔Example〕

An embodiment of the present invention will be described below with reference to FIG. The entire circuit 1 has the function of a shift register, 2 is an input signal, 3 is an output signal, and 4 is a clock. 5 and 6 are D-type flip-flops, which serve as input and output buffers, respectively. 7
is a static type random access memory that can be read and written, such as Hitachi's HM6147, and will be simply referred to as "memory" hereinafter. 8 is a counter giving a memory address. A pulse delay circuit 9 generates a clock 10 delayed from the input clock and supplies it as a memory write pulse and a clock to the counter 8. 11 is a carry output of the counter 8, which is used as its own initial value load signal. As a result, counter 8 registers 1
Starting from the output value of 2, the count is repeated until the maximum count is reached. Therefore, the period can be determined by the register 12.

The timing of the operation in the embodiment of FIG. 1 is shown in FIG. In FIG. 6, from top to bottom, clock 4, delayed clock 10, input buffer 5
The output 51 of the counter 8, the output 71 of the memory 7, and the output signal 3 of the output buffer 6 are shown.

First, since the input and output buffers 5 and 6 are driven by the clock 4, the input signal 2 is taken into the input buffer 5 and the output signal 3 is updated at the same time at the trailing edge _t0 of the clock 4. After the trailing edge t ₀ of clock 4, the output 51 of input buffer 5 becomes stable.
After t ₁ , delayed clock 10 is applied as a write pulse to memory 7 from t ₂ to t ₃ to write the information captured in input buffer 5 to memory 7 .
In this way, the input that is being written to the memory 7 is temporarily held in the input buffer 5, so it is guaranteed that it will remain unchanged. Further, the output 71 of the memory 7 changes from t ₂ to t ₅ described later, but since the trailing edge of the clock 4 is not applied to the output buffer 6 during this period, the output signal 3 is not affected.

An edge trigger type counter 8,
For example, Texas Instruments' integrated circuits
Using SN74163 or similar,
Since the counter output 81 changes after the delayed trailing edge _t3 of the clock 10 and after the access time _t4 - _t3 , it is possible to create a sequence in which the address advances after writing to the memory 7 is correctly completed. . Assuming that the address given to the memory 7 is determined at t ₄ (see point A in FIG. 6), the memory 7 is of a static type and the delayed clock 10, which is a write pulse, is not input. At _t5 , after the access time _t5 - _t4 , the data at the new address given from the output 81 of the counter 8 is read out (see point B in Figure 6), and the next trailing edge _t0 of the clock 4 is read out. By setting the period of clock 4 (interval from t ₀ to the next t ₀ ) so that it comes after t ₅ , the next data (output 71 of memory 7) to be supplied to output buffer 6 can be prepared correctly. .

As can be seen from the above explanation, the role of the input buffer 5 is to hold the value of the input signal at timing t ₀ until t ₃ when writing to the memory 7 ends. As a result, when using this circuit, the external circuit only needs to secure the signal value at the timing of _t0 , and the degree of freedom in the overall circuit design can be increased.

The role of the output buffer 6 is to keep the output signal 3 constant for one cycle. Without it, changes in the output 71 of the memory 7 shown in FIG. 6 would be directly output, so correct data would not be available. from t ₆ to next t ₀
In a high-speed system that attempts to shorten the period of clock 4 (the interval from one t ₀ to the next t ₀ ), the necessary logical operations must be completed in an external circuit during this time. is a factor that hinders speeding up.

In a specific application, for example, when the shift registers of this embodiment are connected in series, the output signal 3 of the output buffer 6 is directly connected to the input buffer 5, and no circuit is inserted between them, so the delay is almost 0, and the output signal is used only at timing _t0 and is not used in other time periods, so correct operation can be achieved even if the output buffer 6 is omitted. However, in general applications, it is used as an input to a circuit network, so
It is desirable that it does not change over a long period of time from t ₁ to t ₀ . Therefore, in order to widen the range of application, it is desirable to provide both an input buffer 5 and an output buffer 6.

Here, the relationship between the period of the counter 8 and the data delay cycle will be clarified using FIG.
This figure shows the data of the input signal 2, input buffer 5, memory 7, output buffer 6, and output signal 3 in the final state of each cycle, that is, in the state immediately before the input clock 4 is input to the counter 8.
This is shown together with the value of . As the counter 8, an addition type counter such as a combination of the above-mentioned SN74163 is used, and the memory address range is ^2k . In the figure, the storage cells of the memory are represented as being arranged in one dimension, and marks 16 and 17 indicate the positions of the storage cells at the start and final states of each cycle, respectively. Data is expressed in the form D ₁ . Here, i indicates the cycle number in which the data was received as an input signal. Data on parts not related to the explanation will be omitted. It is assumed that a value of 2 ^k -n is previously set in the register 12 from the outside. The cycles will be explained below in order. Assume that the counter value changes from 2 ^k -2 to 2 ^k -1 immediately before cycle number 0.
At this time, let the data that is the input signal be D ₀ .
At the next clock 4, the input buffer 5 takes in _D0 and writes the value into the memory 7 at address ^2k -1. In the counter 8, the carry signal C is input to the load terminal D via the line 11, so
The counter 8 takes in the value of the output 2 ^k -n of the register 12 by the carry signal C generated in this cycle. This cycle is cycle number 1. In the next cycle 2, data D ₁ is input to buffer 5.
At the same time, D ₁ is also stored at address 2 ^k −n in memory 7.
is written and counter 8 counts up to 2 ^k
-n becomes 2 ^k -(n-1). The cycle progresses and at the end of cycle number n, the counter 8 is counted again.
The content of reaches 2 ^k −1. In the next cycle, cycle number n+1, the value of this counter 8 is given as the read address of the memory 7, so the data _D0 written at address ^2k -1 of the memory 7 is read out and sent to the output buffer 6. It is output as a shift output signal 3. Since the data that was input at cycle number 0 is output at cycle number n+1, the number of delay stages is n+1.

That is, when it is desired to set the number of delay stages to D, it is preferable to set the period of the counter to D-1. In other words,
In order to set the period of the counter to D-1, the output of the register 12 must be set to 2 ^k -(D-1).
Furthermore, there are several methods to achieve this, as described below. First, there is a method of calculating 2 ^k -(D-1) externally and sending it to the register 12. This is equivalent to sending -(D-1) when expressing a negative number in two's complement. 2 ^k - (D-1) before or after register 12 by sending D or D-1
A circuit may be provided to obtain the . Furthermore, D-2 may be sent to obtain the one's complement. At this time, it is easy to perform logical negation of all bits. Which of these methods should be selected may be determined by considering the scale of the circuit and ease of use.

To explain the first method more specifically, input data (2 ^k −(D−
1))) while controlling the write strobe with the control signal 1
4 to write this data to register 12. In the present invention, by changing the data written to the register 12 in this way, the number of delay stages can be changed arbitrarily without changing the internal wiring. However, if it is incorporated into a specific circuit and the number of delay stages is not changed, writing to the register becomes rather troublesome, and it is preferable to omit the register 12 and provide a constant.

When this entire circuit 1 is a fixed circuit such as an integrated circuit, one of the above advantages may be lost depending on whether or not this register 12 is included, but it is possible to eliminate the function of the register by a specific control signal. In this way, both advantages can be retained in one integrated circuit. An example of such a register is shown in FIG.

In FIG. 3, 12-i indicates the configuration of the i-th bit of the register 12, which consists of a plurality of bits. Control signal 14 is commonly given to all bits. This register is the logical OR element 2
The data is set in an R-S type flip-flop consisting of 3 and 24 chips. When the register 12 is made to function as a register, a write pulse is applied as the control signal 14. At that time, the negative logic element 20, the AND elements 21, 22
As a result, a pulse is generated in either 21 or 22 depending on the value 0 or 1 of the input data 13-i, and data is set in the R-S type flip-flop constituted by OR elements 23 and 24. On the other hand, if it is desired to eliminate the register function of the register 12 and input the signal to the input data line 13 as it is to the counter 8, the control signal 14 may be fixed to the true value (1). In this way, the R-S type flip-flop consisting of 23 and 24 loses its latch function, and the data 13
The -i signal is always the output of the i-th bit 12-i of the register 12.

In addition, the i-th bit 12-
In the configuration of i, a selection signal 15 may be provided separately from the control signal 14 as shown in FIG. 4, and a D-type flip-flop 201 may be used instead of the R-S type flip-flop. In this circuit, the selection signal 15
If the true value (1) is set, the output of the D-type flip-flop 201 becomes the output of the i-th bit 12-i of the register 12, and if the selection signal 15 is set to the false value (0),
The signal applied to the input data line 13 remains as 1.
2-i output.

These allow the input of the input data line 13 for specifying the number of delay stages to be used both as an input to the register 12 and as a direct input to the counter 8, thereby reducing the number of interface signal lines in the overall circuit 1. , and is suitable for integrated circuits.

In the above example, one delay circuit was constructed from one circuit. In contrast, a configuration may be considered in which a certain number of input buffers 5, output buffers 6, and memories 7 are provided. FIG. 5 shows an example of this, including input buffers 5-1, 5-2,..., 5-4, output buffers 6-1, 6-2,..., 6-4, and memory 7-.
1, 7-2, . . . , 7-4, four each. This circuit can be used as multiple individual delay circuits, or as a delay circuit whose length exceeds the capacity of a single memory such as 7-1, by continuously connecting it through an external line as shown by the broken line in the figure. It can be used as required. For example, if each memory has 1000 bits, if four are provided, there will be four delay circuits with up to 1001 stages, two delay circuits with 4 to 2002 stages, and two delay circuits with 8 to 4004 stages. It is also possible to provide one delay circuit by external connection.

Now, it is easy to see that when m cascades are connected and the counter period is D, a delay of (D+1)·m stages can be created, but this is limited to an integer multiple of m. In order to create a delay including the number of stages that are not an integral multiple of the general 12m, the delay adjustment circuit 3
3-1, 33-2, 33-3 are provided, and these receive control signals 34-1, 34-3 from the delay adjustment control circuit 31.
4-2 and 34-3, it is possible to change the circuit to one stage delay or no delay circuit. A specific example of the delay adjustment circuit may be the same as that shown in FIG.
When the required number of delay stages is divided by m, the quotient is D and the remainder is R. As mentioned above, 2 ^k - (D-1) is the output of the register 12, and R delay adjustment circuits are arranged in one stage. , and the other delay adjustment circuits are non-delay circuits. As a result, a circuit with one stage of delay adjustment circuit has D+1 stages, and a circuit with no delay has D stages, and by cascading these, it is possible to realize a circuit with the required number of delay stages in total.

〔Effect of the invention〕

According to the present invention, a delay circuit with an arbitrary number of stages within the limit can be configured and can be used as a standard component in various signal processing circuits, so the circuit configuration is easy, and the circuit of the present invention can be used as an integrated circuit. By doing so, the circuit can be made smaller.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of the entire circuit according to the present invention.
Figure 2 is a diagram for explaining the number of delay stages in the circuit, Figure 3 is a logic diagram showing an example of register configuration, Figure 4 is a logic diagram showing another example of register configuration, and Figure 5 is a diagram showing multiple delay stages. Overall block diagram of the circuit including the circuit, No. 6
The figure is a time chart of the circuit of FIG. 4...Input clock, 5...Input buffer, 6
...Output buffer, 7...Random access memory, 8...Address counter, 12...Register.

Claims (1)

[Scope of Claims] 1. An input buffer that temporarily holds input data in synchronization with a clock, and an input buffer that transfers the input data held in the input buffer to a specified address in synchronization with a delayed clock that is obtained by delaying the clock by a predetermined time. a delay circuit comprising a random access memory for reading input data written to an address next to the specified address within at least one cycle of the clock after writing the input data to the specified address; and an output buffer for temporarily holding the read data. and the plurality of delay circuits are connected in cascade so that the output of the output buffer becomes the input of the input buffer, and the clock is delayed by a predetermined time within one period of the clock. comprising a delay means for generating the delay clock, which periodically generates a count value, sets the predetermined count value to the specified address, and after the random access memory writes the input data to the specified address, the random access memory writes the input data to the specified address; a counter configured to increment a count value and set the incremented count value as the next designated address; further comprising means for setting a cycle of the counter value; At least one of the plurality of delay circuits is provided with a delay adjustment means for inputting and reading out data to be delayed and inputted to the output buffer, and means for controlling whether or not to delay the data by the delay adjustment means. A variable length delay circuit characterized by comprising: