JPH0572298A - Rom code checking circuit - Google Patents

Abstract

PURPOSE:To enable the reading of a ROM code number data with a data bus. CONSTITUTION:This circuit has a first group of transistors 11 connected in series to a data bus 9 allowed to read externally and second groups 12 and 13 of transistors connected in series to the first group of transistors 11 separately. It is so arranged that output voltages of the second group 11 of transistors in which a threshold voltage is varied selectively beforehand in a production process can be read out as ROM code number data through the first group 11 of transistors which is ON or OFF controlled by a specified reading signal.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a ROM (Read Only Memory) code check circuit.

[0002]

2. Description of the Related Art A conventional ROM code check circuit is
As shown in FIG. 3, the pointed conduction needle 20 is erected on the needle stand pad 21, grounded from the GND terminal 25 of the IC chip 24, a predetermined voltage is applied to the power supply 16, and the power supply 16 is connected to the resistor 17 and the conduction. A voltage is applied between GND through the line 19, the needle stand pad 21, and the depletion type transistor 22 (or the enhancement type transistor 23). At this time, the output point 18 between the resistor 17 and the conducting line 19 is monitored. When the depletion type transistor 22 is included, the depletion type transistor 22 is
Since it is in the N state, a current flows from the power supply 16 to GND, and the voltage level of the output point 18 is determined by the ratio of the resistor 17 to the depletion type transistor 22, but since a resistor having a larger value than the depletion type transistor 23 is attached in advance. The GND level “0” is output to the output point 18.

Further, an enhancement type transistor 23
In this case, since the enhancement type transistor 23 is in the OFF state, the power supply and the GND are disconnected, and the power supply level “1” is output to the output point 18.

In this way, the ROM code is identified by changing the positions of the depletion type transistor 22 and the enhancement type transistor 23 for each ROM code.

In FIG. 3, a region 30 surrounded by a dotted line
Is shown as a circuit diagram by enlarging a region 30 ′ on the IC chip 24.

[0006]

SUMMARY OF THE INVENTION The conventional ROM described above.
In the code check configuration, the needle 2 is placed in the IC chip 24.
Since 0 is set, it takes time to familiarize yourself with the operation, and even if you are familiar with it, there is a drawback that the IC chip 24 may be scratched and broken due to an operation error of the needle 20.

Further, if the IC chip 24 is encapsulated with resin, there is a drawback that the resin must be removed.

There is also a drawback that it takes time to measure one IC chip 24 and it is impossible to check a large number of IC chips.

The object of the present invention is to solve the above-mentioned drawbacks and
It is an object of the present invention to provide a ROM code check circuit capable of performing an electrical measurement test promptly without fear of damaging the C chip.

[0010]

A ROM code check circuit according to the present invention has a structure in which a first transistor group connected in series to an externally readable data bus, and a series connected to each transistor of the first transistor group. A second transistor group connected to the second transistor group and selectively changing the threshold voltage via the first transistor group which is on / off controlled by a predetermined read signal. It is characterized in that the output voltage of the transistor is read as ROM code number data.

[0011]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a block diagram of a main part of a ROM code checking circuit incorporated in a microcomputer according to an embodiment of the present invention.

FIG. 2 is a timing chart showing the waveforms of the respective parts of FIG.

In FIG. 2, the waveform of the ROM code read command signal 3 output from the command generation circuit 5 shown in FIG. 1, the waveform of the timing signal 1 output from the timing generation circuit 4, the waveform of the timing signal 2 and the data bus. 9 is a waveform.

In FIG. 1, the timing signal 1 and the timing signal 2 output from the timing generation circuit 4 are
Reading of "1" is repeatedly output every one instruction cycle 14 (FIG. 2) of the microcomputer. When "1" is output from the ROM code read command signal 3 from the command generation circuit 5, the output of the inverter 8 becomes "0" and the pull-up transistor 10 is turned on. When the pull-up transistor 10 is turned on, the data bus 9 becomes the power supply level.

When the ROM code read command signal 3 is "1" and the timing signal 1 is "1", the output of the AND circuit 6 is "1".

When the ROM code read command signal 3 and the timing signal 2 are "1", the AND circuit 7 also outputs "1".

When the outputs of the AND circuits 6 and 7 become "1", the enhancement type transistor 11 is turned on.
To do. When the enhancement-type transistor 11 is turned on, the transistor connected to the enhancement-type transistor 11 becomes a depletion-type transistor 13.
In the case of (hereinafter, depletion Tr), since the depletion Tr is always in the ON state, during the read period 15 (FIG. 2), the pull-up transistor 10, the enhancement type transistor 11, and the depletion Tr
Current flows from the power supply to GND, DA at the midpoint
The output level of the TA bus 9 is the pull-up transistor 1
It depends on the ON resistance ratio of the 0-to-enhancement type transistor 11 and the depletion transistor Tr.

However, the ON resistance ratio of the pull-up transistor 10, the enhancement type transistor 11, and the depletion transistor is previously set to the pull-up transistor 1.
The ON resistance of 0 is made larger, and the output level of the DATA bus 9 is “0”. Further, when the transistor connected to the enhancement type transistor 11 is the enhancement type transistor 12 (hereinafter referred to as a normal Tr), the normal Tr is in the OFF state. Therefore, during the read period 15, the enhancement type transistor 11 is turned on. Current does not flow from the power supply to GND, and the pull-up transistor 10 is connected to the DATA bus 9.
"1" is output through the.

By externally monitoring the DATA bus 9 at the timing, the DAT of the ROM code number
It becomes possible to read A. Moreover, by changing the positions of the depletion Tr and the normal Tr for each ROM code, the DA bus for each ROM code is changed from the DATA bus 9.
Since TA is output, it becomes possible to sort by ROM code. By using a plurality of the elements, more ROM code can be output.

[0020]

As described above, according to the present invention, the ROM
ROM by making it easy to check the code from outside
It is possible to sort by code, enter various types of ROM codes even on a single wafer, enable low-volume, high-mix production, reduce overproduction, and reduce chip cost. There is.

[Brief description of drawings]

FIG. 1 is a block diagram showing a ROM code check circuit according to an embodiment of the present invention.

FIG. 2 is a timing chart showing an output signal waveform of an instruction generation circuit, a waveform of an output signal of a timing generation circuit, a waveform of a DATA bus, and a waveform of a precharge signal in the circuit of FIG.

FIG. 3 is a block diagram showing a conventional ROM code check circuit.

[Explanation of symbols]

 1 Timing signal 2 Timing signal 3 ROM code read command signal 4 Timing generation circuit 5 Command generation circuit 6,7 AND circuit 8 Inverter 9 DATA bus 10 Pull-up transistor 11, 12, 23 Enhancement type transistor 13, 22 Depletion type transistor 14 1 Command cycle 15 Read-out period 16 Power supply 17 Resistance 18 Output point 19 Conduction line 20 Pointed conduction needle 21 Needle stand pad 24 IC chip 25 GND terminal

Claims (1)

[Claims] 1. A predetermined read operation, comprising: a first transistor group connected in series to an externally readable data bus; and a second transistor group connected in series to each transistor of the first transistor group. The output voltage of each transistor of the second transistor group whose threshold voltage is selectively changed is read out as ROM code number data through the first transistor group which is on / off controlled by a signal. A ROM code check circuit characterized in that