JPH057191A - Frame synchronization system for digital multiplexer optical carrier device - Google Patents

Abstract

PURPOSE:To eliminate a delay at out of synchronism by giving the frame synchronization information of a high speed data to a frame synchronization detection circuit for a low speed data. CONSTITUTION:A high speed data frame synchronization detection circuit and a speed conversion circuit 10 use high speed data frame synchronization information (e) to stop the function of a forward protection circuit of a frame synchronization protection circuit 50. Moreover, the synchronization information (e) controls simultaneously a low data timing generator 30. That is, while the high speed data is in hunting for frame synchronization restoration, the low speed data timing generator 30 is stopped. The stop location is its own frame pulse location. Thus, when out of frame synchronization takes place in the high speed data, since frame out of synchronism takes place on the low speed side, no delay is caused. Furthermore, the hunting of the low speed data is started immediately after the restoration of the synchronization of the high speed data and the synchronization recovery depends only on the location of a frame pulse of the input low speed data.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a frame synchronization system in a digital multiplex optical carrier having a digital signal multiplexing function and a speed conversion function into an optical transmission line code.

[0002]

2. Description of the Related Art A conventional digital multiplex optical carrier having a speed conversion circuit for multiplexing a PCM signal, multiplexing auxiliary data on the multiplexed signal, and converting the optical signal into an optical transmission line code is used. After that, the pattern detection immediate shift method or the like is used to first detect the synchronization of high-speed data, and after the frame synchronization of the high-speed data is restored, the synchronization data is passed to the demultiplexing unit, so that the demultiplexing unit synchronizes the frame of the low-speed data. Then, after this is completed, the frame synchronization of the entire device is restored.

[0003]

In the frame synchronization method of the entire apparatus in the conventional digital multiplex optical carrier, the frame synchronization detection is performed separately on the high speed side and the low speed side. Therefore, in the process of losing frame synchronization,
First, the frame synchronization loss occurs on the high speed side, and thereafter, the frame synchronization loss detection is performed on the low speed side, and during this period, the frame synchronization loss time of the entire apparatus is set. However, the out-of-frame detection circuit on the low-speed side is equipped with a front protection circuit to prevent mis-synchronization. Delay occurs. Therefore, when the frame synchronization is lost on the high-speed data side, the front protection circuit of the frame detection circuit on the low-speed data is meaningless.

Further, in the frame synchronization recovery process,
Similar to the above, first, the synchronization recovery is performed on the high speed side, and after the frame synchronization recovery is established on the high speed side, the data is sent to the low speed side and the hunting is started on the low speed side. At this time, where in the low speed data the hunting starts,
There is a problem in that the synchronization recovery time cannot be detected quantitatively because it differs from time to time.

An object of the present invention is to eliminate the delay at the time of loss of synchronization, and when returning to frame synchronization, in the hunting process for recovering synchronization with low-speed data, hunting is started immediately after recovery of frame synchronization with high-speed data. It is an object of the present invention to provide a frame synchronization system for a digital multiplex optical carrier, which has improved synchronization recovery characteristics.

[0006]

According to the frame synchronization system of a digital multiplex optical carrier of the present invention, a high speed data frame synchronization detection circuit and a speed conversion circuit for performing speed conversion after synchronous detection of high speed data, and an output from this circuit. A low-speed data frame detection circuit for detecting a frame from low-speed data and a demultiplexing circuit, and a low-speed data timing generator controlled by high-speed data frame synchronization information output from the high-speed data frame synchronization detection circuit and the speed conversion circuit, And a frame synchronization protection circuit controlled by the high-speed data frame synchronization information.

Further, according to the present invention, the low-speed data timing generator stops the operation of the high-speed data while the high-speed data is hunting to recover the frame synchronization according to the high-speed data frame synchronization information. The protection circuit, by the high-speed data frame synchronization information,
The function of the front protection circuit is stopped.

[0008]

Embodiments of the present invention will now be described with reference to the drawings.

FIG. 1 shows an embodiment of the present invention. The high speed data a and the high speed clock b are subjected to speed conversion after synchronization detection by the high speed data frame synchronization detection circuit and speed conversion circuit 10, and low speed data c and low speed clock d are output. Low speed data frame detection circuit and demultiplexing circuit 2
At 0, the frame is detected from the low speed data, and the low speed separation data i is output. The frame pulse comparison circuit
The frame detected by the circuit 20 is compared with the frame pulse generated by the low-speed data timing generator 30 to determine whether the input data is synchronized with the own timing. The frame synchronization protection circuit 50 protects against false synchronization and false hunting, and outputs low-speed data frame synchronization information f. The clock control circuit 60 inputs the low speed clock d and the hunting control information g from the frame synchronization protection circuit 50 and outputs the clock control information h to the low speed data timing generator 30.

In the present invention, the synchronization information c from the high speed data frame synchronization detection circuit and the speed conversion circuit 10 is connected to the low speed data timing generator 30 and the frame synchronization protection circuit 50.

Now, in the high speed data frame synchronization detection circuit and speed conversion circuit 10, when the high speed data is out of frame synchronization, the function of the forward protection circuit of the frame synchronization protection circuit 50 is stopped by the high speed data frame synchronization information e. Let That is, when the frame synchronization is lost due to the high speed data, the frame synchronization is always lost even at the low speed side. Therefore, there is no delay in the out-of-synchronization detection time as in the conventional case.

The low speed data timing generator 30 is controlled at the same time by the high speed data frame synchronization information e. That is, the low speed data timing generator 30 is stopped while the high speed data is hunting to recover the frame synchronization. The stop position is the frame pulse position of its own. For this reason, hunting with low-speed data is started immediately after synchronization recovery of high-speed data, and synchronization recovery depends only on the frame pulse position of input low-speed data.

[0013]

As described above, according to the present invention, by providing the frame synchronization information of high speed data to the frame synchronization detection circuit of low speed data, the delay at the time of loss of synchronization can be eliminated and the low speed data can be recovered at the time of frame synchronization recovery. By stopping the timing of the low-speed data timing generator at the frame pulse position in the hunting process for the synchronization recovery, the hunting start is started immediately after the high-speed data frame synchronization recovery and the synchronization recovery characteristics are improved.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention.

[Explanation of symbols]

10 High-speed data frame synchronization circuit and speed conversion circuit 20 Low-speed data frame detection circuit and demultiplexing circuit 30 low speed data timing generator 40 frame pulse comparison circuit 50 frame sync protection circuit 60 clock control circuit a high speed data b High-speed clock c Low speed data d low speed clock e High-speed data frame synchronization information f Low speed data frame synchronization information g Hunting control information h Clock control information i Slow separation data

Claims (2)

[Claims] 1. A high-speed data frame synchronization detection circuit and a speed conversion circuit for performing speed conversion after synchronous detection of high-speed data,
Low-speed data frame detection circuit and demultiplexing circuit for detecting a frame from low-speed data output from this circuit, and low-speed data controlled by high-speed data frame synchronization information output from the high-speed data frame synchronization detection circuit and speed conversion circuit. A frame synchronization system for a digital multiplex optical carrier, comprising a timing generator and a frame synchronization protection circuit controlled by the high speed data frame synchronization information. 2. The low speed data timing generator stops its operation according to the high speed data frame synchronization information while the high speed data is hunting to recover the frame synchronization. 2. The frame synchronization system for a data multiplexing optical carrier device according to claim 1, wherein the function of the front protection circuit is stopped by the high speed data frame synchronization information.