JPS62219841A - Dummy synchronizing preventing circuit - Google Patents

Abstract

PURPOSE:To prevent a dummy synchronizing pulling condition and to process receiving data in a correct synchronizing pulling condition by providing two systems of synchronizing circuits having a frame detecting part and an error detecting part, and deciding that the synchronizing circuit, in which the error rate detected by respective error detecting parts is smaller, is the correct synchronizing pulling condition. CONSTITUTION:In a frame detecting circuit 11a of one side synchronizing circuit 10a, the pattern of a part of DATA is detected as a frame pattern from the frame of #1-#$4, when the number of the backward protecting step is three, after the frame of #3, a synchronizing pulling condition is obtained, a separating circuit 13a separates, outputs the pattern detected as the frame pattern by the separating pulse of a synchronizing protecting circuit 12a and the dummy synchronizing pulling condition is obtained. In other synchronizing circuit 10b, the detection of the frame pattern is not executed from the frame of #1 and #2, a frame pattern F is detected from the frame of #3-#5, and then, the synchronizing pulling condition is obtained. At the synchronizing circuit 10b side, the frame pattern F can be separated from a receiving signal, and therefore, the error rate by an error detecting circuit 14b comes to be small, the output of a flip-flop 17 comes to be '1', and a selector 18 selects and outputs the data from the synchronizing circuit 10b.

Description

[Detailed Description of the Invention] [Summary] Two systems are provided with synchronization circuits that perform frame synchronization and process received data, and the system with the smaller error rate is set as the system in the correct synchronization pull-in state, and the received data of that system is selectively output. This method prevents pseudo-image synchronization pull-in and processes received data with fewer errors.

[Industrial application field]

The present invention relates to a pseudo-synchronization prevention circuit for preventing pseudo-synchronization caused by data having the same pattern as a frame pattern.

In data communication systems, a frame pattern is added to the beginning of data of a predetermined length and transmitted, and the receiving side detects the frame pattern, performs frame synchronization, and processes the data with the frame pattern removed. It is something. When detecting a frame pattern, the data may contain the same pattern as the frame pattern.
When that pattern is detected as a frame pattern,
A pseudo-synchronous pull-in state may occur. In such a pseudo-synchronous pull-in state, there are many data errors, so
It is necessary to prevent this pseudo-synchronization.

[Conventional technology]

For example, as shown in FIG. 4, a conventional synchronization circuit includes a frame detection circuit 21, a synchronization protection circuit 22, and a separation circuit 2.
3 and an error detection circuit 24, the frame detection circuit 21 detects a frame pattern and applies the detection signal to the synchronization protection circuit 22. The frame format is
For example, as shown in FIG. 5, a frame pattern F is added to the beginning of data DATA, and this frame pattern is selected as, for example, "01111110".

Further, the synchronization protection circuit 22 performs backward protection to determine that the synchronization pull-in state is established when n detection signals from the frame detection circuit 21 are obtained consecutively or within a predetermined period of time, and also performs backward protection to determine that the synchronization pull-in state is present. m pieces consecutively or within a predetermined time
If no detection signal is obtained, it is determined that the synchronization is out of synchronization, and in the synchronization pull-in state, the separation circuit 2
Adding a separation pulse to 3, frame pattern F and Q5
'DATA is separated, and an error in the separated data DATA is detected by the error detection circuit 24. If it is determined that the synchronization is out of synchronization, the frame pattern detection timing in the frame detection circuit 21 is shifted and controlled until n frame pattern detection signals are obtained consecutively or within a predetermined time. , a synchronous pull-in operation is performed.

[Problem that the invention seeks to solve]

Data DATA in the frame format shown in Figure 5
There may be a case where the same pattern as frame pattern F is included, and if this pattern is detected as a frame pattern and this pattern happens to be repeated in a frame period, a synchronization pull-in state occurs. In this way, a synchronization pull-in state caused by detection of a pattern other than frame pattern F is referred to as a pseudo-synchronization pull-in state.

In such a pseudo-synchronization pull-in state, it will not be determined that synchronization has occurred unless m frame detection signals are obtained consecutively or within a predetermined period of time.
The pseudo-synchronous pull-in state may continue. That is, once synchronization is established, synchronization does not occur and the pseudo synchronization pull-in state continues until m frame detection signals corresponding to the number of forward protection stages are no longer obtained. In this pseudo-synchronization pull-in state, part of the data DATA will be separated as frame pattern F in the separation circuit 23, resulting in erroneous processing of the received data.

It is an object of the present invention to prevent such a pseudo synchronous pull-in state and to process received data in a correct synchronous pull-in state.

[Failure to solve the problem]

The false image synchronization prevention circuit of the present invention includes two systems of synchronization circuits, and processes received data as the system with the smaller error rate is in the correct synchronization pull-in state, and will be explained with reference to FIG. . Frame detection unit 1 that detects frame patterns at different timings and performs synchronization pull-in
A, 1b, and two systems of synchronous circuits 3a, 3b each having error detecting sections 2a, 2b for detecting errors in received data are provided, synchronization pull-in operation is performed in each system, and the frame pattern is removed by the synchronization pull-in. A selection circuit 4 is provided which detects the error rate of data by error detection units 2a and 2b, and selects and outputs the received data by selecting the system with the lower error rate as the system in the correct synchronization pull-in state.

[Effect]

When the synchronization circuit of one system enters a pseudo-synchronization pull-in state, the other system detects a pattern at a timing different from the detection timing of the frame pattern that caused this pseudo-synchronization pull-in. , the synchronous pull-in operation is performed at a timing different from the timing of the pseudo-synchronous pull-in state, and a correct synchronous pull-in state can be achieved. Furthermore, the error rate detected by the error detection units 2a and 2b of each system is sufficiently smaller in the system in the correct synchronization pull-in state compared to the system in the pseudo-synchronization pull-in state, and the system with the smaller error rate By selectively outputting the data in the selection circuit 4, it is possible to selectively output the data of the system in the correct synchronous pull-in state.

〔Example〕

Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 2 is a block diagram of an embodiment of the present invention, 10a,
10b is a synchronization circuit, lla and l1b are frame detection circuits, 12a and 12b are synchronization protection circuits, I3a and 13b are separation circuits, 14a and 14b are error detection circuits, 15 is a gate circuit, 16 is a selection circuit, and 17 is a flip-flop ,1
8 is a selector. Frame detection circuit 11a, l1b
, synchronization protection circuits 12a, 12b, and separation circuits 13a, 13
The frame detectors 1a and 1b in FIG. 1 are configured by the frame detectors 1a and 1b shown in FIG. 1, and the error detectors 2a and 1b in FIG.

The frame detection circuits 11a and 11b detect a frame pattern from a received signal, and shift control of the detection timing is performed until this frame pattern is detected. The frame pattern detection signal is applied to the synchronization protection circuits 12a and 12b, and during synchronization pull-in operation, synchronization is achieved when n detection signals are obtained consecutively or within a predetermined time, corresponding to the number of backward protection stages. It is determined that it is in the retracted state, and a separation pulse is applied to the separation circuits 13a and 13b.

In addition, in the synchronous retracted state, depending on the number of forward protection stages,
If m detection signals are not obtained consecutively or m detection signals are not obtained within a predetermined period of time, it is determined that synchronization has been lost, and a synchronization pull-in operation is started by shifting the frame pattern detection timing in frame detection circuits 11a and 11b. be done.

A detection signal obtained by detecting a frame pattern by the frame detection circuit 11a of one of the synchronization circuits 10a is sent to the synchronization protection circuit 12.
a and is also added to the gate circuit 15 of the other synchronous circuit 10b as an inhibition signal. Therefore, the detection signal of the frame detection circuit 11b of the other synchronous circuit 10b is invalidated at the same timing as the frame pattern detection timing of the frame detection circuit 11a of the one synchronous circuit 10a. In other words, one synchronous circuit 10a and the other synchronous circuit 10b detect frame patterns at different timings, and even if one synchronous circuit 10a enters a pseudo-synchronization pull-in state, the other synchronous circuit fob does not. It becomes possible to detect frame patterns at different correct timings and establish a synchronization pull-in state.

The synchronization protection circuits 12a and 12b are for determining whether a synchronization pull-in state has occurred and whether or not synchronization has occurred, and perform backward protection and forward protection as described above. In the synchronization pull-in state, a separation pulse is applied to the separation circuits 13a and 13b, whereby the separation circuits 13a and 13b separate the frame pattern F, and only the data DATA is output.
TA is applied to the error detection circuits 14a and 14b as well as to the selector 18 of the selection circuit 16.

The error detection circuits 14a and 14b detect the error rate, and output a set or reset signal to the flip-flop 17 of the selection circuit 16 when the error rate is higher than a predetermined error rate. is applied to the set terminal S of the flip-flop 17 and set, and when the Q terminal output voltage becomes 1'', the selector 18
selectively outputs data from the synchronous circuit 10a. Further, when the signal from the error detection circuit 14b is applied to the reset terminal R of the flip-flop 17 and the Q terminal output becomes "O", the selector 18 selectively outputs the data from the synchronization circuit 10b. That is, the error detection circuit 14a
, 14b is assumed to be in the correct synchronization pull-in state, and data from that synchronization circuit is selectively output. Therefore, processing of received data with many errors due to the pseudo synchronization pull-in state can be prevented.

FIG. 3 is an explanatory diagram of the operation of the embodiment of the present invention, and the received signal has a frame structure consisting of a frame pattern F and data DATA as shown in FIG. In the detection DfW11a, #1
When a partial pattern of data DATA is detected as a frame pattern over four frames of ~#4 and the number of backward protection stages is set to 3, one of the synchronization circuits 10a is in the synchronization pull-in state after frame #3, and the synchronization protection circuit 12a is The separation circuit 13a separates and outputs the pattern detected as a frame pattern from the received signal by the separation pulse from the received signal. Such a synchronous pull-in state is a pseudo-synchronous pull-in state.

On the other hand, in the frame detection circuit 11b of the other synchronization circuit 10b, #1. No frame pattern could be detected from frame #2, but #3. #4. #5
If frame pattern F is detected from the frame of , the synchronization circuit 10b enters the synchronization pull-in state.

Note that, like the frame detection circuit 11a of the synchronous circuit 10a, even if the frame detection circuit 11b of the synchronous circuit 10b detects a partial pattern of the data DATA as a frame pattern, the detection signal is processed by the gate circuit 15 for a period of T. Since the signal is blocked and not added to the synchronization protection circuit 12b, the synchronization circuits 10a and 10b detect patterns with different timings as frame patterns, and perform a synchronization pull-in operation.

Assuming that both the synchronization circuits 10a and 10b are in the synchronization pull-in state, the separation circuits 13a and 13b output data whose frame patterns are separated from the received signals using separation pulses at different timings, and the data is output to the error detection circuits 14a and 14b. error detection is performed. In that case, the data on the side of the synchronization circuit 10a that detects a part of the data DATA as a frame pattern is
Since part of A is separated as a frame pattern, the error rate detected by the error detection circuit 14a becomes very large.

On the other hand, on the side of the synchronization circuit 10b, since the frame pattern F can be separated from the received signal, the error detection circuit 10b can separate the frame pattern F from the received signal.
The error rate detected by 4b becomes smaller, so the flip-flop 17 is set and the Q terminal output becomes "1". Thereby, the selector 18 selectively outputs the data from the synchronous circuit 10b.

It is possible to start the synchronous circuits 10a and 10b at the same time during the synchronous pull-in operation, but for example, when one synchronous circuit 10a starts the synchronous pull-in operation and enters the synchronous pull-in state, the other synchronous circuit It is also possible to perform a synchronization pull-in operation by applying an operation start signal to the frame detection circuit 11b of 10b. In this case, when one of the synchronous circuits 10a detects the correct frame pattern F and enters the synchronous pull-in state, the other synchronous circuit 10b may enter a state in which it always continues the synchronous pull-in operation.

〔Effect of the invention〕

As explained above, the present invention includes a frame detection unit 1a,
1b and error detection units 2a and 2b.
a and 3b are provided, and the synchronous circuit with the smaller error rate detected by the error detection units 2a and 2b of the two systems of synchronous circuits 3a and 3b is determined to be in the correct synchronization pull-in state,
The data from the synchronous circuit is selectively outputted by the selection circuit 4, and even if one synchronous circuit enters a pseudo synchronous pull-in state, the other synchronous circuit detects a frame pattern at a different timing and performs a synchronous pull-in operation. Therefore, it is possible to detect the correct frame pattern and enter the synchronization pull-in state. Also, when in the pseudo-synchronous pull-in state, the error rate increases, but by selectively outputting the data of the synchronous circuit with the smaller error rate, correct synchronization can be achieved without selecting the data of the synchronous circuit in the pseudo-synchronous pull-in state. Since the data of the synchronous circuit in the retracted state can be selectively output, it is possible to process data with fewer errors.

[Brief explanation of drawings]

Fig. 1 is a block diagram of the principle of the present invention, Fig. 2 is a block diagram of an embodiment of the invention, Fig. 3 is an explanatory diagram of the operation of the embodiment of the invention, and Fig. 4 is a block diagram of a conventional frame synchronization circuit. , FIG. 5 is an explanatory diagram of the frame format. la and 1b are frame detection units, 2a and 2b are error detection units, 3a and 3b are synchronization circuits, 4 is a selection circuit, 10a and 1
0b is a synchronization circuit, 118.11b is a frame detection circuit,
12a and 12b are synchronization protection circuits, 13a and 13b are separation circuits, 14a and 14b are error detection circuits, 15 is a gate circuit, 16 is a selection circuit, 1-7 are flip-flops, 1
8 is a selector.

Claims (1)

[Claims] Frame detection units (1a, 1b) that detect frame patterns at different timings and perform synchronization pull-in;
Error detection unit (2a, 2
b) Two systems of synchronous circuits (3a, 3b) are provided, and the system with the smaller error rate detected by the error detection section (2a, 2b) of the two systems of synchronous circuits (3a, 3b) is provided. A pseudo synchronization prevention circuit comprising a selection circuit (4) for selectively outputting received data as a system in a correct synchronization pull-in state.