JPH056938U - Error correction code generation circuit - Google Patents

Abstract

(57) [Summary] [Purpose] High-speed serial output of error-correcting codes without erroneous generation. [Configuration] D for data sampling between data input and output
Type flip-flop circuits and flip-flop circuits for data memory are alternately connected by a circuit, and an EXOR circuit is connected to a predetermined portion of this circuit.
The input side of each EXOR circuit is connected to the output side of an AND circuit, and the clock signal output line is further connected to the clock signal input terminal of each D-type flip-flop circuit via a NOT circuit. [Effect] The error correction code can be serially output at high speed only by serially inputting the calling signal, and the data error due to the operation delay time of the IC is eliminated.

Description

[Detailed description of the device]

[0001]

[Industrial applications]

 When an error occurs due to the influence of noise, etc. when a digital transmission signal composed of a binary bit group passes through a communication medium such as a channel, that is, when the bit has a value opposite to the original value. , A circuit for generating an error correction code for correcting to a correct bit.

[0002]

[Prior Art]

Configuration of the digital transmission signal is prescribed by the Radio Law, bit synchronization signal, as shown in Table 1, the frame sync signal is composed of a call signal, the call signal is composed of 63 bits of a ₆₂ ~a ₀ It Of the 63 bits, 51 bits are calling name until a ₆₂ ~a _12, 12 bits from a ₁₁ ~a ₀ is an error correcting code. Bits a ₆₂ to a ₁₂ are calculated by the generator polynomial shown in Formula 1 and the formula shown in Formula 2, and are represented by the coefficients of terms from the 62nd order to the 12th order of the polynomial on the finite field of order 2. .

[Equation 1]

[Equation 2] However, b ₄₇ ~b ₀ number of each digit of the (a ₅₉ ~a ₁₂₎ until the call out the name represented by the decimal number 12 digits from 1 digit when converted to binary by Table 2 to 48 digits and then, b ₅₀ ~b until ₄₈ (a ₆₀ ~a ₆₂₎ is legal to zero. For example, when calling name is _{"123456789012", b 47 ~b 0 (a 59} ~a 12) is obtained by converting the binary number by Table 2, _{also, b 50 ~b 48 (a 60} ~a _{Since 62} ) is "0" as described above, it has the bit configuration shown in Table 3. The error-correcting codes a _{11 to} a ₀ were obtained by programming the multiplication / division polynomial obtained by the equation (3) with a computer (Table 4), and the data was written in the ROM.

[0003]

[Problems to be solved by the device]

 Since the calling name is different for each radio, it is necessary to store the corresponding error correction code, so it takes a lot of time to generate the error correction code by the conventional software means. However, this has been one of the causes of increasing the manufacturing cost of the wireless device.

[0004]

[Means for Solving the Problems]

 The present invention was developed to solve the above-mentioned conventional problems, and provides a circuit for generating an error correction code at high speed without error generation. That is, the configuration is a circuit for inputting call name data composed of a binary number in digital wireless communication to generate an error correction code, and a data input terminal for inputting the data and an error correction code. Is connected to the data output terminal for outputting a data sampling D-type flip-flop circuit and a data memory D-type flip-flop circuit alternately, and a predetermined EXOR circuit is connected to the predetermined location. The output side of the AND circuit connected to the external input terminal is connected to the input / output of the D type flip-flop circuit for data sampling and the D type flip-flop circuit for data memory, and the output side of the AND circuit is connected to the input of each EXOR circuit. The clock signal output line through the NOT circuit to the clock signal input terminal of each D-type flip-flop circuit. There is something.

[0005]

[Action]

 As shown in FIG. 4, the sampling D-type flip-flop circuit (hereinafter abbreviated as sampling DFF) S0 inputs the first bit of the call name from the data input terminal DATA IN with a half cycle delay from the clock signal. Next, D1 of the memory DFF reads the data output from S0 with a half cycle delay from that. Thus, S0 successively inputs data in synchronism with the clock signal. Below, this data is output from DATA OUT via S1, D2 ... It is returned to EX0 to EX10 via. Then, when the operation of the number of steps corresponding to the call name is completed, that is, when the remaining 12 bits corresponding to the error correction code are reached, 12 bits corresponding to the error correction code are stored in D1 to D12. become. Here, the signal output from the EXC terminal can be changed from the "H" level to the "L" level through an AND circuit, and the correct error correction code is serially output from DATA OUT.

[0006]

【Example】

FIG. 1 shows an embodiment of an error correction code generation circuit according to the present invention, FIG. 4 shows its operation flow chart, and FIG. 5 shows a timing chart. Hereinafter, the present invention will be described in detail with reference to these drawings. The error correction code generation circuit according to the present embodiment has a 12-bit error correction code to be obtained. As shown in FIG. 1, 12 data memory DFFs (hereinafter referred to as memory DFFs), D1 to D1. D12 and 13 data sampling DFFs (hereinafter abbreviated as sampling DFFs) S0 to S12, six EXOR circuits EX0, EX3 to EX5, EX8, EX10, one AND circuit, and the like. A clock signal output line is connected to the clock signal input terminal CK of the DFF from the clock signal output terminal CLK via a NOT circuit. As the D input of S0 is connected to the data input terminal DATA IN, the sampling DFFs and the memory DFFs are alternately connected in series. EX0 is between the Q output of S0 and D input of D1, EX3 is between S3 and D4, EX4 is between S4 and D5, EX5 is between S5 and D6, and between S8 and D9. Is connected to EX8, and EX10 is connected between S10 and D11. That is, EX0, EX3, EX4, EX5, EX8, and EX10 are connected to positions corresponding to X ⁰ , X ³ , X ⁴ , X ⁵ , X ⁸ , and X ¹⁰ of the polynomial of the 12th order shown in Equation 3, respectively. ing. The input side of each EXOR circuit is commonly connected to the output side of the AND circuit. The input side of the AND is connected to the Q output of S12 and the EXC terminal which is an external input terminal, and the Q output of D12 is connected to the data output terminal DATA OUT.

Next, the operation of this circuit will be described with reference to the flowchart of FIG. 2 and the timing charts of FIGS. An "H" level signal is output from the EXC terminal, and a clock signal of a predetermined frequency is output from the CLK terminal. Each DFF operates in synchronization with the clock signal output from the CLK terminal, and when the clock signal is "L", all DFFs are cleared. First, S0 inputs the first bit data of the calling signal with a delay of half a cycle of the clock signal. Then, this data is input to EX0 from the Q output of S0. At this time, the waveform of the data output from EX0 OUT is distorted as shown in FIG. 4 due to the operation delay time of the ICs forming the AND circuit and EXO. However, since this data is read into the D input of D1 in the next stage with a half cycle delay of the clock signal, it is output from D1 in a shaped waveform. Since all stages of this circuit have this sampling configuration, data without error can be output from DATA OUT. Hereinafter, S0 inputs data in synchronization with the clock signal, and this data is input to the AND circuit from the Q output of S12 via S1, D 2 ... S11, D12, and from the Q output of D12. It is output to the DATA OUT terminal. Thereafter, this step is similarly repeated, and when the number of steps reaches 63, the data stored in D1 to D12 is the last 12 bits, that is, the error correction code. Here, if the signal output from the EXC terminal is kept at the "H" level (in the case of EXC in FIG. 7), a correct error correction code cannot be obtained (in the case of DATA OUT in FIG. 7). Therefore, when the number of steps is 63, that is, when the dividend order becomes 0, the AND circuit is activated to change the "H" level signal output from the EXC terminal to "L" level. As a result, a correct error correction code is serially output from the DATA OUT terminal (DATA OUT in FIG. 7). In the present embodiment, the case where the error correction code is a binary number of 12 digits and the multiplication / division polynomial for obtaining it is expressed by the formula shown in Formula 3 has been described. However, the number of digits of the error correction code to be obtained and each term of the division are It goes without saying that the number of DFFs and EXOR circuits or the position where EXOR circuits are connected can be changed according to the order.

[0008]

[Effect of the device]

 By using the error correction code generation circuit of the present invention, the error correction code can be serially output at high speed simply by inputting the calling name serially. Moreover, since the sampling configuration is used in all stages of the circuit, data error due to the operation delay time of the IC is eliminated.

[Brief description of drawings]

FIG. 1 is an embodiment of an error correction code generation circuit according to the present invention.

FIG. 2 is a flowchart showing the operation of the error correction code generation circuit according to the present invention.

FIG. 3 is a principle diagram of an error correction code generation circuit according to the present invention.

FIG. 4 is a timing chart of the error correction code generation circuit according to the present invention.

FIG. 5 is a timing chart of the error correction code generation circuit according to the present invention.

FIG. 6 shows an error correction code generation circuit included in a system for writing a call name in a ROM.

[Explanation of symbols]

S0-S12 ... D-type flip-flop circuit for sampling, D1-D12 ... D-type flip-flop circuit for memory, EX0-EX10 ... EXOR circuit, DATA
IN ··· data input terminal, DATA OUT ··· data output terminal, CLK · · clock signal input terminal.

[Equation 3]

[Table 1]

[Table 2]

[Table 3]

[Table 4]

Claims (1)

Claims for utility model registration 1. A circuit for generating error correction code by inputting data of a call name composed of a binary number in digital wireless communication, and a data input terminal for inputting the data. And a data output terminal for outputting an error correction code are connected by a circuit in which a plurality of D-type flip-flop circuits for data sampling and D-type flip-flop circuits for data memory are alternately connected, and a predetermined EXOR circuit is connected. A is connected between the input and output of a D-type flip-flop circuit for data sampling and a D-type flip-flop circuit for data memory at a predetermined location, and is also connected to an external input terminal.
An error correction code in which an output side of the ND circuit is connected to an input side of each of the EXOR circuits, and a clock signal output line is connected to a clock signal input terminal of each of the D-type flip-flop circuits via a NOT circuit. Generation circuit.