JPH056924A - Manufacture of double-sided tab - Google Patents
Manufacture of double-sided tabInfo
- Publication number
- JPH056924A JPH056924A JP3181626A JP18162691A JPH056924A JP H056924 A JPH056924 A JP H056924A JP 3181626 A JP3181626 A JP 3181626A JP 18162691 A JP18162691 A JP 18162691A JP H056924 A JPH056924 A JP H056924A
- Authority
- JP
- Japan
- Prior art keywords
- conductor
- layer
- double
- wiring pattern
- insulating layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/4501—Shape
- H01L2224/45012—Cross-sectional shape
- H01L2224/45015—Cross-sectional shape being circular
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
- H01L2224/45124—Aluminium (Al) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45147—Copper (Cu) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/4824—Connecting between the body and an opposite side of the item with respect to the body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01015—Phosphorus [P]
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は両面ＴＡＢ（Ｔａｐｅ
Ａｕｔｏｍａｔｅｄ Ｂｏｎｄｉｎｇ）の製造方法に関
し、特に高速応答性、高周波特性等の特性に優れ、製造
工程が大幅に短縮された両面ＴＡＢの製造方法に関す
る。The present invention relates to a double-sided TAB (Tape)
The present invention relates to a method for manufacturing automated bonding, and more particularly to a method for manufacturing a double-sided TAB that has excellent characteristics such as high-speed response and high-frequency characteristics and has a significantly shortened manufacturing process.
【０００２】[0002]
【従来の技術】従来の両面ＴＡＢの製造方法は、図１
（ａ）〜（ｅ）、図２（ａ）〜（ｄ）および図３（ａ）
〜（ｃ）のような工程により製造される。すなわち、図
１（ａ）に示されるように、中央にポリイミド等からな
る絶縁層１を有し、その両面に薄い導体層２ａ，２ｂか
らなる両面基板を準備する。次に、図１（ｂ）のように
両面にレジスト１０ａを形成する。さらに、図１（ｃ）
のごとく、裏面の導体層２ａをエッチングし、穴部を形
成する。その後、図１（ｄ）のように表面のレジスト１
０ａ間に電気メッキにより配線パターン５を形成する。
さらに、図１（ｅ）のようにレジスト１０ａを剥離後、
導体層２ａ，２ｂをレジストとして、穴部の絶縁層１を
化学的にエッチング除去してバイアホール部３を形成す
る。2. Description of the Related Art A conventional double-sided TAB manufacturing method is shown in FIG.
(A)-(e), FIG. 2 (a)-(d) and FIG. 3 (a).
It is manufactured by a process such as ~ (c). That is, as shown in FIG. 1A, a double-sided board having an insulating layer 1 made of polyimide or the like in the center and thin conductor layers 2a and 2b on both surfaces thereof is prepared. Next, as shown in FIG. 1B, resists 10a are formed on both sides. Furthermore, FIG. 1 (c)
As described above, the conductor layer 2a on the back surface is etched to form holes. After that, as shown in FIG.
The wiring pattern 5 is formed between 0a by electroplating.
Further, after removing the resist 10a as shown in FIG.
Using the conductor layers 2a and 2b as resist, the insulating layer 1 in the hole is chemically removed by etching to form the via hole portion 3.
【０００３】また、図２（ａ）に示されるごとく、導体
層２ａ，２ｂおよびバイアホール部３に、化学メッキに
より薄い導体皮膜１１を形成する。さらに図２（ｂ）の
ようにフォトレジスト法により片面（パターン側）にレ
ジスト１０ｂを形成する。そして、図２（ｃ）のように
裏面に電気メッキにより比較的厚みの大きい導体層２ｃ
を形成する。さらに、図２（ｄ）のように導体層２ｃお
よびレジスト１０ｂの上にさらにレジスト１０ｃを形成
する。Further, as shown in FIG. 2A, a thin conductor film 11 is formed on the conductor layers 2a and 2b and the via hole portion 3 by chemical plating. Further, as shown in FIG. 2B, a resist 10b is formed on one surface (pattern side) by a photoresist method. Then, as shown in FIG. 2C, the conductor layer 2c having a relatively large thickness is formed on the back surface by electroplating.
To form. Further, as shown in FIG. 2D, a resist 10c is further formed on the conductor layer 2c and the resist 10b.
【０００４】その後、図３（ａ）のようにエッチングに
より裏側の導体層２ｃの一部をエッチング除去し、レジ
スト１０ｂ，１０ｃを剥離する。さらに、図３（ｂ）の
ように導体層２ａ，２ｃおよび導体皮膜１１をレジスト
とし、デバイスホール部４等の窓あき部の絶縁層１を化
学的にエッチングする。最後に、図３（ｃ）のごとく、
フラッシュエッチングにより導体層２ａ，２ｂ，２ｃお
よび導体皮膜１１の所要部分のみを残して除去し、両面
ＴＡＢを形成していた。After that, as shown in FIG. 3A, a part of the conductor layer 2c on the back side is removed by etching to remove the resists 10b and 10c. Further, as shown in FIG. 3B, the conductor layers 2a and 2c and the conductor film 11 are used as a resist, and the insulating layer 1 in the window opening portion such as the device hole portion 4 is chemically etched. Finally, as shown in FIG. 3 (c),
The conductor layers 2a, 2b, 2c and the conductor film 11 were removed by flash etching, leaving only required portions, to form a double-sided TAB.
【０００５】しかしながら、このような製造方法では、
フォトレジストを３回または４回必要とし、絶縁層のエ
ッチング工程も２回必要であり、さらには化学メッキ処
理や電気メッキ処理が必要であるため、製造工程が極め
て繁雑となる。しかも、裏面側の導通用穴部と表面側の
配線パターンとの位置合せ精度に不良があると、両面の
導通が確保できないという課題もある。However, in such a manufacturing method,
Since the photoresist is required three or four times, the insulating layer etching step is required twice, and further chemical plating treatment or electroplating treatment is required, the manufacturing process becomes extremely complicated. In addition, there is also a problem that if there is a defect in the alignment accuracy between the conducting hole on the back side and the wiring pattern on the front side, conduction on both sides cannot be secured.
【０００６】[0006]
【発明が解決しようとする課題】本発明は、これらの従
来技術の課題を解決すべくなされたもので、製造工程が
大幅に短縮され、かつ経済性に優れ、また製品の自由度
が高く、しかも信頼性のある両面ＴＡＢの製造方法を提
供することを目的とする。SUMMARY OF THE INVENTION The present invention has been made to solve these problems of the prior art. The manufacturing process is significantly shortened, the cost is excellent, and the degree of freedom of products is high. Moreover, it is an object of the present invention to provide a reliable double-sided TAB manufacturing method.
【０００７】[0007]
【課題を解決するための手段】本発明の上記目的は、次
に示す製造方法によって達成される。The above object of the present invention can be achieved by the following manufacturing method.
【０００８】すなわち、本発明の両面ＴＡＢの製造方法
は、中央に絶縁層、その両面に導体層を有する基板を用
い、そのデバイス面の導体層をフォトレジストエッチン
グにより穴形状加工した後、両面の導体層をレジストと
し、該絶縁層を化学的または機械的に穴形状加工し開口
部を設け、次いでパターン面の導体層をフォトレジスト
エッチングによって配線パターンを形成し、該配線パタ
ーンとデバイス面の導体層であるグランド層とをワイヤ
ボンディングで接続し導通させ、接続部を樹脂で封止す
ることを特徴とする。That is, in the method for producing a double-sided TAB of the present invention, a substrate having an insulating layer in the center and conductor layers on both sides is used, and the conductor layer on the device surface is processed into a hole shape by photoresist etching. The conductor layer is used as a resist, the insulating layer is chemically or mechanically processed into a hole shape to form an opening, and then the conductor layer on the pattern surface is formed with a wiring pattern by photoresist etching. It is characterized in that the ground layer, which is a layer, is connected by wire bonding to make it conductive, and the connecting portion is sealed with resin.
【０００９】以下、本発明の製造方法を図面に基づいて
具体的に説明する。図４（ａ）〜（ｆ）は、本発明の製
造工程の一例を示す工程図である。The manufacturing method of the present invention will be specifically described below with reference to the drawings. 4A to 4F are process drawings showing an example of the manufacturing process of the present invention.
【００１０】本発明においても、図４（ａ）に示される
ように、中央にポリイミド等からなる絶縁層１を有し、
その両面に銅箔等からなる比較的薄い導体層２ａ，２ｂ
を有する両面基板を出発材料とする。次に、図４（ｂ）
に示されるようにデバイス面（裏面）の導体層２ｂにバ
イアホール部３、デバイスホール部４等の穴加工をフォ
トレジストエッチング法にて形成する。このバイアホー
ル部３が２メタルＴＡＢの両面導体接続用となる。さら
に、図４（ｃ）のように導体層２ａ，２ｂをレジストと
して絶縁層１を化学的または機械的加工により加工す
る。Also in the present invention, as shown in FIG. 4A, an insulating layer 1 made of polyimide or the like is provided at the center,
Relatively thin conductor layers 2a, 2b made of copper foil or the like on both sides thereof
A double-sided substrate having is used as a starting material. Next, FIG. 4 (b)
As shown in FIG. 5, holes are formed in the conductor layer 2b on the device surface (back surface) by the photoresist etching method such as the via hole portion 3 and the device hole portion 4. This via hole portion 3 is for connecting a double-sided conductor of 2-metal TAB. Further, as shown in FIG. 4C, the insulating layer 1 is processed by chemical or mechanical processing using the conductor layers 2a and 2b as resists.
【００１１】その後、図４（ｄ）のようにフォトレジス
トエッチングによりパターン面（表面）の導体層２ａに
配線パターン５を形成する。次に、図４（ｅ）に示され
るように、必要な端子メッキ６を施した後、ワイヤボン
ディング７により表面の導体である配線パターン５と裏
面の導体である加工された導体層（グランド層）８を接
続し、導通させる。そして、図４（ｆ）のように接続部
を樹脂９で封止し、両面ＴＡＢとする。Thereafter, as shown in FIG. 4D, a wiring pattern 5 is formed on the conductor layer 2a on the pattern surface (front surface) by photoresist etching. Next, as shown in FIG. 4E, after the necessary terminal plating 6 is applied, the wiring pattern 5 which is the conductor on the front surface and the processed conductor layer (the ground layer which is the conductor on the back surface) are formed by wire bonding 7. ) 8 is connected and made conductive. Then, as shown in FIG. 4F, the connecting portion is sealed with resin 9 to form a double-sided TAB.
【００１２】このようにして両面ＴＡＢが製造される。
この両面ＴＡＢのパターン面（表側）の斜視図の一例を
図５に示すと共に、Ｘ−Ｘ部分の断面図を図６に示す。
なお、図６における符号は図４と同じであり、両側導体
接続用窓あき部は折り曲用窓あき部と別個に設けられて
いるが、この折り曲げ用窓あき部を両面導体接続用窓あ
き部と兼用して用いてもよい。また、この両側導体接続
用窓あき部の形状は任意である。In this way, the double-sided TAB is manufactured.
An example of a perspective view of the pattern surface (front side) of the double-sided TAB is shown in FIG. 5, and a sectional view of the XX portion is shown in FIG.
The reference numerals in FIG. 6 are the same as those in FIG. 4, and the conductor-opening windows on both sides are provided separately from the bending window openings. It may also be used as a part. The shape of the window opening for connecting the conductors on both sides is arbitrary.
【００１３】[0013]
【実施例】以下、実施例に基づいて本発明を具体的に説
明する。EXAMPLES The present invention will be specifically described below based on examples.
【００１４】図４の工程に基づいて両面ＴＡＢを作成し
た。A double-sided TAB was prepared based on the process shown in FIG.
【００１５】すなわち、５０μｍのポリイミドを中間層
（絶縁層）とし、その両側に３５μｍの銅箔からなる導
電層を有する両面板（エスパネックス両面板、新日鉄化
学（株）製）を用意し、両面にドライフィルムラミネー
ト後、裏面の銅箔層の所望部分にフォトレジストエッチ
ング法によってデバイスホール部、バイアホール部（両
面導体接続用窓あき部）を形成した。次に、両面の銅箔
層をレジストとし、水加ヒドラジン含有アルカリ液にて
絶縁層であるポリイミドをエッチングした。That is, a double-sided plate (Espanex double-sided plate, manufactured by Nippon Steel Chemical Co., Ltd.) having 50 μm of polyimide as an intermediate layer (insulating layer) and conductive layers of 35 μm of copper foil on both sides thereof is prepared. After laminating the dry film, a device hole portion and a via hole portion (opening portion for double-sided conductor connection) were formed on a desired portion of the back side copper foil layer by a photoresist etching method. Next, using the copper foil layers on both sides as resist, the insulating layer, polyimide, was etched with an alkaline solution containing hydrazine hydrate.
【００１６】さらに、両面にドライフィルムをラミネー
ト後、表面にフォトレジスト法によって所定の配線パタ
ーンを形成した。必要部分にソルダーレジスト印刷を施
した後、フィンガー部、窓あき部にニッケル２μｍ、金
０．５μｍの厚さにそれぞれ電気メッキを施した。ま
た、この時の窓あき部の導体幅は１００μｍであった。
２５μｍφ金線にて、裏面の加工された導体層（グラン
ド層）をボールボンディング、配線パターンをウェッジ
ボンディングによりワイヤボンディングを行ない、両者
を接続し、導通させた。このワイヤボンディングによる
接続部をポリイミドワニスにより封止し、硬化した。Further, after laminating a dry film on both sides, a predetermined wiring pattern was formed on the surface by a photoresist method. After the solder resist printing was performed on the necessary portions, the finger portion and the window opening portion were electroplated to a thickness of nickel 2 μm and gold 0.5 μm, respectively. At this time, the conductor width of the window opening was 100 μm.
With a 25 μmφ gold wire, the processed conductor layer (ground layer) on the back surface was ball-bonded, and the wiring pattern was wire-bonded by wedge bonding, and both were connected and electrically connected. The connection portion formed by the wire bonding was sealed with a polyimide varnish and cured.
【００１７】このようにして得られた両面ＴＡＢは、高
速応答性、高周波特性等の特性に優れ、極めて信頼性の
高いものであった。The double-sided TAB thus obtained was excellent in characteristics such as high-speed response and high-frequency characteristics and was extremely highly reliable.
【００１８】[0018]
【発明の効果】以上のような本発明では、次のような効
果を奏する。The present invention as described above has the following effects.
【００１９】（１）フォトレジストの回数が少なくな
り、また無電解メッキ、電気メッキ処理が不要となり、
さらに絶縁層のエッチングが１回ですむため、製造工程
が大幅に短縮される。(1) The number of photoresists is reduced, and electroless plating and electroplating are not required,
Furthermore, since the insulating layer only needs to be etched once, the manufacturing process is greatly shortened.
【００２０】（２）両側導体接続用窓あき部の形状を任
意に形成することが可能となる。(2) It is possible to arbitrarily form the shape of the window opening for connecting the conductors on both sides.
【００２１】（３）ワイヤボンディングで接続し導通さ
せ、また樹脂で封止するために、熱衝撃等による熱応力
に対する信頼性がよい。(3) Since they are connected by wire bonding for electrical continuity and are sealed with resin, they have high reliability against thermal stress due to thermal shock or the like.
【００２２】また、本発明による製造方法において、材
料を選択することによって、副次的に次の効果を有する
こととなる。Further, in the manufacturing method according to the present invention, by selecting the material, the following effects are secondarily obtained.
【００２３】（１）絶縁層にポリイミドを用いた場合に
は耐熱性が良好なために、ワイヤボンディングにおいて
高温設定（２００℃）ができ、ワイヤボンディングの信
頼性がよい。(1) Since heat resistance is good when polyimide is used for the insulating layer, a high temperature (200 ° C.) can be set in wire bonding, and the reliability of wire bonding is good.
【００２４】（２）ワイヤボンディング用のチップやワ
イヤを選択することにより、ファインパターンも可能と
なる（例えば１８μｍφ金線、５０μｍ幅）。(2) Fine patterns are possible by selecting a chip or wire for wire bonding (for example, 18 μmφ gold wire, 50 μm width).
【００２５】（３）ワイヤボンディング用のワイヤを選
択することにより（銅線、アルミニウム線等）、従来よ
りも経済性に優れる。(3) By selecting a wire for wire bonding (copper wire, aluminum wire, etc.), it is more economical than conventional ones.
【００２６】従って、本発明は両面ＴＡＢの製造方法と
して好適である。Therefore, the present invention is suitable as a method for manufacturing a double-sided TAB.
【図１】 従来の両面ＴＡＢの製造方法を示す工程図。FIG. 1 is a process diagram showing a conventional double-sided TAB manufacturing method.
【図２】 従来の両面ＴＡＢの製造方法を示す工程図。FIG. 2 is a process diagram showing a conventional method for manufacturing a double-sided TAB.
【図３】 従来の両面ＴＡＢの製造方法を示す工程図。FIG. 3 is a process diagram showing a conventional double-sided TAB manufacturing method.
【図４】 本発明の両面ＴＡＢの製造方法を示す工程
図。FIG. 4 is a process drawing showing the method for producing a double-sided TAB of the present invention.
【図５】 本発明により得られる両面ＴＡＢの裏面（部
品面）の一例を示す斜視図。FIG. 5 is a perspective view showing an example of a back surface (component surface) of a double-sided TAB obtained by the present invention.
【図６】 図５のＸ−Ｘ部分の断面図。FIG. 6 is a cross-sectional view taken along line XX in FIG.
１ 絶縁層、 ２ａ，２ｂ 導体層、 ３ バイアホー
ル部、４ デバイスホール部、 ５ 配線パターン、
６ 端子メッキ、７ ワイヤボンディング、 ８ グラ
ンド層、 ９ 樹脂。1 insulating layer, 2a, 2b conductor layer, 3 via hole part, 4 device hole part, 5 wiring pattern,
6 terminal plating, 7 wire bonding, 8 ground layer, 9 resin.
Claims (1)
る基板を用い、そのデバイス面の導体層をフォトレジス
トエッチングにより穴形状加工した後、両面の導体層を
レジストとし該絶縁層を化学的に、または機械的に穴形
状加工し開口部を設け、次いでパターン面の導体層をフ
ォトレジストエッチングによって配線パターンを形成
し、該配線パターンとデバイス面の導体層であるグラン
ド層とをワイヤボンディングで接続し導通させ、接続部
を樹脂で封止することを特徴とする両面ＴＡＢの製造方
法。Claims: 1. A substrate having an insulating layer in the center and conductor layers on both sides thereof is used, and the conductor layer on the device side is processed into a hole shape by photoresist etching, and then the conductor layers on both sides are resisted. Then, the insulating layer is chemically or mechanically processed into a hole shape to form an opening, and then a wiring pattern is formed on the conductor layer on the pattern surface by photoresist etching to form the wiring pattern and the conductor layer on the device surface. A method of manufacturing a double-sided TAB, which comprises connecting the ground layer with wire bonding to make it conductive, and sealing the connecting portion with a resin.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3181626A JP2884271B2 (en) | 1991-06-27 | 1991-06-27 | Method for manufacturing double-sided TAB |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3181626A JP2884271B2 (en) | 1991-06-27 | 1991-06-27 | Method for manufacturing double-sided TAB |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH056924A true JPH056924A (en) | 1993-01-14 |
| JP2884271B2 JP2884271B2 (en) | 1999-04-19 |
Family
ID=16104073
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3181626A Expired - Fee Related JP2884271B2 (en) | 1991-06-27 | 1991-06-27 | Method for manufacturing double-sided TAB |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2884271B2 (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4945868A (en) * | 1989-06-21 | 1990-08-07 | General Motors Corporation | Two cycle exhaust recycling |
| WO1998018161A1 (en) * | 1996-10-17 | 1998-04-30 | Seiko Epson Corporation | Semiconductor device, method of its manufacture, circuit substrate, and film carrier tape |
-
1991
- 1991-06-27 JP JP3181626A patent/JP2884271B2/en not_active Expired - Fee Related
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4945868A (en) * | 1989-06-21 | 1990-08-07 | General Motors Corporation | Two cycle exhaust recycling |
| WO1998018161A1 (en) * | 1996-10-17 | 1998-04-30 | Seiko Epson Corporation | Semiconductor device, method of its manufacture, circuit substrate, and film carrier tape |
| US6274405B1 (en) | 1996-10-17 | 2001-08-14 | Seiko Epson Corporation | Semiconductor device, method of making the same, circuit board, and film carrier tape |
| US6452257B2 (en) | 1996-10-17 | 2002-09-17 | Seiko Epson Corporation | Film carrier tape |
| US6867068B2 (en) | 1996-10-17 | 2005-03-15 | Seiko Epson Corporation | Semiconductor device, method of making the same, circuit board, and film carrier tape |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2884271B2 (en) | 1999-04-19 |
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