JPH0568062A - Frequency offset compensation system - Google Patents

Abstract

PURPOSE:To improve the deterioration in the detection characteristic due to a frequency offset by estimating the magnitude of the frequency offset from a time change rate of a mean phase of plural partial series extracted from a unique word series. CONSTITUTION:An IF signal inputted to a detection circuit is divided into two signals at a branching device 1 and they are fed respectively to mixers 2-1, 2-2, the outputs are subject to band limit by low pass filters 5-1, 5-2 respectively and converted into digital signals by A/D converters 6-1, 6-2 and stored in a memory 7. A digital signal processor (DSP) 8 reads a partial unique word series from the memory 7 to obtain a mean phase in a signal space as to plural partial unique word series. Then the magnitude of a frequency offset is estimated from a time change rate of the mean phase. Thus, a deviation between a carrier frequency of a reception signal and a local oscillation frequency of a receiver is reduced.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a communication system applied to a low C / N propagation path such as mobile satellite communication, in which the carrier frequency of a received signal is different from the local oscillation frequency of the receiver, that is, the frequency. The present invention relates to a frequency offset compensation method that improves deterioration of detection characteristics due to offset.

[0002]

2. Description of the Related Art A receiver used for mobile satellite communication is
In order to obtain good detection characteristics even in a low C / N propagation path,
A synchronous detection method is used. The synchronous detection method requires the receiver to have a local oscillator that generates a signal synchronized with the carrier frequency of the received signal. However, low C
It is not easy to generate a signal that is synchronized with the carrier frequency of the received signal in the / N propagation path, and it is necessary to reduce the difference between the carrier frequency of the received signal and the local oscillation frequency of the receiver, that is, the frequency offset by using the synchronous detection method. It has become a technical issue for realization.

The structure of a conventional receiver using the synchronous detection method will be described below. FIG. 5 is a block diagram of the receiver. In the figure, an RF signal received by an antenna 11 is amplified by a low noise amplifier (LNA) 12, then band-limited by an RF bandpass filter 13, and multiplied by an output of a first local oscillator 15 by a mixer 14. Is converted to an intermediate frequency (IF). Further, the IF band pass filter 16 limits the band again, and the IF amplifier (AMP) 17 amplifies the signal to an appropriate signal level, which is then sent to the synchronous detection circuit 18 and the demodulation result is output from the output terminal 19.

FIG. 6 is a block diagram of a Costas type synchronous detection circuit for BPSK. IF signal (I
The output of the F amplifier 17) is divided into two signals by the distributor 21 and sent to the mixers 22-1 and 22-2. Also,
The output signal of the voltage controlled oscillator (VCO) 23 is directly applied to the mixer 22-1, and the VCO 23 is applied to the mixer 22-2.
A signal whose phase is shifted by 90 ° by the 90 ° phase shifter 24 is input to the output signal of.

The outputs of the mixers 22-1 and 22-2 are band-limited by the low-pass filters 25-1 and 25-2, and the output of 25-1 is sent to the discriminator 26 and a demodulated signal is output. In addition, the low-pass filters 25-1, 25
The output of -2 is converted into a phase error signal by the multiplier 27, band-limited by the loop filter 28, and added to the VCO 23 as a frequency control signal. At this time, the VCO 23 outputs a signal synchronized with the carrier frequency of the received signal.

[0006]

In order to obtain stable synchronization characteristics even in a low C / N propagation path in a Costas type synchronous detection circuit, the bandwidth of the loop filter must be narrowed, that is, the equivalent noise bandwidth (BW). ) Is required to be narrowed, but when BW is narrowed, there is a problem that the pull-in characteristic of synchronization is deteriorated. Further, it is known that the time required for pulling in the synchronization is proportional to the square of the frequency offset amount.

In order to compensate the frequency offset, it is necessary to measure the frequency offset amount, and actually, the frequency offset amount is obtained by measuring the change in the phase error. In the conventional Costas-type synchronous detection circuit, the maximum value is B because the phase difference between the received signal and the signal whose sign is determined is measured as the phase error.
It becomes ± π / 2 in the case of PSK and ± π / 4 in the case of QPSK.

Further, since the feedback loop is constructed by using all the measured phase errors, there is a possibility that the frequency offset may be erroneously corrected when a large amount of noise is entered, and the operation is unstable in the low C / N propagation path. There was a problem that it would be.

The present invention has been made to solve the above-mentioned problems, and is a means capable of obtaining stable synchronization characteristics even in a low C / N propagation path and performing synchronization pull-in at high speed. It is intended to provide.

[0010]

According to the present invention, in a transmission system for periodically transmitting a unique word sequence, a receiver is provided with means for extracting a plurality of partial unique word sequences from the unique word sequence. This is a frequency offset compensation method provided with means for obtaining the average phase in the signal space for each word sequence and means for estimating the magnitude of the frequency offset from the time change rate of these average phases.

[0011]

In the method of the present invention, since the frequency offset amount is measured by using the unique word portion, it is possible to measure up to a range of ± π regardless of the modulation method. In addition, since the phase error is measured as the average phase error of the partial unique word sequence, it is not easily affected by noise, and if a phase error that greatly differs from other phase errors due to the effect of noise is measured, the measurement is performed. Since it has a mechanism for rejecting the result, it operates stably even in a low C / N propagation path. Further, since the received signal is stored in the memory, the frequency offset amount can be repeatedly measured as long as the processing time of the processor permits, and the reliability of the measurement can be improved.

[0012]

1 is a block diagram of a synchronous detection circuit according to the present invention. The IF signal (output of the IF amplifier 17) input to the detection circuit is split into two signals by the distributor 1, and the mixer 2
-1, 2-2. Further, the output signal of the oscillator 3 is directly applied to the mixer 2-1 and the output signal of the oscillator 3 is applied to the mixer 2-2 by 90 ° by the phase shifter 4.
The shifted signal is input.

The outputs of the mixers 2-1 and 2-2 are band-limited by low-pass filters (LPF) 5-1 and 5-2, and then converted into digital signals by A / D converters 6-1 and 6-2. It is converted and stored in the memory 7. A digital-signal-processor (DSP) 8 reads the received signal from memory 7 and compensates for frequency offsets in the manner described below.

FIG. 2 shows the structure of a frame applied to the method of the present invention. In FIG. 2, the unique word is transmitted prior to the information, but since the received signal is stored in the memory in the present invention, the unique word may be in any part of the frame. Hereinafter, the frequency offset compensation method will be described with reference to FIG.

The received 1-frame signal is stored in the memory. The memory stores the received signals in succession without fail and switches the banks so that the received signal of the current frame can be read any number of times until all the signals of the next frame are received. Memory configuration. That is, while the received signal of the nth frame is being read from the first bank of the memory and being processed, the received signal of the n + 1th frame is stored in the second bank of the memory.
It is assumed that data is written in a bank, and the bank of the memory is switched every time one frame signal is written.

As shown in FIG. 4, a first partial unique word sequence (consisting of m symbol received signals)
Is read from the memory and the phase is compared with the unique word sequence stored in the DSP to obtain the instantaneous phase of the received signal of each m symbol. Next, the average phase of the partial unique word sequence is obtained from the m instantaneous phases by the method of least squares. In order to actually obtain the average phase, the calculation amount can be reduced by using the recursive least squares method (RLS algorithm).

The method of obtaining the average phase by the RLS algorithm will be described below. The partial unique word sequence read from the memory is x (t) (t = 1, 2, ..., M), DSP
Part of the unique word sequence stored inside is r (t) (t = 1, 2,
, M), the following operations are performed. Note that p (i), w (i), k (i), e (i), and x will be described below.
(I) and r (i) are complex numbers, and * indicates a complex conjugate.

(I) Initial setting p (0) = (δ, 0) * δ is a positive decimal number w (0) = (0,0)

(II) The following calculation is performed for i = 1, 2, ..., M.

[Equation 1]

(III) Obtaining the average phase θ ₁ The operation of θ ₁ = Arg [w (m)] is performed for the second, third, ..., Nth partial unique word series, and the average phases θ ₂ , θ ₃ ,
…, Θ _n is obtained.

Difference Δθk (k = 1, 2, ..., N−1) between the k-th average phase θ _k and the k + 1-th average phase θ _{k + 1}
Ask for. If the phase difference is large (generally, the absolute value of the phase difference exceeds π / 2), it is rejected as having a large influence of noise and low reliability, and the phase fluctuation amount, that is, Find the amount of frequency offset.

The obtained frequency offset amount is a specified value (generally, the frequency offset amount is 1/1 of the symbol rate.
(About 00) or less, the received signal of one frame stored in the memory is subjected to phase rotation according to the obtained frequency offset amount to correct the frequency offset, and the received signal is demodulated. When it is larger than the specified value, the phase rotation is applied to the received signal of one frame stored in the memory according to the obtained frequency offset amount, the temporary frequency offset is corrected, and the result is stored again in the memory. Repeat the operations from and.

The above is the basic embodiment of the present invention.
The following improvements are possible. (1) Since the frequency offset amount does not change greatly for each frame, it is possible to use the frequency offset amount detected from a certain frame as the initial value of the frequency offset amount of the next frame.

(2) In the above description, the first partial unique word series to the nth partial unique word series are all in the same frame. However, when the frequency offset amount is small, a plurality of plural parts are used. By extracting the partial unique word sequence from the frame, more accurate estimation can be performed. Further, there is also a method in which when the frequency offset amount is large, the partial unique word sequence is taken out from one frame, and the partial unique word sequences are taken out from a plurality of frames as the frequency offset amount becomes smaller.

(3) In FIG. 1, the oscillator 3 having a fixed frequency is used. However, if the oscillator 3 is replaced with a VCO and the correction amount of the frequency offset is controlled by a signal converted into an analog signal, the frequency offset is corrected. Since the generated signal is stored in the memory, the load of the arithmetic processing of the DSP can be lightened and the power consumption can be saved.

[0026]

As described above, in the present invention, low C /
Even if the frequency offset amount is large in the N propagation path, the frequency offset amount can be estimated and corrected quickly and accurately, and the problem of the synchronous detection method can be solved.

[Brief description of drawings]

FIG. 1 is a diagram showing a configuration of a synchronous detection circuit including a frequency offset compensation method of the present invention.

FIG. 2 is a diagram showing a frame structure of a signal used in the present invention.

FIG. 3 is a diagram showing an algorithm of the frequency offset compensation method of the present invention.

FIG. 4 is a diagram showing a method of extracting a partial unique word sequence.

FIG. 5 is a diagram illustrating an example of a receiver including a synchronous detection circuit.

FIG. 6 is a diagram showing a conventional Costas type synchronous detection circuit for BPSK.

[Explanation of symbols]

 1 Distributor 2-1, 2-2 Mixer 3 Oscillator 4 Phase shifter 5-1, 5-2 Low-pass filter 6-1, 6-2 A / D converter 7 Memory 8 Digital-signal-processor

Claims (1)

[Claims] 1. A transmission system for periodically transmitting a unique word sequence, wherein a receiver extracts a plurality of partial unique word sequences from the unique word sequence, and an average of a plurality of partial unique word sequences in a signal space. A frequency offset compensating method, characterized in that means for determining the respective phases and means for estimating the magnitude of the frequency offset from the time change rate of these average phases are provided.