JP3388079B2 - Receiver - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a receiving device for mobile communication and the like, and more particularly to a device capable of accurately establishing synchronization even when there is a large fluctuation in the reception level or a large frequency offset.

[0002]

2. Description of the Related Art In TDMA digital mobile communication, a transmitting side transmits data by including a synchronization word in a time slot, and a receiving side detects a known pattern of the synchronization word and decodes the received data. Establish synchronization.

As shown in FIG. 10, the conventional receiving apparatus has an A / D converter 1003 for sampling the in-phase component (I-ch) of the received signal, as a mechanism for establishing this synchronization.
A for sampling the quadrature component (Q-ch) of the received signal
/ D converter 1004 and the number of known pattern symbols (N
, A memory 1007 for storing the received signals, a memory 1013 for storing the patterns of known symbols, and a correlation for obtaining the correlation value between the in-phase component and the quadrature component of the received signal and the in-phase component and the quadrature component of the known symbol. A detector 1010, an envelope detection circuit 1012 for obtaining the envelope of the correlation output, and a determination circuit 1018 that compares the envelope of the correlation value with a threshold value and determines that a known symbol is detected when the correlation value is larger than the threshold value. I have it.

In this device, the correlator 1010 has a memory 1007.
The correlation value between the received signal of N symbols stored in the memory and the known pattern held in the memory 1013 is calculated, and the envelope detection circuit 1016 calculates the envelope of this correlation value. By the operation of the correlator 1010 and the envelope detection circuit 1016, the correlation between the received signal and the known symbol is given by the following equation (1).

Comb = (1 / N) √ (Σr (i) × sw * (i)) (Σ is added from i = 1 to N) (1) where sw (i) is a known pattern and N is The number of known pattern symbols, r (i) represents the received signal, and * represents the complex conjugate.

By performing such calculation, the correlation value becomes 1 when the received signal sequence is the same as the known pattern, and becomes a value much smaller than 1 when it is different. Judgment circuit 10
18 compares this correlation value with a threshold value, and determines that a known pattern has been detected when the correlation value is larger than the threshold value.

[0007]

However, in actual communication, there are several factors that prevent synchronization establishment in this way. One of them is fading that occurs in the environment of mobile communication, and large reception level fluctuations from moment to moment make the detection of known patterns erroneous. Now, assuming that the level fluctuation ratio of the received signal is A, the correlation value is given by the following equation (2). comb = √ (Σ (Ar (i)) × sw * (i)) (Σ is added from i = 1 to N) = A ^1/2 √ (Σr (i) × sw * (i)) (2) However, in Expression (2), sw (i) is a known pattern, N is the number of symbols in the known pattern, r (i) is a received signal, and * is a complex conjugate. Further, here, for simplicity, it is assumed that the variation ratio A of the received signal does not vary at the reception time of the known pattern. This correlation value is the amplitude ratio A of the received signal at the correct time when the correlation result between the received signal and the known pattern becomes 1.
Is larger than 1, it is larger than 1, and if the amplitude ratio A is smaller than 1, it is smaller than 1. Therefore, even if this correlation value is compared with the threshold value, it becomes impossible to correctly obtain the reception time of the known pattern.

[0008] Therefore, conventionally, a saturation type receiver has been used to solve the above problem by making the envelope of the received signal constant. However, in order to realize a highly functional received signal correction function such as an equalizer, it is necessary to use a linear receiver that directly receives the level of the received signal, rather than a saturation type receiver. Even when using such a linear receiver, there is a demand for a synchronization mechanism capable of establishing synchronization without being affected by the level fluctuation of the received signal.

The frequency difference between the modulation frequency of the transmitter and the demodulation frequency of the receiver (hereinafter referred to as frequency offset).
Even if is large, the known symbol detection performance in the receiver is deteriorated. FIG. 3 shows the influence of this frequency offset on the correlation value, where the horizontal axis represents the frequency offset and the vertical axis represents the correlation value. As can be seen from FIG. 3, as the frequency offset becomes larger, the correlation value becomes smaller, so that the known symbol cannot be detected accurately.

[0010] The present invention is intended to solve such conventional problems, <br/> Hisage Kyosu Rukoto a receiver capable of accurately detecting a known pattern, even when the level variation of the received signal is large It is an object.

[0011]

Therefore, in the receiving apparatus of the present invention, a correlation value calculating means for obtaining a correlation value between a received signal and a known pattern composed of known symbols, and an envelope of the correlation value. For detecting the envelope of the received signal, the envelope detecting means for obtaining the envelope of the received signal, the normalization means for normalizing the envelope of the correlation value with the envelope of the received signal, and the threshold for the normalized correlation value And a determination means for comparing with.

As described above, since the correlation value is standardized by the received signal level, the correlation value and the threshold value can be stably compared even when the received signal level changes.

[0013]

[0014]

[0015]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The invention according to claim 1 of the present invention is a receiving apparatus provided with a mechanism for detecting a known symbol included in a received signal, and the known signal is composed of the received signal and the known symbol. Correlation value calculating means for obtaining the correlation value with the pattern, envelope detecting means for obtaining the envelope of this correlation value, reception envelope detecting means for obtaining the envelope of the received signal, and envelope of the correlation value for the received signal The standardization means for normalizing with the envelope of and the judgment means for comparing the standardized correlation value with the threshold value are provided, and since the correlation value is standardized with the reception signal level, the reception signal level is Even if there is a change, it is possible to stably compare the correlation value with the threshold value.

According to a second aspect of the present invention, in a receiver having a mechanism for detecting a known symbol included in a received signal, a correlation value between the received signal and a known pattern formed by the known symbol is calculated. Correlation value calculation means for obtaining, power detection means for obtaining power of this correlation value, reception power detection means for obtaining power of received signal, standardization means for standardizing power of correlation value with power of received signal, standard It is provided with a determination means for comparing the normalized correlation value with a threshold value.In this case also, since the correlation value is standardized by the received signal level, even when the received signal level changes, the correlation value and the threshold value Can be stably compared. Also, compared to the case of calculating the envelope curve, the calculation of the square root becomes unnecessary,
The arithmetic processing becomes simple.

[0017]

[0018]

[0019]

[0020]

[0021]

[0022]

Embodiments of the present invention will be described below with reference to the drawings.

(Embodiment 1) The receiving apparatus of the first embodiment has a synchronization mechanism for accurately detecting a known pattern included in a received signal even when the received signal level fluctuates greatly. As shown in FIG. 1, this device uses a reception envelope detection circuit 118 for obtaining an envelope of a reception signal as a synchronization mechanism.
And a normalization circuit 120 for normalizing the envelope of the correlation value with the envelope of the received signal. Other configurations are the same as those of the conventional device (FIG. 10).

In this device, the in-phase component (I-
ch) and the quadrature component (Q-ch) are input to A / D converters 103 and 104, respectively, and the quantized results are stored in a memory.
Enter in 107. The memory 107 stores received signals of a known pattern number (N). The new received signal is overwritten on the oldest received signal.

The memory 111 stores known patterns. The correlator 110 obtains a correlation value between the received signal stored in the memory 107 and the known pattern stored in the memory 111. In practice, the correlator 110 obtains the correlation values of the in-phase component and the quadrature component by the following equations (3) and (4), respectively, and then the envelope detection circuit 116 calculates the in-phase component by the following equation (5). Find the envelope of the component and the orthogonal component. Where subscript I
Represents an in-phase component and Q represents a quadrature component.

Comb _I = Re [Σsw (i) × r (i) *] = Σ {sw _I (i) × r _I (i) + sw _Q (i) × r _I (i)} (3) comb _Q = Im [Σsw (i) × r (i) *] = Σ {-sw Q (i) × r I (i) + sw I (i) × r Q (i)} (4) (Σ is i = 1 To N) comb = √ (comb _I ² + comb _Q ² ) (5) The calculation by these equations can be easily performed by the software of the signal processor such as DSP.

On the other hand, the reception envelope detection circuit 118 obtains the envelope of the received signal by the following equation (6).

A = √ (Σr (i) × r (i) *) (Σ is added from i = 1 to N) = √ (Σ {r _I (i) × r _I (i) + r _Q (i) × r _Q (i)}) (6) Next, the normalization circuit 120 normalizes the correlation value by dividing the envelope 117 of the correlation value by the envelope 119 of the received signal according to the following equation (7). To do.

X = comb / A (7) The decision circuit 122 compares the correlation value standardized by the envelope of the received signal with a threshold value, and when the correlation value is larger than the threshold value, a known symbol is detected. It is determined that it was done.

The comparison with the threshold value obtained by dividing the correlation value by the envelope is completely equivalent to the comparison with the correlation value obtained by multiplying the threshold value by the envelope. The latter makes the division unnecessary.

As described above, in this receiving apparatus, since the correlation value is standardized by the envelope of the received signal, the known pattern can be detected without being influenced by the received signal level. Therefore, it is possible to stably establish synchronization even when fading occurs.

(Embodiment 2) The receiving apparatus of the second embodiment can shorten the calculation time for establishing synchronization. In order to eliminate the square root calculation that consumes a great amount of calculation time, this device is, as shown in FIG. 2, replaced with a correlation value envelope detection, a power detection circuit 21 for detecting the power of the correlation value.
6 and a power detection circuit 218 that detects the power of the received signal instead of detecting the envelope of the received signal, and the determination circuit 222 has a power threshold value as a threshold value. Other configurations are the same as those of the first embodiment (FIG. 1).

In this device, as in the first embodiment, the received signal is stored in the memory 207, and the correlator 210 uses the equations (3) and (4) to determine the received signal and the known pattern. Compute the correlation values for the in-phase component and the quadrature component with.

Next, the correlation value power detection circuit 216 obtains the correlation power from the in-phase component 214 and the quadrature component 215 of the correlation value by the following equation (8).

Comb = comb _I ² + comb _Q ² (8) On the other hand, the received signal power detection circuit 218 obtains the received signal power from the in-phase component 208 and the quadrature component 209 of the received signal by the following equation (9). .

A = Σr (i) × r (i) * (Σ is added from i = 1 to N) = Σ {r _I (i) × r _I (i) + r _Q (i) × r _Q (i )} (9) Next, the normalization circuit 220 normalizes the correlation value by dividing the power 217 of the correlation value by the power 219 of the received signal according to the following equation (10).

X = comb / A (10) The determination circuit 222 compares the power of the correlation value standardized by this received signal with a threshold value, and when the power of this correlation value is larger than the threshold value, the known symbol is Judge as detected.

The comparison of the correlation value by the threshold value obtained by dividing the power by the power is completely equivalent to the comparison by the correlation value obtained by multiplying the threshold value by the power. The latter makes the division unnecessary.

As described above, in this receiving apparatus, the power of the correlation value is standardized by the power of the received signal, and the known pattern is detected using the value, so that the known value is obtained regardless of the received signal level. The pattern of can be detected.

Further, since this receiving device does not use the square root circuit, the execution time is short when the calculation is performed using the signal processor such as DSP.
Real-time processing becomes possible. Further, even when this device is realized by hardware, the configuration is simple and the current consumption is small. However, since the entire operation configuration is used by squaring each value in the first embodiment, the dynamic range is half that in the first embodiment when implemented by fixed-point hardware.

(Embodiment 3) A receiving apparatus according to the third embodiment has a mechanism for detecting a vector of frequency offset. This device, as shown in FIG. 4, is an A / D converter 403 for sampling the in-phase component (I-ch) 401 of the received signal.
An A / D converter 404 that samples the quadrature component (Q-ch) 402 of the received signal, a delay circuit 410 that delays the received signal by one symbol time, and a received signal at the current time
Difference circuit 40 that detects the phase difference from the received signal before the symbol
7, a memory 416 that stores a phase difference between known symbols that form a known pattern, and a known symbol for the output signal of the difference circuit 407 (a known symbol at the current time and a known symbol one symbol before). An inverse modulation circuit 413 that performs inverse rotation processing by the phase difference of (symbol) and an averaging circuit 419 that averages the output of the inverse modulation circuit 413 and outputs a frequency offset vector.

Here, the received signal vector r (t) consisting of the in-phase component and the quadrature component is expressed in polar coordinates exp (jθ (t)).
Will be expressed as The known pattern is composed of a sequence of known symbols, and the amount of phase change between each known symbol and the symbol immediately before it (that is, the angle formed by both received signal vectors) is known. The memory 416 stores the amount of phase change between known symbols.

In this device, the in-phase component (I-
ch) and the quadrature component (Q-ch) are input to the A / D converters 403 and 404, respectively, and the A / D converters 403 and 404 output the quantized in-phase component and quadrature component. These components are input to the difference circuit 407 and the delay circuit 410, and the delay circuit 41
0 delays it by one symbol time and outputs it to the difference circuit 407. In response to this, the difference circuit 407 detects the phase difference between the current symbol and the immediately preceding symbol output from the delay circuit 410 by the following equation (11).

Δ = r (t) × r * (tT) = exp (j (θ (t) + at)) × exp (−j (θ (tT) + a (tT))) = exp (j (θ ( t) −θ (tT)) × exp (jaT) (11) where T represents the time between symbols (1 symbol time), and a represents the amount of phase change due to frequency offset per symbol. Where exp (j (θ
(t) −θ (t−T))) is a term due to modulation, and exp (j
aT) is a term due to the frequency offset.

This actual calculation is performed as follows. δ _I = Re [r (t) × r * (t−T)] = r _I (t) × r _I (t−T) + r _Q (t) × r _Q (t−T) (12) δ _Q = Im [r (t) × r * (t−T)] = −r _I (t) × r _Q (t−T) + r _Q (t) × r _I (t−T) (13) Subscript I and Q represent an in-phase component and a quadrature component, respectively. The in-phase component 408 and the quadrature component 409 of the calculation result of the difference circuit 407 are input to the inverse modulation circuit 413.

The inverse modulation circuit 413 stores the phase difference of the known symbol corresponding to the difference signal output from the difference circuit 407.
A reverse rotation process (inverse modulation process) of reading the difference signal from 416 and rotating the difference signal in the opposite direction by the phase difference of the known symbol is performed. Now, assuming that the known symbols forming the known pattern are received and the differential signal of the received signal is output from the differential circuit 407, the inverse modulation circuit 413 is configured to operate in the memory 4
The phase difference between the corresponding known symbol and the preceding symbol is read from 16 and reverse rotation processing is performed by the following equation (14).
As a result, the in-phase component and the quadrature component of the phase change amount for one symbol due to the frequency offset are output.

Δθ = δ × δsw * (t) = exp (j (θ (t) −θ (t−T)) × exp (jaT) × exp (−j (θ (t) −θ (t−T) )) = Exp (jaT) = δθ _I + jδθ _Q (14) where δsw is the amount of phase change of a known symbol in one symbol time.

This calculation is actually performed by the following equations (15) (1
It is performed by the product-sum operation of 6).

Δθ _I = Re [δ (t) × δsw * (t)] = δ _I (t) × δsw _I (t) + δ _Q (t) × δsw _Q (t) (15) δθ _Q = Im [ δ (t) × δsw * ( t)] = -δ I (t) × δsw Q (t) + δ Q (t) × δsw I (t) (16) in this way, the in-phase component 414 of the frequency offset The quadrature component 415 is detected.

The inverse modulation circuit 413 performs this process for the number of known symbols, and the averaging circuit 419 obtains the average value.

By the above processing, the amount of phase change per symbol due to the frequency offset can be obtained using the known symbols, and the frequency offset vector can be detected.

In this apparatus, since the frequency offset vector is calculated only by the product-sum calculation without including the calculation such as arctan, the calculation is simple.

(Embodiment 4) The receiver of the fourth embodiment has a mechanism for correcting the frequency offset vector. This device, as shown in FIG. 5, is an A / D converter for sampling an in-phase component 501 and a quadrature component 502 of a received signal.
503, 504, a frequency offset output circuit 508 that outputs a frequency offset vector estimated value, a vector product circuit 515 that updates the frequency offset vector estimated value, and a frequency offset removal circuit 507 that corrects the frequency offset of the received signal. ing.

The frequency offset output circuit 508 outputs an estimated value of a constant frequency offset vector here.

The vector product circuit 515 calculates a vector product of the estimated value of the frequency offset vector and the correction value used for the correction of the frequency offset of the previous symbol, and uses it as the frequency offset correction value of the current symbol to remove the frequency offset. Output to the circuit 507.

The input signal r '(t) to this device is expressed by the following equation (17) when the frequency offset is included.

R ′ (t) = r (t) × exp (jat) = r _I ′ (t) + jr _Q ′ (t) (17) where a is the phase change amount due to the frequency offset in one symbol time. is there.

For this input signal, the frequency offset removing circuit 507 outputs the ex signal output from the vector product circuit 515.
The frequency offset is corrected using the correction value of p (ja't). Here, a'is an estimated value of the amount of phase change due to the frequency offset.

The input signal received at time T is expressed by the following expression (18), and the correction value for the input signal is expressed by the expression (19).

R ′ (T) = r (T) × exp (jat) = r _I ′ (T) + jr _Q ′ (T) (18) δ (T) = exp (−ja′t) = δ _I ( T) −jδ _Q (T) (19) The frequency offset removing circuit 507 corrects the frequency offset of this input signal by the following equation (20).

R ″ (T) = r ′ (T) × δ (T) = r (T) × exp (jat) × exp (−ja′t) = r (T) × exp (j (a− a ') T) (20) If the frequency offset estimation value a'is estimated correctly, aa' becomes zero and the frequency offset is removed. At this time, the frequency offset removal circuit 507 performs the actual calculation by using the in-phase component 505 and the quadrature component 506 of the received signal, and the in-phase component 511 and the quadrature component 512 of the frequency offset correction vector. 22).

R _I ″ (T) = Re [r ′ (T) × δ (T)] = r _I ′ (T) × δ _I (T) + r _Q ′ (T) × δ _Q (T) ( 21) r _Q ″ (T) = Im [r ′ (T) × δ (T)] = − r _I ′ (T) × δ _Q (T) + r _Q ′ (T) × δ _I (T) ( 22)

Next, consider the case of time 2T. The input signal received at time 2T is expressed by the following equation (23). In this case, the phase change due to the frequency offset is 2a.
You can see that it is T.

R ′ (2T) = r (2T) × exp (j2aT) = r _I ′ (2T) + jr _Q ′ (2T) (23) At this time, the vector product circuit 515 outputs from the frequency offset output circuit 508. The vector product of the calculated frequency offset vector estimation value δ (T) and the correction value δ (T) used to correct the frequency offset of the preceding symbol is calculated, and the calculation result is used as the frequency offset correction value of the current symbol to remove the frequency offset. Output to the circuit 507. The frequency offset correction value of the current symbol at this time is as shown in the following equation (24): δ (2T) = δ (T) × δ (T) = exp (−ja′T) × exp (−ja ′) T) = exp (−j2a′T) = δ _I (2T) −jδ _Q (2T) (24), and the amount of phase change is from (−a′T) to (−2a ′).
T).

Therefore, the frequency offset removing circuit 507
Can correct the frequency offset vector included in the input signal r ′ (2T) by the following equation (25) using this correction value.

R ″ (2T) = r ′ (2T) × δ (2T) = r (2T) × exp (j2at) × exp (−j2a′t) = r (2T) × exp (j2 (a− a ') T) (25) This actual calculation is performed by the in-phase component 505 and the quadrature component 5 of the received signal.
06, and the in-phase component 511 of the frequency offset correction vector
And the quadrature component 512 are used according to equations (21) and (22).

Similarly, for the input signal after the time 3T, the vector product circuit 515 updates the frequency offset correction value, and the frequency offset removal circuit 507 includes it in the input signal using the updated correction value. The frequency offset is removed.

As described above, in this apparatus, the frequency offset vector can be corrected only by the product-sum calculation.

(Embodiment 5) As shown in FIG. 6, the receiver of the fifth embodiment has a mechanism of the third embodiment, which is a vector-frequency conversion circuit 622 for converting a vector (phase) into a frequency. Is added, it is possible to obtain the displacement of the frequency to be used for VOC control or the like from the detected frequency offset vector.

The frequency offset vector is effective when the frequency offset is corrected using the correction mechanism of the fourth embodiment. However, when correcting a frequency offset using a VCO that controls an analog oscillator with a voltage, it is more effective to obtain a frequency displacement amount and give this to the VCO than to obtain a frequency offset vector. is there.

In this device, the in-phase component 620 and the quadrature component 621 of the frequency offset vector are output from the averaging circuit 619 by the operation described in the third embodiment by the following equation (26).

[0073] δ = exp (-jat) = δ I -jδ Q (26) where, a is a phase variation per 1 symbol time due to the frequency offset, the unit is [rad / s]. When this is converted into frequency displacement δf [Hz], a /
2π.

The vector-frequency conversion circuit 622 calculates δf by the equation (27) from the quadrature component δ _I and the in-phase component δ _Q of the frequency offset vector.

[0075] ^{δf = a / 2π = tan -1} (-δ Q / δ I) / 2πT (27) Thus, in this apparatus, vector - frequency conversion circuit 62
By adding 2, the frequency offset vector is calculated from the quadrature component δ _I and the in-phase component δ _Q of the frequency offset vector.
Can be detected.

(Embodiment 6) The receiver of the sixth embodiment has a structure for correcting the frequency offset detected by the mechanism of the fifth embodiment. This device
As shown in FIG. 7, a D / A converter 729 that converts the estimated frequency offset value into an analog voltage, a voltage controlled oscillator (VCO) 731 that controls the oscillation frequency by the voltage, a high-frequency input signal, and the VCO 731. A mixer 725 that multiplies the frequency to convert it to a low frequency, a band-pass filter (BPF) 726 that removes unnecessary frequencies, and a quadrature detection circuit 728 that converts the IF frequency into an in-phase component and a quadrature component. Other configurations are the same as those of the fifth embodiment.

In this apparatus, the detected frequency offset 723 is output from the phase-frequency conversion circuit 722, and the D / A
Input to converter 729. The D / A converter 729 converts the frequency offset estimated value 723 into the analog voltage 730.

The VCO 731 is an oscillator capable of controlling the oscillation frequency by voltage, and can finely adjust the oscillation frequency according to the analog voltage 730 of the frequency offset estimated value with respect to the preset oscillation frequency.

The mixer 725 outputs from the VCO 731,
Frequency where the oscillation frequency is finely adjusted (frequency = f2)
732 is multiplied by the high frequency reception signal (frequency = f1) 724. Then, two types of frequencies 733, (f1 + f2) and (f1-f2), are output from the mixer 725.

The BPF 726 is configured to pass the lower frequency (f1-f2) of them. The quadrature detection circuit 728 outputs the output of the BPF 726 to the in-phase component 701 and the quadrature component 7
Convert to 02 and.

As described above, in this device, the adjustment according to the detected frequency offset is applied to the mixer 725 through the feedback loop to correct the frequency offset.

(Embodiment 7) As shown in FIG. 8, the receiver of the seventh embodiment has a frequency offset vector detection mechanism of the third embodiment and a frequency offset correction of the fourth embodiment. This is a combination of the mechanism and the known symbol detection mechanism of the first embodiment.

The operation of each mechanism is as described in each embodiment.

In this apparatus, first, the frequency offset vector detection mechanism estimates the in-phase component 820 and the quadrature component 821 of the frequency offset vector from the received signal sequence of known symbols (N). At this time, the received signals for the known symbols (N) are stored in the memory 822.

Next, the frequency offset compensating mechanism uses the in-phase component 820 and the quadrature component 821 of the frequency offset vector to compensate the frequency offset of the received signal stored in the memory 822.

The in-phase component 826 and the quadrature component 827 of the received signal in which the frequency offset has been compensated are input to the known symbol detection mechanism, where the correlation between the in-phase component 835 and the quadrature component 836 of the known symbol is calculated. Further, the received signal is normalized with the envelope 840, and the reception of a known symbol is detected by the threshold value judgment.

As described above, this apparatus can detect the reception time of a known symbol without being affected by the frequency offset and the fluctuation of the received signal level.

(Embodiment 8) As shown in FIG. 9, the receiver of the eighth embodiment includes the frequency offset detecting mechanism of the fifth embodiment and the known symbol detecting mechanism of the first embodiment. In combination with the known symbol detection mechanism, a known pattern selection mechanism for providing the detected known pattern to which the frequency offset is added is provided to the correlator 933.

This known pattern selection mechanism uses a memory 925 storing known patterns to which several types of frequency offsets are added and the detected frequency offsets.
A selection circuit 924 for selecting a known pattern to be read from the memory 925 is provided.

In this apparatus, the frequency offset detecting mechanism estimates the frequency offset 923 from the received signal sequence of known symbols (N pieces). At this time, the received signals for the known symbols (N) are stored in the memory 930.

On the other hand, the selection circuit 924, to which the frequency offset 923 is input, selects the frequency closest to the frequency offset 923 from the known symbols to which a plurality of types of frequency offsets stored in the memory 925 of the known pattern selection mechanism are added. The known symbol with the offset added is selected and output to the correlator 933.

At this time, the selection circuit 924 quantizes (1) the frequency offset 923, calculates the argument of the table,
(2) By using this argument, a table is looked up from the memory 925 in which known patterns to which a plurality of types of frequency offsets are stored are stored, and known patterns to which appropriate frequency offsets are added are obtained. Obtainable.

The correlator 933 of the known symbol detection mechanism includes the quadrature component 931 and the in-phase component 932 of the received signal stored in the memory 930, and the in-phase component 928 and the quadrature component 929 of the known symbol selected by the selection circuit 924. Calculate the correlation of. The subsequent procedure in the known symbol detection mechanism is the same as in the case of the seventh embodiment.

This device can reduce the circuit scale in the hardware configuration and the amount of calculation when implemented by software, as compared with the seventh embodiment.

[0095]

As is clear from the above description, the receiving apparatus of the present invention can accurately detect a known symbol and establish stable synchronization even when the level fluctuation of the received signal is large.

[0096]

[0097]

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a receiving device according to a first embodiment of the present invention,

FIG. 2 is a block diagram showing a configuration of a receiving device according to a second embodiment of the present invention,

FIG. 3 is a diagram showing deterioration in frequency offset of a correlation value,

FIG. 4 is a block diagram showing a configuration of a receiving device according to a third embodiment of the present invention,

FIG. 5 is a block diagram showing a configuration of a receiving device according to a fourth embodiment of the present invention,

FIG. 6 is a block diagram showing a configuration of a receiving device according to a fifth embodiment of the present invention,

FIG. 7 is a block diagram showing a configuration of a receiving device according to a sixth embodiment of the present invention,

FIG. 8 is a block diagram showing a configuration of a receiving device according to a seventh embodiment of the present invention,

FIG. 9 is a block diagram showing a configuration of a receiving device according to an eighth embodiment of the present invention,

FIG. 10 is a block diagram showing a configuration of a conventional receiving device.

[Explanation of symbols]

103, 104, 203, 204, 403, 404, 503, 504, 603, 604, 703, 704, 803, 804, 903, 904, 1003, 1004 A / D converters 107, 111, 207, 211, 416, 616, 716, 815, 821, 833,
916, 925, 930, 1007 Memory 110, 210, 830, 933, 1010 Correlators 116, 118, 836, 838, 936, 938, 1016 Envelope detection circuit 120, 840, 940 Normalization circuit 122, 222, 842, 942, 1018 Determination circuit 216, 218 Power detection circuit 407, 607, 707, 807, 907 Differential circuit 410, 610, 710, 809, 910 Delay circuit 413, 613, 713, 812, 913 Inverse modulation circuit 419, 619, 719 , 818, 919 Average circuit 508 Frequency offset output circuit 515, 827 Vector product circuit 507, 824 Frequency offset removal circuit 622, 722, 922 Vector-frequency conversion circuit 729 D / A converter 731 Voltage controlled oscillator 725 Mixer 726 Bandpass filter 728 Quadrature detector 924 Selection circuit

Front page continuation (58) Fields surveyed (Int.Cl. ⁷ , DB name) H04L 27/00-27/38 H04L 7/00

Claims (2)

(57) [Claims] 1. A receiving device having a mechanism for detecting a known symbol included in a received signal, the correlation value calculating means for obtaining a correlation value between the received signal and a known pattern formed by the known symbol, Envelope detecting means for obtaining the envelope of the correlation value, reception envelope detecting means for obtaining the envelope of the received signal, and normalization means for normalizing the envelope of the correlation value with the envelope of the received signal, A receiving device, comprising: a determination unit that compares the normalized correlation value with a threshold value. 2. A receiving device having a mechanism for detecting a known symbol included in a received signal, the correlation value calculating means for obtaining a correlation value between the received signal and a known pattern composed of the known symbol, Power detection means for obtaining the power of the correlation value, reception power detection means for obtaining the power of the received signal, normalizing means for normalizing the power of the correlation value with the power of the received signal, and the normalized correlation A receiving device, comprising: a determining unit that compares a value with a threshold value.