JP2967658B2 - Tracking receiver - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an automatic aerial tracking receiver.

[0002]

2. Description of the Related Art Conventionally, there is a monopulse system as one of automatic tracking systems for automatically directing an aerial to a target (for example, an artificial satellite), and there is a device of this type shown in FIG. In this system, a higher-order mode coupler provided after an antenna detects a higher-order mode according to a pointing error in an Az (azimuth) direction of the antenna and an El (elevation) direction orthogonal thereto, and generates an error signal. ,
The basic mode signal serving as the reference signal is sent to the apparatus shown in FIG. 4 separately. 4, reference numeral 1 denotes a reference signal input terminal, 2 denotes an error signal input terminal, 3 denotes a quadrature phase splitter, 4 denotes a first switch circuit, 5 denotes a two-phase PSK modulator, and 6 denotes a 0 to 2π variable phase shifter. , 7 are combiners, 8 is a clock signal generator, 9 is a frequency divider, 10 is a local signal generator, 11 is a frequency converter,
12 is a bandpass filter, 13 is an automatic gain control circuit,
14 is a variable amplifier or variable attenuator, 15 is a voltage detector, 16 is a capacitor for removing a DC component, 17 is a synchronous detector, 18 is a second switch circuit, 19 is a first low-pass filter, and 20 is a second low-pass filter. Second low pass filter, 21
Is an Az error signal output terminal, 22 is an El error signal output terminal, and 23 is a variable phase shifter control input terminal.

Next, the operation will be described. The communication signal or beacon signal wave input to the antenna is converted into a fundamental mode signal (reference signal) proportional to the received signal level by a higher-order mode coupler provided at a subsequent stage, and a higher-order signal generated according to the pointing error of the antenna. The reference signal is applied to a reference signal input terminal 1 and the error signal is applied to an error signal input terminal 2. At this time, for example, the antenna Az
When there is a pointing error only in the direction, the input phases of the reference signal and the error signal are in phase (no phase difference), and when there is a pointing error only in the El direction, the input phases of the reference signal and the error signal are orthogonal (phase difference). (π / 2). FIG. 5A shows the relationship between the reference signal and the error signal in vector representation. Next, the error signal is output to the quadrature phase splitter 3.
A long-period switching signal obtained by dividing the clock signal from the clock signal generator 8 into 1 / n by the frequency divider 9 by dividing into two in-phase components (0 radians) and quadrature components (π / 2 radians) Is alternately selected by the first switch circuit 4 and sent to the subsequent stage. Further, the two-phase PSK modulator (0
In the (-π modulator) 5, the short-period switching signal from the clock signal generator 8 performs 0-π modulation. This is shown in FIG. 5B in vector representation. The modulated error signal is sent to the combiner 7 via the 0-2π variable phase shifter 6, and is combined with the reference signal also input to the combiner 7 to become an AM modulated wave of the reference signal based on the error signal. . The state of the envelope of the AM modulated wave is shown in FIG. As shown in the figure, the envelope of the AM modulated wave changes at a single cycle timing from the clock signal generator 8 and at a long cycle timing divided by 1 / m by the frequency divider 9. The amplitude value of this envelope indicates the amplitude change of the vector sum of the error signal and the reference signal accompanying the 0-π modulation at each short cycle timing, and indicates the pointing error value in the Az direction and El direction alternately at the long cycle timing. ing. When the phase of the error signal with respect to the reference signal is shifted due to a temperature change or an input frequency fluctuation in each circuit section in the apparatus, the 0-2π variable phase shifter 6 controls the passing phase of the error signal system by an external control signal. And correct the phase difference with the reference signal. Combiner 7
The received signal synthesized and converted into a single channel is multiplied by the signal from the local signal generator 10 by the frequency converter 11 and converted into a low frequency band, and then the band-pass filter 12 outputs out-of-band noise. Is removed and the automatic gain control circuit 1 is removed.
Enter 3 In the automatic gain control circuit 13, a voltage value of a single-channel reception signal that changes with a change in the level of an input signal to the present apparatus is detected by a voltage detector 15, and a variable amplifier is set in accordance with the voltage value. By changing the gain (or attenuation) of the (or variable attenuator) 14, a constant output level is always maintained. A part of the output of the voltage detector 15 is sent to the synchronous detector 17 after the DC component is removed by the capacitor 16, and the switching signal from the clock signal generator 8 changes the amplitude component of the AM modulation signal. Is synchronously detected. Further, the second switch circuit 18 switches at the same timing as the first switch circuit 4 by the switching signal from the frequency divider 9,
The demodulated signal is distributed to input terminals of a first low-pass filter 19 and a second low-pass filter 20. In the first low-pass filter 19 and the second low-pass filter 20, the pulse-like Az-direction error signal and El-direction error signal distributed by the second switch circuit 18 are smoothed to a DC voltage value, and the Az error Signal output terminal 21 and El
The signal is transmitted from the error signal output terminal 22.

[0004]

The conventional tracking receiver is constructed as described above, but the variable phase shifter determines the phase relationship between the reference signal and the error signal due to changes in the ambient temperature of the device and fluctuations in the input frequency. Since a phase variable range from 0 to 2π is required for compensation, the path length of the phase delay unit is increased and the size of the device is increased, and Az and El due to amplitude characteristic fluctuation of a passing signal due to a difference in phase setting. There has been a problem that the detection sensitivity of the direction error signal changes, and as a result, the directivity of the antenna decreases.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problem, and corrects a phase difference between a reference signal in any one of 0 to 2π and an error signal by correcting an influence on a passing signal amplitude characteristic. It is an object of the present invention to obtain a tracking receiver which can reduce the number of signals and can be performed by a small circuit.

[0006]

A tracking receiver according to the present invention is provided with an inverter and a switch circuit for inverting the phases of respective signals at the outputs of a clock signal generator and a frequency divider, and receives an external signal. The switches are individually switched by the control signal, the clock signal and the frequency divider output signal are inverted or non-inverted output, the error signal 0-π / 2 selection switch is switched by the frequency divider output signal, and the clock signal is switched by the clock signal. This is to apply phase PSK modulation.

Also, a quadrature phase splitter, a switch circuit for selecting 0-π / 2, a 4-phase PSK instead of a 2-phase PSK modulator
The modulator is further provided with an exclusive-OR circuit for calculating an exclusive OR of the frequency divider output signal and the clock signal of the above-described means, and performs four-phase PSK modulation with the exclusive-OR circuit output signal and the clock signal. Multiply.

An n-bit digital phase shifter instead of a quadrature phase splitter, a switch circuit for selecting 0-π / 2, a two-phase PSK modulator, and a variable phase shifter of 0 to 2π. In the same way as above, an inverter and a switch circuit for inverting the phase of each signal are provided at the output of the clock signal generator and the frequency divider, and the switches are individually switched by an external control signal, and the clock signal and the frequency divider are divided. Output signal is inverted or non-inverted output.
The phase set by the π phase shifter is set to 0- by the frequency divider output signal.
Change the set phase of the π / 2 phase shifter.

[0009]

In the tracking receiver according to the present invention, 0-π /
2 selection switch circuit switching timing and 2 phase PS
The phase of the modulation timing signal of the K modulator is switched by an external control signal, and the passing phase of the error signal is changed from 0 to 3π / 2 in π / 2 steps.

In another embodiment, the phase of the modulation timing signal of the four-phase PSK modulator is switched by an external control signal, and the passing phase of the error signal is changed from 0 to 3π / 2 in π / 2 steps.

Further, in another embodiment, the setting of the phase shifter section corresponding to each bit of the n-bit digital variable phase shifter is switched by an external control signal, and 0 to (2 ⁿ -1) π / 2.
At the same time, 4-phase PSK modulation is applied up to ^(n-1) radians in π / 2 ^(n-1) steps.

[0012]

【Example】

Embodiment 1 Hereinafter, an embodiment of the present invention will be described. In FIG. 1, reference numerals 1 to 5 and 7 to 23 are exactly the same as those in the above-mentioned conventional example. 24 is a first inverter, 25 is a second inverter, 26 is a third switch circuit, 27 is a fourth switch circuit, 28 is a 0-π / 2 variable phase shifter, and 29 is a third switch control signal. An input terminal 30 is a fourth switch control signal input terminal.

In the tracking receiving apparatus configured as described above, first, the error signal input from the error signal input terminal 2 is converted into the in-phase component (0
Radian) and a quadrature component (π / 2 radian), and the first switch circuit 4 switches the period from the signal from the clock signal generator 8 to 1 / m by the frequency divider 9 for long period switching. It is alternately selected by a signal and sent to the subsequent stage. Further, in the two-phase PSK modulator (0-π modulator) 5, phase modulation is performed by the short-period switching signal from the clock signal generator 8. In the present invention, part of the output of the frequency divider 9 is input to the first inverter 24, the phase of which is inverted, and the third switch circuit 26 together with the non-inverted signal.
Sent to The third switch circuit 26 switches the switches according to the signal from the third switch control signal input terminal 29 and sends the inverted or non-inverted frequency divider 9 output signal to the first switch circuit 4. . A part of the output of the clock signal generator 8 is input to the second inverter 25, the phase is inverted, and sent to the fourth switch circuit 27 together with the non-inverted clock signal. The fourth switch circuit 27 switches the switches according to the signal from the fourth switch control signal input terminal 30 and sends the inverted or non-inverted clock signal generator 8 output signal to the two-phase PSK modulator 5. . The modulated error signal is sent to the combiner 7 via the variable phase shifter 28, and is combined with the reference signal also input to the combiner 7 to form an AM modulated wave of the reference signal based on the error signal. As in the conventional example, the AM-modulated wave has a short-period timing indicating a vector sum of an error signal amplitude change accompanying the 0-π modulation and a reference signal, and a long-period timing alternately indicates a pointing error value in the Az direction and the El direction. Therefore, the four AM modulation envelope characteristics shown in FIGS. 6A to 6D can be obtained by a combination of switching of the third switch circuit 26 and the fourth switch circuit 27 in the present embodiment. . Since this is equivalent to the characteristic in the case where the phase setting in the 0-2π variable phase shifter 6 in the conventional example is changed from 0 to 2π every 2 / π, in the present embodiment, the variable phase shifter 28 If the phase variable range is 0 to 2 / π, when the phase of the error signal with respect to the reference signal is shifted due to temperature change or input frequency change in each circuit unit in the device,
Phase setting of variable phase shifter 28 and third switch circuit 2
By changing the settings of the sixth and fourth switch circuits 27, 0
The phase difference from the reference signal can be corrected in the entire phase range from to 2π. Subsequent operations in each part of the present apparatus are exactly the same as those in the conventional example, and A
The z-direction error signal and the El-direction error signal are output from an Az error signal output terminal 21 and an El error signal output terminal 22, respectively.

Embodiment 2 In Embodiment 1 described above, the quadrature phase splitter 3 uses the phase 0 and π / 2
And the output is further converted to 0-π by a two-phase PSK modulator.
The phase of the modulated error signal is changed in π / 2 steps by an external control signal. However, the same operation is performed by changing the modulation signal pattern by an external control signal using a 4-phase PSK modulator. Can be expected. In FIG. 2, 1-3, 7
-30 are the same as or equivalent to the first embodiment. 31
Is a four-phase PSK modulator, and 32 is its component 0
A -π modulation section, 33 is a second 0-π modulation section, 34 is an in-phase multiplexer, and 35 is an exclusive-OR circuit.

In the embodiment 2 shown in FIG. 2, the error signal input from the error signal input terminal 2 is a four-phase PSK modulator 31.
Is modulated by the signals from the clock signal generator 8 and the frequency divider 9, the frequency divider output signal passing through the third switch circuit 26 and the fourth switch circuit 2
Exclusive part of the clock signal passed through
The output signal ORed by the OR circuit 35 is modulated by the first 0-π modulation unit 32, and the second 0-π modulation unit 3 is modulated by the clock signal passed through the fourth switch circuit 27.
3, the third switch circuit 26 and the fourth switch circuit 27 are switched so that the four-phase P
The output phase of the SK modulator 31 can be changed in π / 2 steps. However, in the first embodiment, the phase of the error signal input to the 0 to π / 2 variable phase shifter 28 is 0, π /
2, π, or 3π / 2, but in the second embodiment,
Since the phase PSK modulator 31 is used, π / 4, 3π /
Either 4,5π / 4 or 7π / 4. Therefore, in the second embodiment, the passing phase of the error signal is π with respect to the reference signal.
Although the value becomes / 4 offset, the operation is the same as that of the first embodiment by performing the phase correction in advance by the 0 to π / 2 variable phase shifter 28.

Embodiment 3 In Embodiment 1 described above, the quadrature phase splitter 3 uses the phases 0 and π.
/ 2, and the output is further reduced to 0 by a two-phase PSK modulator.
The phase of the -π-modulated error signal is changed by π /
In the second embodiment, the modulator output phase is changed by an external control signal using a four-phase PSK modulator. In the second embodiment, the above-described circuit unit and 0 to π / 2 are used.
An n-bit digital variable phase shifter controlled by n switching signals is provided instead of the variable phase shifter, and the 0-π phase shifter performs 0-π modulation and the 0-π / 2 phase shifter. The same operation can be expected by switching the Az and E1 error signals. FIG.
Are the same as in the first embodiment. Numeral 36 denotes an n-bit digital variable phase shifter in the case of n = 5 in this embodiment. 37-41
Is a bit phase shifter of the n-bit digital variable phase shifter, 37 is a 0-π phase shifter, and 38 is 0-π /
2 phase shifter section, 39 is 0-π / 4 phase shifter section, 40 is 0-π
Reference numeral 41 denotes a 0-π / 16 phase shifter unit. Reference numeral 42 denotes an n-bit phase shifter control signal input terminal. In this embodiment, a case of 5-bit parallel input is shown.

In the third embodiment shown in FIG. 3, the error signal input from the error signal input terminal 2 is input to the n-bit digital variable phase shifter 36, and the passing phase is 0 to (2 ⁿ -1) π / 2.
^(n-1) radian to [pi / 2 ^(n-1) is set at a resolution of radians. FIG. 3 shows n = 5, and the pass phase is set in a range of 0 to 31π / 16 radians in π / 16 radian steps. Here, the upper 2 bits of the n-bit digital variable phase shifter 36, that is, 0-π
The phase shifter unit 37 and the 0-π / 2 phase shifter unit 38 are switched by the clock signal and the frequency divider output signal to perform 0-π modulation and Az / El direction error signal switching. The clock signal that has passed through the fourth switch circuit 27 is sent to the 0-π phase shifter 37, and performs 0-π modulation. The frequency divider output signal via the third switch circuit 26 is 0
The signal is sent to the -π / 2 phase shifter unit 38 to switch the phase over a long period. Upper 2 bits of the parallel control signal from the n-bit phase shifter control signal input terminal 42 (42-a and 42-b)
Are sent to the third switch circuit 26 and the fourth switch circuit 27, respectively, to select each switch and to set the passing phase to 0, π
/ 2, π, or 3π / 2, the operation is the same as in the first and second embodiments. The other lower bits are directly input to each phase shifter unit, and by performing a fine phase shift setting of π / 2 or less, correction is made so that the passing phase of the error signal system matches the phase of the reference signal.

[0018]

Since the present invention is configured as described above, it has the following effects.

In the first and second embodiments, the 0-π modulation timing and the Az / El error signal switching timing can be set from 0 to 3π / 2 in π / 2 steps by an external control signal. Since the variable phase shifter of 0 to 2π is a variable phase shifter of 0 to π / 2, the variable range can be reduced to ４ and the device can be reduced. In addition, the variable range of the variable phase shifter is narrow, so that the fluctuation of the amplitude characteristic is reduced. Az
And the detection sensitivity of the El error signal is stabilized, and the pointing accuracy of the antenna can be maintained.

Further, in the third embodiment, the variable phase shifter is an n-bit digital type, and the amount of the passing phase of the error signal is varied. On the other hand, 0-π modulation and 0-π / 2 Az, E
Since the switching of the 1 error signal is performed, the quadrature phase splitter, the first switch circuit and the two-phase PSK modulator in the conventional example become unnecessary, so that the device can be reduced in the same manner as the effect of the above item 17, and Because there is no fluctuation, the amplitude fluctuation of the device is reduced, the detection sensitivity of the Az and El error signals is stabilized, and the pointing accuracy of the antenna can be maintained.

[Brief description of the drawings]

FIG. 1 is a circuit block diagram showing a first embodiment of the present invention.

FIG. 2 is a circuit block diagram showing Embodiment 2 of the present invention.

FIG. 3 is a circuit block diagram showing Embodiment 3 of the present invention.

FIG. 4 is a circuit block diagram illustrating a conventional tracking receiver.

FIG. 5 is a signal vector and a signal waveform diagram that supplement the description of the operation of the conventional tracking receiver.

FIG. 6 is a signal waveform diagram that supplements the description of the operation of the present invention.

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 reference signal input terminal 2 error signal input terminal 3 quadrature phase splitter 4 first switch circuit 5 two-phase PSK modulator 7 in-phase multiplexer 8 clock signal generator 9 frequency divider 10 local signal generator 11 frequency Converter 12 Band-pass filter 13 Automatic gain control circuit 14 Variable amplifier (or variable attenuator) 15 Voltage detector 16 Capacitor 17 Synchronous detector 18 Second switch circuit 19 First low-pass filter 20 Second low-pass filter 21 Az Direction angle error signal output terminal 22 El direction angle error signal output terminal 23 Variable phase shifter control signal input terminal 24 First inverter 25 Second inverter 26 Third switch circuit 27 Fourth switch circuit 28 0-π / 2 variable phase shifter 29 Third switch switching signal input terminal 30 Third switch switching signal Input terminal 31 Four-phase PSK modulator 32 First 0-π modulator 33 First 0-π modulator 34 Second in-phase multiplexer frequency converter 35 Exclusive or circuit 36 n-bit digital variable phase shifter 37 0-π phase shifter section 38 0-π / 2 phase shifter section 39 0-π / 4 phase shifter section 40 0-π / 8 phase shifter section 41 0-π / 16 phase shifter section 42 n Bit phase shifter control signal input terminal

Claims (3)

(57) [Claims] 1. An antenna receives a radio wave from a predetermined direction as a reference signal and an error signal, and extracts a phase difference and an amplitude difference of the error signal with respect to the reference signal to generate an angle error signal, thereby obtaining a pointing direction of the antenna. A quadrature phase splitter for dividing the error signal into 0-π / 2 phases, and a switch circuit for alternately selecting the error signal split into 0-π / 2 phases. A two-phase PSK modulator that performs 0-π modulation on the selected signal, and sets a passing phase of the 0-π modulated error signal to 0.
0 to π / 2 variable phase shifter that changes over a range from π / 2 to π / 2, a clock signal generator that generates a modulation signal for the 0-π modulation, and a part of the output of the clock signal generator. A frequency divider that circulates, and sets the passing phase of the 0 to π / 2 variable phase shifter and selects inversion / non-inversion output of the clock signal generator and the frequency divider from outside. A tracking receiver, wherein the tracking signal is selected by a control signal, and the combined phase of the 0-π modulated error signal and the reference signal is matched. 2. A quadrature phase splitter for dividing an error signal into 0-π / 2 phases, and a 0-π / 2 splitter for each of the split error signals.
a pair of 0-π modulation units for performing π modulation, and the pair of 0-π
A four-phase PSK modulator comprising an in-phase multiplexer for multiplexing an output signal of the modulation section in the same phase. On the other hand, a clock signal in which one of the 0-π modulators has an inverted / non-inverted output selected by an external control signal. On the other hand, the generator output signal is subjected to 0-π modulation, and on the other hand, an exclusive OR signal of the clock signal generator output signal and a frequency divider output signal whose inverted / non-inverted output is selected by an external control signal. The error signal is subjected to four-phase PSK modulation by performing 0-π modulation in step (1), and the phase of the modulated error signal and the reference signal are matched by a 0-π / 2 variable phase shifter. The tracking receiver according to claim 1. 3. An antenna receives a radio wave from a predetermined direction as a reference signal and an error signal, and extracts a phase difference and an amplitude difference of the error signal with respect to the reference signal to generate an angle error signal, thereby obtaining a pointing direction of the antenna. And an n-bit digital variable phase shifter for changing the passing phase of the angle error signal from 0 to 2π, and setting of the 0-π phase shift bit of the n-bit digital variable phase shifter. A clock signal generator for switching in a short cycle; and a frequency divider for generating a signal for switching a setting of 0-π / 2 phase shift bits in a long cycle. The clock signal is generated by an external switching signal. The phase of the output signal of the generator and the phase of the output signal of the frequency divider are selected to be inverted / non-inverted, respectively. Subjected to 0-[pi modulated in phase bits,
A tracking receiver, wherein lower-order bits below 0-π / 4 phase-shifted bits are switched by an external signal to arbitrarily set a passing phase.