JP2007067692A - Demodulator and receiving system - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a demodulator capable of rapidly acquiring information from an input signal such as a digital modulation signal. <P>SOLUTION: An I/Q signal corresponding to a unit frame is inputted to an A/D converter 20. The A/D converter 20 discretizes the I/Q signal and inputs it to a division frame storage 44 and a phase difference estimator 23 as a discrete I/Q signal. The phase difference estimator 23 calculates a phase difference Δθ being a difference between the phase of the signal to express a symbol frequency, which is extracted from the discrete I/Q signal, and the phase of a reference signal on the basis of the division frame in which the unit frame is divided. The division frame storage 44 stores the discrete I/Q signal corresponding to the division frame and holds it. An I/Q signal reproducer 34 outputs a reproduction I/Q signal which is synchronized with a symbol period, based on the discrete I/Q signal which is outputted from the division frame storage 44 and the phase difference Δθ. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to an apparatus for detecting timing indicating information based on an input signal, and obtaining and outputting a value indicated by the timing from the input signal.

  Digital modulation signals are widely used in digital wireless communications. The digital modulation signal is obtained by associating a symbol code with a digital code consisting of one bit or a plurality of bits as a unit with a physical quantity such as a phase of a carrier wave, a change amount thereof, and an amplitude at a predetermined time interval. Various digital modulation signal schemes are conceivable depending on the physical quantity of the carrier to which the symbol code is associated. For example, a PSK modulation scheme in which the symbol code is associated with the phase of the carrier, and the symbol code is changed to the amplitude and phase of the carrier. There are associated QAM modulation schemes and the like.

  The modulation component signal of the digital modulation signal is represented by a two-channel signal of an in-phase component signal (hereinafter referred to as I signal) and a quadrature component signal (hereinafter referred to as Q signal). Hereinafter, these two-channel signals are referred to as I / Q signals.

  In order to extract a symbol code from an I / Q signal, it is necessary to extract a timing (symbol period) in which the symbol code is associated with at least one of the amplitude and phase of a carrier from the I signal and the Q signal. A point where a value is extracted for each symbol period in the time waveform of the I / Q signal is referred to as a symbol point. It can be said that the symbol point is a point on the time waveform that appears at the timing when the information is associated with the I / Q signal.

  FIG. 4 shows a configuration example of a digital modulation signal handled in digital wireless communication. The digital modulation signal is composed of a plurality of unit frames 50 that are continuous in time series. The receiving apparatus receives a unit frame 50 allocated to itself among a plurality of unit frames 50 connected in time series, extracts a symbol code, and performs digital demodulation.

  FIG. 5 shows the configuration of the receiving device 5 in the prior art. The receiving device 5 includes an antenna 10, a radio receiving unit 12, a quadrature detection unit 14, a storage type synchronous demodulation unit 70, a code detection unit 36, a frame detection unit 38, a control unit 40, and a clock signal generation unit 18. . The receiving device 5 demodulates the digital modulation signal corresponding to the unit frame 50 allocated to itself under the control of the control unit 40. Since the receiving device 5 operates independently of the transmitting device that transmits the digital modulation signal, the symbol period of the digital modulation signal and the clock signal CK generated by the clock signal generation unit 18 to extract the symbol code are extracted. It is not synchronized with the clock period. Therefore, the receiving device 5 can extract a digital signal from a digital modulation signal by including a storage type synchronous demodulation unit 70 that reproduces an I / Q signal that can obtain a symbol code synchronized with a symbol period. It is said. Hereinafter, a specific operation of the receiving device 5 will be described.

  The radio reception unit 12 performs high frequency amplification, frequency conversion to an intermediate frequency, and intermediate frequency amplification on the digital modulation signal received via the antenna 10 and inputs the result to the quadrature detection unit 14. The quadrature detection unit 14 extracts an I / Q signal from the digital modulation signal corresponding to the input unit frame 50 and inputs the I / Q signal to the storage type synchronous demodulation unit 70.

  The storage-type synchronous demodulator 70 includes an A / D converter 20, a phase difference estimator 72, a unit frame storage unit 80, and an I / Q signal reproduction unit 82. The I / Q signal input to the storage type synchronous demodulator 70 is input to the A / D converter 20. The A / D conversion unit 20 discretizes each of the I signal and the Q signal according to the period of the clock signal CK output from the clock signal generation unit 18, and the phase difference estimation unit 72 and the unit frame storage unit as a discretized I / Q signal Enter 80. Assuming that the period of the clock signal CK is 1 / L of the symbol period (L is an integer of 2 or more), the time interval for discretization is the time interval obtained by dividing the symbol period of the I / Q signal by L. It becomes.

  As described above, since the symbol period of the digital modulation signal and the period of the clock signal CK are not synchronized, the phase obtained from the symbol point of the I / Q signal and the discretization point (represented on the amplitude time plane). Difference between the phase of the reference signal obtained from the discretized point.

FIG. 6 shows this situation. Point e ₀ to point e _N-1 in FIG. 6A is a discretized square sum signal that is the sum of the square of the discretized I signal and the square of the discretized Q signal, and curve A is It represents a square sum signal that has not been discretized. Points E _{0 to} E _J-1 on the curve A represent symbol points of the I / Q signal. Generally, since band limitation is applied to an I / Q signal, the symbol point does not coincide with the point at which the maximum value of the square sum signal appears. Here, for convenience of explanation, the case where the band limitation is not applied to the I / Q signal is considered, and the symbol points E _{0 to} E _J-1 are assumed to coincide with the point where the maximum value of the curve A appears. Curve B in FIG. 6B represents the reference cosine wave signal. Here, the reference cosine wave signal is a cosine wave signal for extracting a symbol frequency component from the square sum signal, and the first appearing discretization point of the I / Q signal corresponding to the unit frame 50 is the phase. Set to zero. A curve D in FIG. 6C represents a reference sine wave signal. Here, the reference sine wave signal is a sine wave signal for extracting a symbol frequency component from the sum of squares signal, and the first appearing discretization point of the I / Q signal corresponding to the unit frame 50 is a phase. Of zero.

In FIG. 6, the time t _Aj at which the symbol point appears (j is an integer from 0 to J−1, and J is the number of symbol points included in the unit frame 50. The number of discretization points included in the unit frame 50. If N is N, there is a relationship N = LJ.) And a time t _{Bj at} which the maximum value of the curve B appears is a time difference Δt = t _Aj −t _Bj . When this is converted into a phase based on the symbol period T, a phase difference Δθ = 2πΔt / T is obtained. Since the phase difference Δθ is based on the phase of the point where the maximum value of the reference cosine wave signal appears, Δθ is a positive value in the case of FIG. It can be said that the phase difference Δθ is a phase difference between the signal representing the symbol frequency component of the I / Q signal and the reference signal defined by the discretization point.

  The phase difference estimation unit 72 includes a square sum calculation unit 74, a cosine component extraction unit 76a, a sine component extraction unit 76b, and an arctangent calculation unit 78. The phase difference estimation unit 72 is arranged according to the following processes (i) to (iii). The phase difference Δθ is calculated. (I) A square sum signal is calculated. (Ii) A reference cosine wave component C and a reference sine wave component S included in the square sum signal are calculated. (Iii) The phase difference Δθ is calculated based on the arc tangent of the ratio of the reference sine wave component S to the reference cosine wave component C.

A specific process of the phase difference estimation unit 72 for performing the processes (i) to (iii) will be described. The sum of squares calculation unit 74 calculates a discretized square sum signal by calculating and adding the square of the discretized I signal and the square of the discretized Q signal. The discretized value u _k of the discretized square sum signal is expressed by the following equation (1) by the discretized value I _k of the I signal forming the discretized I / Q signal and the discretized value Q _k of the Q signal. It is expressed in
(Equation 1) u _k = I _k ² + Q _k ² (1)
However, k is an integer from 0 to N−1, and N represents the number of discretization points included in the unit frame 50.

The cosine component extraction unit 76a performs Fourier transform on the reference cosine wave component expressed by the following equation (2) with respect to the squared sum signal.
(Expression 2) C = Σu _k cos (2πkτ / T) (2)
Here, Σ means that cumulative addition from k = 0 to k = N−1 is performed. T is a predetermined symbol period. τ is a discretization time interval and has a relationship of τ = T / L. Further, cos (2πkτ / T) corresponds to the signal represented by the curve B shown in FIG. 6B, and means a discretized value of the reference cosine wave signal.

The sine component extraction unit 76b performs Fourier transform on the reference sine wave component expressed by the following equation (3) for the squared sum signal.
(Expression 3) S = Σu _k sin (2πkτ / T) (3)
Here, Σ means that cumulative addition from k = 0 to k = N−1 is performed. sin (2πkτ / T) corresponds to the signal represented by the curve D shown in FIG. 6C, and means a discretized value of the reference sine wave signal.

The arctangent calculation unit 78 calculates the phase difference Δθ according to the following equation (4-1) or (4-2) from the calculation results of the cosine component extraction unit 76a and the sine component extraction unit 76b. The phase difference Δθ can take a value from −π / 2 to 3π / 2.
(Equation 4-1) When C is positive and S is positive, or when C is positive and S is negative, Δθ = arctan (S / C) (4-1)
(Expression 4-2) When C is negative and S is positive, or when C is negative and S is negative, Δθ = arctan (S / C) + π (4-2)
Here, arctan assumes a main value from −π / 2 to π / 2.

  The phase difference estimation unit 72 inputs the phase difference Δθ calculated by the arctangent calculation unit 78 to the I / Q signal reproduction unit 82. As can be seen from the equations (2) and (3), in order to calculate the phase difference Δθ, it is necessary to perform cumulative addition from k = 0 to k = N−1. Therefore, at least the time for performing cumulative addition, that is, the time length of the unit frame 50 is required until the discretized I / Q signal is input to the phase difference estimation unit 72 and the phase difference Δθ is calculated.

  While the phase difference estimation unit 72 calculates the phase difference Δθ, the unit frame storage unit 80 stores and holds the value of the discretized I / Q signal. The unit frame storage unit 80 inputs the phase difference Δθ to the I / Q signal reproduction unit 82 and inputs the stored discretized I / Q signal to the I / Q signal reproduction unit 82.

  Based on the phase difference Δθ and the discretized I / Q signal, the I / Q signal reproduction unit 82 performs an interpolation operation for calculating a value at a symbol point for each of the I signal and the Q signal, and performs the I / Q signal reproduction for each symbol period T. An operation result for each of the signal and the Q signal is output. As shown in FIG. 6, there is a phase difference of Δθ between the signal of the symbol frequency component included in the square sum signal and the reference cosine wave signal defined by the discretization point. Therefore, any of the discretized values of the discretized I / Q signal cannot be extracted as the value indicated by the symbol point, and the value at a point that is separated from the discretized point by a time of Δt = TΔθ / (2π). Calculated by interpolation calculation.

  In the I / Q signal reproducing unit 82, one interpolation value is output for every L discretized values. By such processing, a reproduction I / Q signal indicating a value corresponding to a value given on the transmission device side is generated every time Lτ, that is, every symbol period T. The I / Q signal reproduction unit 82 inputs the reproduction I / Q signal to the frame detection unit 38 and the code detection unit 36.

  The frame detection unit 38 calculates a correlation value between each waveform change pattern of the reproduction I signal and the reproduction Q signal and a waveform change pattern stored in advance, and inputs the correlation value to the control unit 40. Based on the correlation value, the control unit 40 determines whether or not the received unit frame 50 is assigned to the receiving device 5, and is assigned based on the determination result and the clock signal CK. Each component of the receiving device 5 is controlled to demodulate only the unit frame 50 that is present.

  The code detector 36 obtains a symbol code from the reproduced I / Q signal, and outputs a time-sequential symbol code as a digital signal.

  With such a configuration, the receiving device 5 can extract a digital signal from the digital modulation signal even when the symbol period of the digital modulation signal and the clock period of the clock signal CK are not synchronized. It becomes.

  A configuration similar to that of the storage-type synchronous demodulator 70 described here is disclosed in the following document.

Yoichi Matsumoto, Masahiro Morikura, Shuzo Kato, “Burst Mode Fully Digitized High-speed Clock Recovery Circuit-Storage Clock Recovery Method”, IEICE Transactions B-II Vol. J75-B-II No. 6 pp. 354-362 May 1992

  In the receiving apparatus 5 according to the conventional technique, the unit frame storage unit 80 stores the value of the discretized I / Q signal and waits while the phase difference estimation unit 72 calculates the phase difference Δθ. This assumes that the phase difference Δθ varies for each unit frame 50 and applies the phase difference Δθ calculated based on the discretized I / Q signal itself to generate the reproduction I / Q signal. This is for generating an I / Q signal. Therefore, at least the time length of the unit frame 50 is required from the input of the digital modulation signal to the storage-type synchronous demodulator 70 until the reproduction I / Q signal is output. For this reason, the receiving device 5 has a problem that processing based on the digital signal extracted from the digital modulation signal cannot be performed immediately after receiving the digital modulation signal corresponding to the unit frame 50.

  The present invention has been made for such a problem, and provides a demodulator capable of quickly acquiring information from an input signal such as a digital modulation signal.

  The present invention relates to a discretization unit that discretizes an input signal and outputs the discretized input signal, and a value indicated by the input signal at an information timing that is a timing at which the input signal indicates information, based on the discretized input signal. A demodulating device comprising: a demodulating unit comprising: a demodulating unit including: a discretizing unit that discretizes an input signal having a finite time length and outputs the input signal as a finite discretized input signal; A reference phase is set based on the timing at which the partially discretized input signal, which is a part of the finite-length discretized input signal, is discretized by the discretizer, and the phase obtained from the information timing of the partially discretized input signal and the reference phase A phase difference calculating means for calculating a phase difference that is a difference between the first and second input signals, and an input signal reproducing means for calculating a value at an information timing of the partially discretized input signal based on the phase difference. Characterized in that it obtain.

  In the demodulator according to the present invention, it is preferable that the demodulator includes a digital filter that determines a tap coefficient based on the phase difference.

  The present invention also provides a discretization unit that discretizes an input signal and outputs the discretized input signal, a value indicated by the input signal at an information timing at which the input signal indicates information, and the discretized input signal. And a demodulator for obtaining and outputting based on the timing at which the first input signal is discretized in the discretizer, and the demodulator sets the reference phase. Phase difference calculating means for calculating a phase difference, which is a difference between a phase obtained from information timing of one input signal and the reference phase, based on a discretized signal of the first input signal, and based on the phase difference And input signal reproducing means for calculating a value at the information timing of the second input signal inputted after the first input signal.

  In the demodulator according to the present invention, it is preferable that the demodulator includes a digital filter that determines a tap coefficient based on the phase difference.

  In the demodulator according to the present invention, it is preferable that the first input signal and the second input signal are signals included in the same unit frame.

  In the receiving system according to the present invention, comprising: a radio reception unit that receives an orthogonal modulation signal; and a digital demodulation unit that extracts a digital signal from a signal output from the radio reception unit. It is preferable that the demodulator according to the invention is provided and a digital signal is extracted from a signal output from the demodulator.

  According to the present invention, the phase difference is calculated based on the partially discretized input signal that is a part of the finite-length discretized input signal, and based on this, the value at the information timing of the partially discretized input signal is calculated. As a result, processing can be performed more quickly than in the case where the value at the information timing of the finite-length discretized input signal is calculated based on all the finite-length discretized input signals.

  Also, according to the present invention, the value at the information timing of the second input signal is calculated based on the phase difference calculated based on the first input signal. When calculating the information timing of the second input signal, the phase difference calculated based on the first input signal is applied, so that the processing time can be reduced.

  Further, according to the present invention, it is possible to realize a receiving apparatus that can quickly acquire information from a received signal.

  FIG. 1 shows the configuration of a receiving apparatus 1 according to the first embodiment of the present invention. The receiving apparatus 1 includes an antenna 10, a radio receiving unit 12, an orthogonal detection unit 14, a divided storage type synchronous demodulation unit 17, a code detection unit 36, a frame detection unit 38, a control unit 40, and a clock signal generation unit 18. The

  The radio reception unit 12 performs high frequency amplification, frequency conversion to an intermediate frequency, and intermediate frequency amplification on the digital modulation signal received via the antenna 10 and inputs the result to the quadrature detection unit 14. The quadrature detection unit 14 extracts an I / Q signal from the digital modulation signal and inputs the I / Q signal to the divided storage type synchronous demodulation unit 17.

  The divided memory type synchronous demodulator 17 includes an A / D converter 20, a phase difference estimator 23, a divided frame memory 44, and an I / Q signal regenerator 34.

  The I / Q signal input to the divided storage type synchronous demodulator 17 is input to the A / D converter 20. The A / D conversion unit 20 discretizes each of the I signal and the Q signal at the period of the clock signal CK output from the clock signal generation unit 18, and the phase difference estimation unit 23 and the divided frame storage unit as a discretized I / Q signal 44. The A / D converter 20 is provided with an interpolating unit that discretizes the I / Q signal in a time shorter than the cycle of the clock signal CK, thereby discretizing the discretized at a time interval shorter than the cycle of the clock signal CK. A configuration for outputting an I / Q signal is also possible. As the interpolation means, it is preferable to apply an intermediate value interpolator described in Non-Patent Document 1.

The phase difference estimator 23 includes a square sum calculator 24, a cosine component extractor 26a, a sine component extractor 26b, and an arctangent calculator 28. 5 calculates the phase difference Δθ based on the unit frame 50, whereas the phase difference estimation unit 23 calculates the phase difference Δθ based on the divided frame 50a that is a signal obtained by dividing the unit frame 50. calculate. FIG. 2 shows the relationship between the unit frame 50 and the divided frame 50a. The unit frame 50 including N discretization points includes a divided frame 50a including M discretization points. The divided frame 50a that appears at the end of the unit frame 50 includes M _E discretization points because N includes M more discretization points. The first discretization point of each divided frame 50 a appears every M times from the first discretization point of the unit frame 50. The number M of discretization points included in the divided frame 50a can be arbitrarily set in a range less than the number N of discretization points included in the unit frame 50. However, from the viewpoint of accuracy in extracting the symbol clock period, it is desirable to set M so that Mτ is an integral multiple of the symbol period T.

  Divided frame information R indicating the timing at which reception of the divided frame 50 a is started from the control unit 40 is input to the phase difference estimation unit 23. When the divided frame information R is input, the phase difference estimation unit 23 starts calculating the phase difference Δθ for the divided frame 50a.

The sum of squares calculation unit 24 calculates a discretized square sum signal by calculating and adding the square of the discretized I signal and the square of the discretized Q signal. The discretized value u _p of the discretized square sum signal is expressed by the following equation (5) according to the discretized value I _p of the I signal and the discretized value Q _p of the Q signal. It is expressed in
(Expression 5) u _p = I _p ² + Q _p ² (5)
However, p is an integer from q to q + M−1 (up to p = q + M _E −1 for the divided frame 50a that appears at the end of the unit frame 50). q represents the number of the first appearing discretization point included in the divided frame 50a, and M represents the number of discretization points included in the divided frame 50a.

The cosine component extraction unit 26a performs a Fourier transform on the reference cosine wave component expressed by the following equation (6) on the digitized square sum signal.
(Number _{6) C = Σu p cos (} 2πpτ / T) (6)
Here, Σ means that cumulative addition from p = q to p = q + M−1 (up to p = q + M _E −1 for the divided frame 50a appearing at the end of the unit frame 50) is performed. τ is a discretization time interval, and T is a predetermined symbol period. Further, cos (2πpτ / T) corresponds to the signal represented by the curve B shown in FIG. 6B, and means a discretized value of the reference cosine wave signal.

The sine component extraction unit 26b performs Fourier transform on the reference sine wave component expressed by the following equation (7) for the squared sum signal.
(Number _{7) S = Σu p sin (} 2πpτ / T) (7)
Here, Σ means that cumulative addition from p = q to p = q + M−1 (up to p = q + M _E −1 for the divided frame 50a appearing at the end of the unit frame 50) is performed. sin (2πpτ / T) corresponds to the signal represented by the curve D shown in FIG. 6C, and means a discretized value of the reference sine wave signal.

The arc tangent calculation unit 28 calculates the phase difference Δθ from the calculation results of the cosine component extraction unit 26a and the sine component extraction unit 26b according to the following equation (8-1) or (8-2).
(Expression 8-1) When C is positive and S is positive, or when C is positive and S is negative, Δθ = arctan (S / C) (8-1)
(Equation 8-2) When C is negative and S is positive, or when C is negative and S is negative, Δθ = arctan (S / C) + π (8-2)
Here, arctan assumes a main value from −π / 2 to π / 2.

The phase difference estimation unit 23 inputs the phase difference Δθ calculated by the arctangent calculation unit 28 to the I / Q signal reproduction unit 34. (6) and (7) As can be seen from the equation, for the last occurrence division frame 50a (unit frame 50 from p = q to p = q + M-1 in order to calculate a phase difference Δθ p = q + M _E Up to -1). Therefore, at least the time for performing cumulative addition, that is, the time length of the divided frame 50a is required before the discretized I / Q signal is input to the phase difference estimation unit 23 and the phase difference Δθ is calculated.

  While the phase difference estimation unit 23 calculates the phase difference Δθ, the divided frame storage unit 44 stores and holds the value of the discretized I / Q signal. In the divided frame storage unit 44, the phase difference Δθ is input to the I / Q signal reproduction unit 34 and the discretized I / Q signal is input to the I / Q signal reproduction unit 34.

  Based on the phase difference Δθ and the discretized I / Q signal, the I / Q signal reproduction unit 34 performs an interpolation operation for calculating a value at a symbol point for each of the I signal and the Q signal, and performs the I / Q signal reproduction for each symbol period T. An operation result for each of the signal and the Q signal is output. The I / Q signal reproduction unit 34 is preferably configured by a digital filter whose characteristics are determined by tap coefficients.

  The tap coefficient of the digital filter is determined based on the phase difference Δθ. As described above, the phase difference Δθ represents the phase difference between the signal representing the symbol frequency component of the I / Q signal and the reference signal defined by the discretization point. In the reference signal, since the first appearing discretization point is the zero point of the phase, there is a symbol point at a time separated from the first appearing discretization point by the phase difference Δθ.

The I / Q signal reproduction unit 34 makes P (P is an integer of 2 or more) discretization points e _{i to} e _{i +} that contribute to the interpolation calculation based on the discretization time interval τ and the phase difference Δθ. _The nearest discretization point that is present closest to the symbol point is selected from _P-1 , and the time difference δt between the neighboring discretization point and the symbol point is calculated.

Next, the I / Q signal reproduction unit 34 calculates the time t _{i to} t _{i + P-1} to the neighboring discretization point for each of the discretization points e _{i to} e _{i + P-1} to be contributed to the interpolation calculation. calculate. The time from the discretized points e _{i to} e _{i + P-1} to the symbol point to be contributed to the interpolation calculation is t _i + δt to t _{i + P-1} + δt, respectively.

The I / Q signal reproducing unit 34 calculates tap coefficients W0 to WP-1 based on the time t _i + δt to t _{i + P-1} + δt according to the formula of the interpolation calculation. Here, the tap coefficients W0 to WP-1 represent the interpolation values at the symbol points by a convolution operation such as W0e _i + W1e _{i + 1} +... + WP-1e _{i + P−1} .

  That is, the I / Q signal reproduction unit 34 inputs the tap coefficients W0 to WP-1 determined by referring to the phase difference Δθ output from the phase difference estimation unit 23 to the digital filter provided therein, and the tap coefficients W0 to WP. The interpolated value at the symbol point is calculated by performing a convolution operation with −1 and the input discrete I / Q signal.

  The I / Q signal reproducing unit 34 outputs one interpolation value for every L discrete values by counting the pulses of the clock signal CK. Since the time interval for outputting the interpolation value depends on the cycle of the clock signal CK, the error between the time Lτ which is L times the cycle of the clock signal CK and the symbol cycle T indicated by the digital modulation signal is sufficiently small. If it is suppressed, one interpolation value is calculated from the discretization points included in one symbol period T, and the value is output at every constant time interval Lτ = T.

  Through such processing, the I / Q signal reproduction unit 34 generates a reproduction I / Q signal indicating a value corresponding to a value given on the transmission device side for each symbol period T. The I / Q signal reproduction unit 34 inputs the reproduction I / Q signal to the frame detection unit 38 and the code detection unit 36.

  The code detector 36 obtains a symbol code from the reproduced I / Q signal, and outputs a time-sequential symbol code as a digital signal.

  The frame detection unit 38 calculates a correlation value between each waveform change pattern of the reproduction I signal and the reproduction Q signal and a waveform change pattern stored in advance, and inputs the correlation value to the control unit 40. Based on the correlation value, the control unit 40 determines whether or not the received unit frame 50 is assigned to the receiving device 1, and is assigned based on the determination result and the clock signal CK. Each component of the receiving apparatus 1 is controlled to demodulate only the unit frame 50 that is present.

  The control unit 40 detects the time when reception of the divided frame 50a is started based on the correlation value output from the frame detection unit 38. The time at which the first discretization point of each of the plurality of divided frames 50a appears can be estimated by a predetermined number M of discretization points. Therefore, the control unit 40 detects the time when the first discretization point of the divided frame 50a appears by detecting the elapsed time from the time when reception of the unit frame 50 is started by the clock signal CK. Then, the divided frame information R is input to the phase difference estimation unit 23 at the time when reception of the divided frame 50a is started.

  With such a configuration, the receiving apparatus 1 can extract a digital signal from the digital modulation signal even when the symbol period of the digital modulation signal and the clock period of the clock signal CK are not synchronized. It becomes.

In the divided memory type synchronous demodulator 17 according to the present embodiment, as can be seen from the equations (6) and (7), in order to calculate the phase difference Δθ, from p = q to p = q + M−1 (unit frame 50 For the divided frame 50a that appears at the end of (1), the cumulative addition of p = q + M _E −1) is performed. Therefore, the time required until the discretized I / Q signal is input to the phase difference estimation unit 23 and the phase difference Δθ is calculated is a time corresponding to the time length of the divided frame 50a. Therefore, the time required to calculate the phase difference Δθ is larger than that of the storage type synchronous demodulator 70 according to the conventional configuration which requires a time corresponding to the time length of the unit frame 50 to calculate the phase difference Δθ. It can be shortened. Further, in the receiving device 1 to which the divided storage type synchronous demodulator 17 is applied, processing from receiving a digital modulation signal to acquiring a digital signal can be performed more quickly than the receiving device 5.

  In the divided storage type synchronous demodulator 17 according to the present embodiment, the divided frame storage unit 44 stores the divided frame 50a and stands by while the phase difference estimation unit 23 calculates the phase difference Δθ. For this reason, at least the time length of the divided frame 50a is required from the input of the digital modulation signal to the divided storage type synchronous demodulator 17 until the reproduction I / Q signal is output. Therefore, in the receiving apparatus 3 according to the second embodiment of the present invention described below, the process of storing and holding the discretized I / Q signal is not performed while the phase difference Δθ is calculated. The processing for generating the / Q signal is performed quickly.

  FIG. 3 shows the configuration of the receiving device 3 according to the second embodiment of the present invention. The same components as those of the receiving device 1 according to the first embodiment are denoted by the same reference numerals, and the description thereof is simplified.

  The receiving device 3 includes an antenna 10, a radio receiving unit 12, a quadrature detection unit 14, a real-time synchronous demodulation unit 16, a code detection unit 36, a frame detection unit 38, a control unit 40, and a clock signal generation unit 18. The

  The radio reception unit 12 performs high frequency amplification, frequency conversion to an intermediate frequency, and intermediate frequency amplification on the digital modulation signal received via the antenna 10 and inputs the result to the quadrature detection unit 14. The quadrature detection unit 14 extracts an I / Q signal from the digital modulation signal and inputs it to the real-time synchronous demodulation unit 16.

  The real-time synchronous demodulator 16 includes an A / D converter 20, a phase difference estimator 22, and an I / Q signal regenerator 34.

  The I / Q signal input to the real-time synchronous demodulator 16 is input to the A / D converter 20. The A / D conversion unit 20 discretizes each of the I signal and the Q signal at the period of the clock signal CK output from the clock signal generation unit 18 and outputs the phase difference estimation unit 22 and the I / Q signal as a discretized I / Q signal. Input to the playback unit 34.

  The phase difference estimation unit 22 includes a square sum calculation unit 24, a cosine component extraction unit 26a, a sine component extraction unit 26b, an arctangent calculation unit 28, and a phase difference storage unit 30. Similar to the phase difference estimator 23 according to the first embodiment, the phase difference estimator 22 calculates the phase difference Δθ based on the divided frame 50 a that is a signal obtained by dividing the unit frame 50.

  Divided frame information R indicating the timing at which reception of the divided frame 50 a is started from the control unit 40 is input to the phase difference estimation unit 22. When the divided frame information R is input, the phase difference estimation unit 22 starts calculating the phase difference Δθ with respect to the divided frame 50a.

  Similar to the phase difference estimation unit 23 according to the first embodiment, the phase difference estimation unit 22 calculates the phase difference Δθ based on the equations (5) to (8-2). However, the calculated phase difference Δθ is different from the phase difference estimation unit 23 in that it is input to the phase difference storage unit 30.

  The arc tangent calculation unit 28 inputs the calculated phase difference Δθ to the phase difference storage unit 30. The phase difference storage unit 30 stores and holds the previously input phase difference Δθ until the phase difference Δθ is input based on the next received divided frame 50a, and the I / Q signal reproduction unit 34 stores it. The value is output. Therefore, until the divided frame information R is input from the control unit 40 and the phase difference Δθ is calculated, the recently calculated phase difference Δθ is output to the I / Q signal reproducing unit 34.

  Further, the phase difference Δθ calculated based on the divided frame 50a appearing at the end of the unit frame 50 is not changed until the phase difference Δθ is input based on the first divided frame 50a of the next received unit frame 50. It is held in the phase difference storage unit 30.

  Based on the phase difference Δθ and the discretized I / Q signal, the I / Q signal reproduction unit 34 performs an interpolation operation for calculating a value at a symbol point for each of the I signal and the Q signal, and performs the I / Q signal reproduction for each symbol period T. An operation result for each of the signal and the Q signal is output. The I / Q signal reproduction unit 34 is preferably configured by a digital filter whose characteristics are determined by tap coefficients. The tap coefficient of the digital filter is determined based on the phase difference Δθ. Specific processing is as described in the description of the receiving device 1 according to the first embodiment.

  The phase difference Δθ input from the phase difference estimating unit 22 to the I / Q signal reproducing unit 34 is based on the divided frame 50a that is one ahead of the divided frame 50a input to the I / Q signal reproducing unit 34. It is calculated. This is because the storage means is not provided between the A / D conversion unit 20 and the I / Q signal reproduction unit 34 unlike the divided storage type synchronous demodulation unit 17 according to the first embodiment, and This is because the phase difference storage unit 30 stores and outputs the phase difference Δθ calculated based on the previous divided frame 50a. When the first divided frame 50a of the unit frame 50 is input to the I / Q signal reproducing unit 34, the phase difference calculated based on the divided frame 50a that appears at the end of the unit frame 50 received earlier. Δθ is input to the I / Q signal reproducing unit 34.

  The I / Q signal reproducing unit 34 outputs one interpolation value for every L discrete values by counting the pulses of the clock signal CK. Since the time interval for outputting the interpolation value depends on the cycle of the clock signal CK, the error between the time Lτ which is L times the cycle of the clock signal CK and the symbol cycle T indicated by the digital modulation signal is sufficiently small. If it is suppressed, one interpolation value is calculated from the discretization points included in one symbol period T, and the value is output at every constant time interval Lτ = T.

  Through such processing, the I / Q signal reproduction unit 34 generates a reproduction I / Q signal indicating a value corresponding to a value given on the transmission device side for each symbol period T. The I / Q signal reproduction unit 34 inputs the reproduction I / Q signal to the frame detection unit 38 and the code detection unit 36.

  The code detector 36 obtains a symbol code from the reproduced I / Q signal, and outputs a time-sequential symbol code as a digital signal.

  With such a configuration, the receiving apparatus 3 can extract a digital signal from the digital modulation signal even when the symbol period of the digital modulation signal and the clock period of the clock signal CK are not synchronized. It becomes.

  The real-time synchronous demodulation unit 16 according to the present embodiment is based on the previously input divided frame 50a while the phase difference estimation unit 22 calculates the phase difference Δθ according to the currently input divided frame 50a. A reproduction I / Q signal is generated based on the calculated phase difference Δθ. Therefore, it is not necessary to store the discretized I / Q signal in order to wait for the phase difference Δθ to be calculated by the phase difference estimator 22, and until the digital signal is acquired after receiving the digital modulation signal. Can be performed quickly.

  The real-time synchronous demodulator 16 generates a reproduction I / Q signal based on the phase difference Δθ calculated based on the previously input divided frame 50a. Therefore, the error included in the reproduction I / Q signal depends on the fluctuation of the phase difference Δθ for each divided frame 50a. That is, the greater the variation in the phase difference Δθ for each divided frame 50a due to the symbol period variation of the I / Q signal or the phase variation of the clock signal CK, the greater the error contained in the reproduced I / Q signal. However, if the time length of the divided frame 50a is shortened, the variation in the phase difference Δθ for each of the divided frames 50a described above can be suppressed to be small, so that the error included in the reproduced I / Q signal can be suppressed to be small. Therefore, the number M of discretization points included in the divided frame 50a is preferably determined in view of errors included in the reproduction I / Q signal.

  When the symbol period fluctuation of the I / Q signal or the phase fluctuation of the clock signal CK is sufficiently small, the error included in the reproduced I / Q signal is sufficiently small even if the time length of the divided frame 50a is not set sufficiently short. It can be suppressed.

  In the receiving apparatus 1 according to the first embodiment and the receiving apparatus 3 according to the second embodiment, the following problem is avoided by optimally setting the number M of discretization points included in the divided frame 50a. can do.

  The receiving apparatus 5 in the conventional configuration has the following problems due to an error in the symbol period T of the I / Q signal extracted from the digital modulation signal or an error in the time interval τ of the discretization of the discretized I / Q signal. there were.

  The phase difference estimation unit 72 of the receiving device 5 calculates the phase difference Δθ based on the discretized I / Q signal corresponding to the unit frame 50. This is because it is more effective to eliminate non-regular errors caused by noise or the like by contributing as many discretized values as possible to the cumulative addition processing shown in the above equations (2) and (3). Because. That is, the maximum number of discretized values that can contribute to the calculation of the phase difference Δθ is all the discretized values obtained from the unit frame 50, and all of these contribute to the calculation of the phase difference Δθ.

  However, making more discretized values contribute to the calculation of the phase difference Δθ is not necessarily advantageous in order to reduce the estimation error of the phase difference Δθ. The reason is as follows.

The transmission apparatus includes a symbol clock signal generation unit that determines a symbol period when digital modulation is performed. Frequency error of the symbol clock signal generating unit appears as an error Delta] t _a symbol period T of the I / Q signals extracted from the digital modulated signal in the receiver 5.

On the other hand, the clock signal generation unit 18 included in the receiving device 5 outputs a clock signal CK indicating a cycle defined by design, and the cycle fluctuates within the range of the cycle error specified. This periodic error appears as an error Δt _{b in} the discretization time interval of the discretized I / Q signal. This error is LΔt _b per symbol period (L is the number of discretization points included in the unit symbol). Then, when the design criteria of the design criteria and the clock signal generator 18 of the symbol clock signal generator included in the transmitting apparatus different, the value of the error Delta] t _a and the error Eruderutati _b will be different.

The period deviation between the symbol period indicated by the I / Q signal and the period indicated by the reference signal is expressed as Δt _a −LΔt _b, and the difference between the error Δt _a and the error LΔt _b indicates that the symbol period and the reference signal It means that there is a period deviation between. If there is such a periodic deviation, an error included in the reference cosine wave component C and the reference sine wave component S extracted from the square sum signal becomes large, and an estimation error of the calculated phase difference Δθ becomes large.

The estimation error of the phase difference Δθ due to such a period deviation between the symbol period and the reference signal cannot be reduced even if the number of discretized values contributing to the calculation of the phase difference Δθ is increased. This is because as the number of discretized values contributing to the calculation of the phase difference Δθ increases, the time difference between the symbol point and the point at which the reference cosine wave signal takes a maximum value becomes more prominent. This is because, for example, each of the symbol points E _{0 to} E _J-1 in FIG. 6A and each of the points t _{B0 to} t _BJ-1 at which the maximum value of the reference cosine wave signal in FIG. It is also clear that the time difference becomes non-uniform as the number of discretization points increases.

  Therefore, contributing more discretized values to the calculation of the phase difference Δθ is advantageous in order to reduce the estimation error of the phase difference Δθ caused by noise or the like, but it is effective between the symbol period and the reference signal. It can be said that it is disadvantageous to reduce the estimation error of the phase difference Δθ caused by the period deviation. The receiving apparatus 5 in the conventional configuration causes all the discretized values included in the unit frame 50 to contribute to the calculation of the phase difference Δθ. For this reason, when the number of discretization points included in the unit frame 50 is large, there is a problem that an estimation error of the phase difference Δθ due to a period deviation between the symbol period and the reference signal increases. .

  The estimation error of the phase difference Δθ appears as an error in amplitude included in each of the reproduction I signal and reproduction Q signal output from the I / Q signal reproduction unit 34, and the error rate of the digital signal output from the code detection unit 36 Strengthen the tendency to increase.

  In the divided memory type synchronous demodulator 17 according to the first embodiment and the real time type synchronous demodulator 16 according to the second embodiment, the number M of discretization points included in the divided frame 50a can be arbitrarily set. . That is, the number M of discretized values that contribute to the calculation of the phase difference Δθ according to the equations (6) and (7) can be optimally set.

  Increasing the number M of discretization points included in the divided frame 50a increases the effect of eliminating the estimation error of the phase difference Δθ caused by noise and the like, and reducing the number M of discretization points included in the divided frame 50a reduces the symbol The effect of eliminating the estimation error of the phase difference Δθ due to the period deviation between the period and the reference signal is increased. Therefore, the number M of discretization points eliminates the estimation error of the phase difference Δ caused by noise and the like, and the estimation error of the phase difference Δ caused by the period deviation between the symbol period and the reference signal. It is preferable to set in consideration of both of the degree to be performed.

  In Non-Patent Document 1, a case where a maximum of 1200 symbols is included in one burst is taken as an example. In the present embodiment, on the other hand, it is preferable to determine the number of symbol points included in the divided frame, for example, about 64 symbols to 512 symbols.

It is a figure which shows the structure of the receiver which concerns on the 1st Embodiment of this invention. It is a figure which shows the relationship between a unit frame and a division | segmentation frame. It is a figure which shows the structure of the receiver which concerns on the 2nd Embodiment of this invention. It is a figure which shows the structural example of the digital modulation signal handled by digital wireless communication. It is a figure which shows the structure of the receiver in a prior art. It is a figure which shows a square sum signal, a reference cosine wave signal, and a reference sine wave signal.

Explanation of symbols

  1, 3, 5 Receiver 10 Antenna, 12 Radio receiver, 14 Quadrature detector, 16 Real time synchronous demodulator, 17 Divided memory synchronous demodulator, 18 Clock signal generator, 20 A / D converter, 22 , 23, 72 Phase difference estimation unit, 24, 74 square sum calculation unit, 26a, 76a cosine component extraction unit, 26b, 76b sine component extraction unit, 28, 78 arc tangent calculation unit, 30 phase difference storage unit, 34, 82 I / Q signal reproduction unit, 36 code detection unit, 38 frame detection unit, 40 control unit, 44 divided frame storage unit, 50 unit frame, 50a divided frame, 70 storage type synchronous demodulation unit, 80 unit frame storage unit.

Claims (6)

A discretization unit that discretizes an input signal and outputs the discretized input signal;
A demodulator that obtains and outputs a value indicated by the input signal based on the discretized input signal at an information timing that is a timing at which the input signal indicates information;
A demodulator comprising:
The discretization unit includes:
Discretize an input signal of finite time length and output it as a finite length discretized input signal,
The demodulator
A reference phase is set based on a timing at which a partially discretized input signal that is a part of the finite-length discretized input signal is discretized by the discretization unit, and a phase obtained from information timing of the partially discretized input signal and the reference Phase difference calculating means for calculating a phase difference that is a difference from the phase;
An input signal reproducing means for calculating a value at an information timing of the partially discretized input signal based on the phase difference;
A demodulating device comprising: The demodulator according to claim 1,
The demodulator comprises a digital filter that determines a tap coefficient based on the phase difference. A discretization unit that discretizes an input signal and outputs the discretized input signal;
A demodulator that obtains and outputs a value indicated by the input signal based on the discretized input signal at an information timing that is a timing at which the input signal indicates information;
A demodulator comprising:
The demodulator
A reference phase is set based on the timing at which the first input signal is discretized in the discretization unit, and a phase difference that is a difference between the phase obtained from the information timing of the first input signal and the reference phase is Phase difference calculating means for calculating based on the discretized signal of the first input signal;
An input signal reproducing means for calculating a value at an information timing of a second input signal inputted after the first input signal based on the phase difference;
A demodulating device comprising: The demodulator according to claim 3, wherein
The demodulator comprises a digital filter that determines a tap coefficient based on the phase difference. The demodulator according to claim 3 or claim 4, wherein
The demodulator according to claim 1, wherein the first input signal and the second input signal are signals included in the same unit frame. A wireless receiver for receiving a digitally modulated signal;
A digital demodulator for extracting a digital signal from the signal output by the wireless receiver;
A receiving system comprising:
The digital demodulator includes the demodulator according to any one of claims 1 to 5,
A receiving system, wherein a digital signal is extracted from a signal output from the demodulator.

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