JP2004064671A

JP2004064671A - Demodulating device, and receiving device

Info

Publication number: JP2004064671A
Application number: JP2002223591A
Authority: JP
Inventors: Atsushi Murayama; 村山　敦; Kenji Izawa; 井澤　賢二; Hirotsugu Kubo; 久保　博嗣
Original assignee: Mitsubishi Electric Corp
Current assignee: Mitsubishi Electric Corp
Priority date: 2002-07-31
Filing date: 2002-07-31
Publication date: 2004-02-26
Anticipated expiration: 2022-07-31
Also published as: JP3976634B2

Abstract

<P>PROBLEM TO BE SOLVED: To provide a demodulating device for detecting a frequency error with precision. <P>SOLUTION: The demodulating device includes data demodulators (5-1 to 5-N, 5) for demodulating original transmission data from an input signal. Each data demodulator includes a phase adjuster 8 for adjusting the phase of a symbol to be a data determination object, based on a transmission line estimating result obtained by estimating the symbol immediately before the data determination object symbol; a data determining part 9 for determining the input signal after phase adjustment with the symbol as a unit as a demodulation processing; a transmission line estimating apparatus 10 for performing a transmission line estimation processing by using the determination result, and the input signal before phase adjustment; and a frequency error detecting apparatus 11 for detecting the frequency error through the use of the transmission line estimating result corresponding to the two symbols which are temporally separated in the same receiving signal sequence. <P>COPYRIGHT: (C)2004,JPO

Description

【０００１】
【発明の属する技術分野】
本発明は、蓄積一括復調方式を採用する復調装置および受信装置に関するものであり、特に、パイロットシンボルを用いることなく周波数誤差を検出することが可能な復調装置および受信装置に関するものである。
【０００２】
【従来の技術】
以下、従来の復調方法について説明する。図９は、復調時における周波数誤差の検出にパイロットシンボルを用いる場合の信号フォーマットの一例を示す図である。図９において、「ＳＷ」は同期語を表し、「Ｐ」はパイロットシンボルを表し、「Ｄ」はデータを表す。この方法では、パイロットシンボルという既知系列をスロットに埋め込み、このパイロットシンボルの位相変化を検出することによって、周波数誤差を検出する。
【０００３】
また、図１０は、復調時における周波数誤差の検出に同期語のみを用いる場合の信号フォーマットの一例を示す図である。たとえば、同期語におけるｋ−１番目とｋ番目のシンボル間の位相偏移をθとし、受信信号中の同期語部分におけるｋ−１番目とｋ番目のシンボル間の位相偏移をφとすると、この間における実際の位相偏移はφ−θで与えられる。これを同期語全体にわたって平均化すると、この間の位相偏移、すなわち、周波数誤差を求めることができる。
【０００４】
【発明が解決しようとする課題】
しかしながら、上記、図９に示す従来の復調方法では、スロット中にパイロットシンボルという冗長信号を挿入するので、フレームの使用効率が低下する、という問題があった。
【０００５】
また、図１０に示す従来の復調方法では、同期語だけを用いて周波数誤差を検出しているが、同期語だけでは精度のよい周波数誤差を検出することができず、さらに、同期語における周波数誤差と同期語から離れた時間位置での周波数誤差が異なる場合には、ＢＥＲ特性が劣化する、という問題があった。
【０００６】
本発明は、上記に鑑みてなされたものであって、パイロットシンボルを用いることなく、同期語およびデータ部分の少なくともいずれか一方を用いて、精度よく周波数誤差を検出可能な復調装置および受信装置を得ることを目的とする。
【０００７】
【課題を解決するための手段】
上述した課題を解決し、目的を達成するために、本発明にかかる復調装置にあっては、同期語およびデータ部を有する受信信号から送信データを復調するデータ復調手段を備え、前記データ復調手段は、前記受信信号に基づいて伝送路推定処理を行う伝送路推定手段と、受信信号系列内において時間的に離れた複数のシンボルに対応した前記伝送路推定結果を用いて周波数誤差を検出する周波数誤差検出手段と、を備えることを特徴とする。
【０００８】
つぎの発明にかかる復調装置に置いて、前記データ復調手段は、受信済みのシンボルから推定された伝送路推定結果に基づいて、当該データ判定対象のシンボルの位相を調整する位相調整手段と、前記位相調整後の入力信号をシンボル単位に判定するデータ判定手段と、を備え、前記伝送路推定手段は、前記判定結果および前記位相調整前の受信信号を用いて伝送路推定処理を行うことを特徴とする。
【０００９】
つぎの発明にかかる復調装置にあっては、前記データ復調手段と、前段の周波数誤差検出手段により検出された周波数誤差に基づいて受信信号から周波数誤差を除去し、当該周波数誤差除去後の受信信号を次段のデータ復調手段に対して出力する周波数誤差除去手段と、の組み合わせを複数段備えることを特徴とする。
【００１０】
つぎの発明にかかる復調装置にあっては、前記周波数誤差除去手段が、前記周波数誤差またはその定数倍の値と、同一受信信号系列において検出されたそれ以前の周波数誤差またはその定数倍の値と、の加算結果に基づいて、受信信号から周波数誤差を除去し、当該周波数誤差除去後の受信信号を次段のデータ復調手段に対して出力し、前記複数段にわたって復調処理および周波数誤差除去処理を繰り返し実行し、最終段のデータ復調手段が、前段にて周波数誤差除去後の受信信号から送信データを復調することを特徴とする。
【００１１】
つぎの発明にかかる復調装置にあっては、さらに、前記周波数誤差と同一受信信号系列において検出されたそれ以前の周波数誤差との加算結果に基づいて、受信信号から現段階でのすべての周波数誤差を除去し、当該周波数誤差除去後の受信信号を前記データ復調手段に対して出力する周波数誤差除去手段と、前記データ復調手段出力の周波数誤差を所定のタイミングで前記周波数誤差除去手段にフィードバックするタイミング制御手段と、を備え、前記フィードバックによって発生する周波数誤差除去処理と、当該周波数誤差除去処理後の受信信号の復調処理と、を所定回数にわたって繰り返し実行することを特徴とする。
【００１２】
つぎの発明にかかる復調装置にあっては、前記データ復調手段と、前段にて周波数誤差除去後の受信信号から前記データ復調手段出力の周波数誤差を除去し、当該周波数誤差除去後の受信信号を次段のデータ復調手段に入力する周波数誤差除去手段と、の組み合わせを複数段備え、前記複数段にわたって復調処理および周波数誤差除去処理を繰り返し実行し、最終段のデータ復調手段が、前段にて周波数誤差除去後の受信信号から送信データを復調することを特徴とする。
【００１３】
つぎの発明にかかる復調装置にあっては、前記定数と、前記伝送路推定手段にてＬＭＳアルゴリズムを採用した場合のステップサイズと、前記周波数誤差検出手段によってデータ判定を行うシンボル数と、の少なくとも１つのパラメータの値を、復調処理毎に変更可能とすることを特徴とする。
【００１４】
つぎの発明にかかる受信装置にあっては、所定の無線受信処理後の受信信号から送信データを復調するデータ復調手段を備え、前記データ復調手段は、前記受信信号に基づいて伝送路推定処理を行う伝送路推定手段と、受信信号系列内において時間的に離れた複数のシンボルに対応した伝送路推定結果を用いて周波数誤差を検出する周波数誤差検出手段と、を備えることを特徴とする。
【００１５】
つぎの発明にかかる受信装置において、前記データ復調手段は、受信済みのシンボルから推定された伝送路推定結果に基づいて、当該データ判定対象のシンボルの位相を調整する位相調整手段と、前記位相調整後の受信信号をシンボル単位に判定するデータ判定手段と、を備え、前記伝送路推定手段は、前記判定結果および位相調整前の受信信号を用いて伝送路推定処理を行うことを特徴とする。
【００１６】
つぎの発明にかかる受信装置にあっては、前記データ復調手段と、前段の周波数誤差検出手段により検出された周波数誤差に基づいて受信信号から周波数誤差を除去し、当該周波数誤差除去後の受信信号を次段のデータ復調手段に対して出力する周波数誤差除去手段と、の組み合わせを複数段備えることを特徴とする。
【００１７】
つぎの発明にかかる受信装置にあっては、前記周波数誤差除去手段が、前記周波数誤差またはその定数倍の値と、同一受信信号系列において検出されたそれ以前の周波数誤差またはその定数倍の値と、の加算結果に基づいて、受信信号から周波数誤差を除去し、当該周波数誤差除去後の受信信号を次段のデータ復調手段に対して出力し、前記複数段にわたって復調処理および周波数誤差除去処理を繰り返し実行し、最終段のデータ復調手段が、前段にて周波数誤差除去後の受信信号から送信データを復調することを特徴とする。
【００１８】
つぎの発明にかかる受信装置にあっては、さらに、前記周波数誤差またはその定数倍の値と、同一受信信号系列において検出されたそれ以前の周波数誤差またはその定数倍の値と、の加算結果に基づいて、受信信号から現段階でのすべての周波数誤差を除去し、当該周波数誤差除去後の受信信号を前記データ復調手段に対して出力する周波数誤差除去手段と、前記データ復調手段出力の周波数誤差を所定のタイミングで前記周波数誤差除去手段にフィードバックするタイミング制御手段と、を備え、前記フィードバックによって発生する周波数誤差除去処理と、当該周波数誤差除去処理後の受信信号の復調処理と、を所定回数にわたって繰り返し実行することを特徴とする。
【００１９】
つぎの発明にかかる受信装置にあっては、前記データ復調手段と、前段にて周波数誤差除去後の受信信号から前記データ復調手段出力の周波数誤差またはその定数倍の値を除去し、当該周波数誤差除去後の受信信号を次段のデータ復調手段に入力する周波数誤差除去手段と、の組み合わせを複数段備え、前記複数段にわたって復調処理および周波数誤差除去処理を繰り返し実行し、最終段のデータ復調手段が、前段にて周波数誤差除去後の受信信号から送信データを復調することを特徴とする。
【００２０】
つぎの発明にかかる受信装置にあっては、前記定数と、前記伝送路推定手段にてＬＭＳアルゴリズムを採用した場合のステップサイズと、前記周波数誤差検出手段によってデータ判定を行うシンボル数と、の少なくとも１つのパラメータの値を、復調処理毎に変更可能とすることを特徴とする。
【００２１】
【発明の実施の形態】
以下に、本発明にかかる復調装置および受信装置の実施の形態を図面に基づいて詳細に説明する。なお、この実施の形態によりこの発明が限定されるものではない。
【００２２】
実施の形態１．
図１は、本発明にかかる復調装置の実施の形態１の構成を示す図である。図１において、１は受信信号であり、２はデータ判定結果であり、３−２，…，３−Ｎは受信信号を記憶するための受信信号記憶回路であり、４−１，４−２，…，４−Ｎは周波数誤差を補正するための周波数誤差補正器であり、５−１，５−２，…，５−Ｎは受信信号から送信データを取り出すためのデータ復調器であり、１３−１，１３−２，…は乗算器である。
【００２３】
また、図２は、上記復調装置を備えた受信装置の構成を示す図である。図２において、２１は受信アンテナであり、２２は受信アンテナで受信した信号から送信データを取り出す受信装置であり、２３は受信アンテナで受信した信号を所望のレベルに増幅し、周波数変換処理等の受信処理を実行する無線受信部であり、２４は上記復調装置である。
【００２４】
ここで、上記のように構成される復調装置の動作について説明する。まず、受信信号は、蓄積一括復調における復調処理単位で周波数誤差補正器４−１と受信信号記憶回路３−２に受け取られる。この受信信号は、たとえば、直交振幅変調（ＱＡＭ：Ｑｕａｄｒａｔｕｒｅ　Ａｍｐｌｉｔｕｄｅ　Ｍｏｄｕｌａｔｉｏｎ）の場合、同相成分である余弦波の振幅（Ｉ軸）をＩとし、直交成分である正弦波の振幅（Ｑ軸）をＱとし、（Ｉ、Ｑ）＝（１、１）のように表される。
【００２５】
周波数誤差補正器４−１では、受け取った受信信号１を用いて周波数誤差を除去する。なお、ここでは、前段にデータ復調器がなく、周波数誤差が検出されていないので、上記周波数誤差除去処理を省略することとしてもよい。また、上記周波数誤差除去処理においては、たとえば、予め規定した固定値や、データ復調器以外で検出された値、等を用いて周波数誤差を除去することとしてもよい。
【００２６】
データ復調器５−１では、周波数誤差除去後の受信信号に対してデータ判定を行う。同時に、同期語（ＳＷ）およびデータ部分（Ｄ）の少なくともいずれか一方を用いて後述する周波数誤差の検出を行い、周波数誤差補正器４−２に対して周波数誤差を出力する。
【００２７】
一方、受信信号記憶回路３−２では、受け取った受信信号１を記憶するとともに、周波数誤差補正器４−２に対してこの受信信号１を出力する。周波数誤差補正器４−２では、データ復調器５−１から受け取る周波数誤差（この場合乗算器１３−１省略可）または乗算器１３−１出力の定数倍（α（１））の周波数誤差と、同一受信信号系列において検出された（補正された）以前の周波数誤差またはその定数倍（α（１））の周波数誤差と、をすべて加算する。そして、その加算結果を用いて、受信信号記憶回路３−２出力の受信信号１から周波数誤差を除去する。
【００２８】
データ復調器５−２では、周波数誤差除去後の受信信号に対してデータ判定を行う。同時に、同期語（ＳＷ）およびデータ部分（Ｄ）の少なくともいずれか一方を用いて後述する周波数誤差の検出処理を行う。
【００２９】
以下同様に、受信信号記憶回路３−Ｎ（Ｎは３以上の整数）では、受け取った受信信号を記憶するとともに、周波数誤差補正器４−Ｎに対してこの受信信号を出力する。周波数誤差補正器４−Ｎでは、前段のデータ復調器から受け取る周波数誤差またはその定数倍（α（Ｎ−１）：図示せず）の周波数誤差と、同一受信信号系列において検出された（補正された）以前の周波数誤差またはその定数倍の周波数誤差と、をすべて加算する。そして、その加算結果を用いて、受信信号記憶回路３−Ｎ出力の受信信号から周波数誤差を除去する。最後に、データ復調器５−Ｎでは、周波数誤差除去後の受信信号に対してデータ判定を行い、当該データ判定結果２を出力する。
【００３０】
図３は、上記データ復調器の構成例を示す図である。図３において、６は周波数誤差補正後の受信信号であり、７は検出された周波数誤差であり、８は受信信号６の位相を調整するための位相調整器であり、９は位相調整後の受信信号に対してデータ判定を行うデータ判定器であり、１０はデータ判定結果とデータ判定前の信号を用いて伝送路インパルス応答（ＣＩＲ）を推定するための伝送路推定器であり、１１は推定ＣＩＲから周波数誤差を推定するための周波数誤差検出器である。
【００３１】
ここで、上記のように構成されるデータ復調器の動作について説明する。まず、位相調整器８では、伝送路推定器１０から出力される１つ前のシンボルから求められた推定ＣＩＲを用いて、データ判定対象の１シンボルの位相調整を行う。
【００３２】
データ判定器９では、位相調整後のシンボルに対してデータ判定を行う。伝送路推定器１０では、上記判定データと、受信信号６と、上記位相調整に用いた推定ＣＩＲと、の３つのデータに基づいて、ＬＭＳ（Ｌｅａｓｔ　Ｍｅａｎ　Ｓｑｕａｒｅ）アルゴリズムによる推定ＣＩＲの更新処理を行う。ここで、ＬＭＳアルゴリズムにおけるステップサイズは、復調の回数に応じた値を用いることとしてもよい。
【００３３】
以降、位相調整器８では、シンボル毎に更新される推定ＣＩＲを用いて受信シンボルの位相調整を行い、後続するデータ判定器９および伝送路推定器１０においても、上記と同様の動作を繰り返し実行する。なお、判定対象のシンボルは、同期語（ＳＷ）であってもデータ部分（Ｄ）であってもよい。
【００３４】
また、周波数誤差検出器１１では、同一受信信号系列内において、時間的に離れた２つのシンボルに対応するそれぞれの推定ＣＩＲより、１シンボルあたりの位相回転量、すなわち、周波数誤差を検出する。なお、周波数誤差を検出する場合は、同一受信信号系列内（同期後およびデータ部分を含む同一スロット内）において時間的に離れた２つのシンボルに対応した推定ＣＩＲが必要であって、必ずしも、同一受信信号系列内のすべてのシンボルに対してデータ判定を行う必要はない。たとえば、図４に示したように、周波数誤差検出時におけるデータ判定シンボル数は、同期語部分とデータ部分の中のＮ（ＥＴ）シンボルだけでもよい。また、ここで検出される周波数誤差は、図４に示したように、定常位相誤差の存在により本来の周波数誤差よりも値が小さくなるのが一般的である。
【００３５】
また、図５は、上記繰り返し復調の時間的な制約を示す図である。上記繰り返し復調では、蓄積一括復調方式を採用しているため、１スロット分のデータは、１スロットに相当する時間以内に復調されなければならない。
【００３６】
このように、本実施の形態においては、従来の復調時のように同期語だけを用いて周波数誤差を検出するのではなく、一回の復調時に、同期語およびデータ部分の少なくともいずれか一方を用いて、精度よく周波数誤差を検出する。そして、この復調処理を繰り返し実行することによって、さらに精度の高い周波数誤差を求める。これにより、ビット誤り率を大幅に改善することができる。
【００３７】
実施の形態２．
図６は、本発明にかかる復調装置の実施の形態２の構成を示す図である。図６において、３は受信信号を格納するための受信信号記憶回路であり、４は周波数誤差を補正するための周波数誤差補正器であり、５は受信信号から送信データを取り出すためのデータ復調器であり、１２は動作タイミングを制御する動作タイミング制御回路であり、１４は乗算器である。なお、受信装置の構成については、前述した実施の形態１と同様である。
【００３８】
受信信号記憶回路３では、蓄積一括復調における復調処理単位で受信信号を記憶し、動作タイミング制御回路１２からの制御信号にしたがって、周波数誤差補正器４に対して受信信号を出力する。
【００３９】
周波数誤差補正器４では、受信信号から動作タイミング制御回路１２出力の周波数誤差を除去し、周波数誤差除去後の受信信号をデータ復調器５に対して出力する。このとき、動作タイミング制御回路１２では、データ復調器５が検出する周波数誤差（この場合乗算器１４省略可）または乗算器１４出力の定数倍（α（Ｎ））の周波数誤差と、同一受信信号系列において検出された（補正された）以前の周波数誤差またはその定数倍（α）の周波数誤差と、をすべて加算し、その加算結果を周波数誤差補正器４に対して出力する。
【００４０】
データ復調器５では、周波数誤差補正後の受信信号に対してデータ判定を行う。同時に、周波数誤差の検出処理を行い、動作タイミング制御回路１２に対して周波数誤差を出力する。なお、データ復調器５の詳細な動作については、前述した実施の形態１における図３と同様である。また、繰り返し復調における時間的な制約についても、前述した実施の形態１と同様である。
【００４１】
つぎに、本実施の形態の復調方法の手順について説明する。図７は、上記復調装置の処理手順を示すフローチャートである。
【００４２】
動作タイミング制御回路１２では、同一受信信号系列を復調する場合に、周波数誤差の補正が必要かどうか、すなわち、すでにデータ復調器５で検出済みの周波数誤差が存在するかどうか、を判断する（ステップＳ１）。
【００４３】
たとえば、補正すべき周波数誤差が存在する場合（ステップＳ１，Ｙｅｓ）、周波数誤差補正器４では、動作タイミング制御回路１２から受け取った周波数誤差にしたがって受信信号を補正する（ステップＳ２）。
【００４４】
また、補正すべき周波数誤差が存在しない場合（ステップＳ１，Ｎｏ）、または、周波数誤差補正後（ステップＳ２）、データ復調器５では、周波数誤差補正器４出力の受信信号を上記のように復調する（ステップＳ３）。そして、上記のように周波数誤差を検出し、その結果を動作タイミング制御回路１２に対して出力する（ステップＳ４）。
【００４５】
動作タイミング制御回路１２では、復調処理が終了したかどうか、すなわち、同一受信信号系列に対する復調回数が規定回数に達したかどうか、を判断する（ステップＳ５）。そして、たとえば、規定回数に達している場合（ステップＳ５，Ｙｅｓ）、復調装置では、復調処理を終了する。一方、規定回数に達していない場合は（ステップＳ５，Ｎｏ）、規定回数に達するまで、上記処理（ステップＳ１〜Ｓ５）を繰り返し実行する。
【００４６】
このように、本実施の形態においては、繰り返し復調に複数の同一構成を用いることなく、動作タイミング制御回路によるタイミング制御で、さらに精度の高い周波数誤差を求める。これにより、前述した実施の形態１と同様の効果が得られるとともに、さらに、回路規模を削減できる。
【００４７】
実施の形態３．
図８は、本発明にかかる復調装置の実施の形態３の構成を示す図である。図８において、３−１，３−２，…，３−Ｍ（Ｍ＝Ｎ−１）は受信信号を記憶するための受信信号記憶回路であり、４−１，４−２，４−３，…，４−Ｎは周波数誤差を補正するための周波数誤差補正器であり、５−１，５−２，５−３，…，５−Ｎは受信信号から送信データを取り出すためのデータ復調器であり、１５−１，１５−２，…は乗算器である。なお、受信装置の構成については、前述した実施の形態１と同様である。
【００４８】
ここで、上記のように構成される復調装置の動作について説明する。まず、受信信号は、蓄積一括復調における復調処理単位で周波数誤差補正器４−１に受け取られる。この受信信号は、たとえば、直交振幅変調（ＱＡＭ）の場合、同相成分である余弦波の振幅（Ｉ軸）をＩとし、直交成分である正弦波の振幅（Ｑ軸）をＱとし、（Ｉ、Ｑ）＝（１、１）のように表される。
【００４９】
周波数誤差補正器４−１では、受け取った受信信号を用いて周波数誤差を除去する。そして、周波数誤差補正後の受信信号を、データ復調器５−１と受信信号記憶回路３−１に対して出力する。なお、ここでは、前段にデータ復調器がなく、周波数誤差が検出されていないので、上記周波数誤差除去処理を省略することとしてもよい。また、上記周波数誤差除去処理においては、たとえば、予め規定した固定値や、データ復調器以外で検出された値、等を用いて周波数誤差を除去することとしてもよい。
【００５０】
データ復調器５−１では、周波数誤差除去後の受信信号に対してデータ判定を行う。同時に、同期語（ＳＷ）およびデータ部分（Ｄ）の少なくともいずれか一方を用いて先に説明した周波数誤差の検出処理を行い、周波数誤差補正器４−２に対して周波数誤差を出力する。一方、受信信号記憶回路３−１では、受け取った周波数誤差補正後の受信信号を記憶し、これを周波数誤差補正器４−２に対して出力する。
【００５１】
周波数誤差補正器４−２では、受信信号記憶回路３−１からの受信信号から、データ復調器５−１に検出された周波数誤差（この場合乗算器１５−１省略可）または乗算器１５−１出力の定数倍（α（１））の周波数誤差を除去する。そして、周波数誤差補正後の受信信号を、データ復調器５−２と受信信号記憶回路３−２に対して出力する。
【００５２】
以下同様に、周波数誤差補正器４−Ｎ（Ｎは３以上の整数）では、前段のデータ復調器から受け取る周波数誤差またはその定数倍（α（Ｎ−１））の周波数誤差を用いて、受信信号記憶回路３−Ｍ出力の受信信号から周波数誤差を除去する。最後に、データ復調器５−Ｎでは、周波数誤差除去後の受信信号に対してデータ判定を行い、当該データ判定結果２を出力する。なお、各データ復調器の詳細な動作については、前述した実施の形態１における図３と同様である。
【００５３】
このように、本実施の形態においては、従来の復調時のように同期語だけを用いて周波数誤差を検出するのではなく、一回の復調時に、同期語およびデータ部分の少なくともいずれか一方を用いて、精度よく周波数誤差を検出する。そして、この復調処理を繰り返し実行することによって、さらに精度の高い周波数誤差を求める。これにより、ビット誤り率を大幅に改善することができる。
【００５４】
【発明の効果】
以上、説明したとおり、本発明によれば、従来の復調時のように同期語だけを用いて周波数誤差を検出するのではなく、一回の復調時に、同期語およびデータ部分の少なくともいずれか一方を用いて、すなわち、同一受信信号系列内において時間的に離れた２つのシンボルに対応した伝送路推定結果を用いて、周波数誤差を検出する構成とした。これにより、同期語のみを用いて周波数誤差を検出する場合と比較して、精度よく周波数誤差を検出することができる、という効果を奏する。
【００５５】
つぎの発明によれば、受信済みのシンボルから推定された伝送路推定結果に基づいてデータ判定対象のシンボルの位相を調整する構成とした。これにより、さらに精度よく周波数誤差を検出することができる、という効果を奏する。
【００５６】
つぎの発明によれば、一回の復調時に、同一受信信号系列内において時間的に離れた２つのシンボルに対応した伝送路推定結果を用いて、周波数誤差を検出する構成とした。そして、この復調処理を繰り返し実行することによって、さらに精度の高い周波数誤差を求め、各周波数誤差除去手段が、受信信号から現段階でのすべての周波数誤差を除去する構成とした。これにより、高精度に周波数誤差を除去できるため、ビット誤り率を大幅に改善することができる、という効果を奏する。
【００５７】
つぎの発明によれば、前段で検出された周波数誤差またはその定数倍の値と、同一受信信号系列において検出されたそれ以前の周波数誤差またはその定数倍の値と、の加算結果に基づいて、受信信号から周波数誤差を除去する構成とした。これにより、精度の高い周波数誤差除去処理が可能となる、という効果を奏する。
【００５８】
つぎの発明によれば、繰り返し復調に複数の同一構成を用いることなく、タイミング制御手段によるタイミング制御で、さらに精度の高い周波数誤差を求める構成とした。これにより、さらに、回路規模を削減できる、という効果を奏する。
【００５９】
つぎの発明によれば、一回の復調時に、同一受信信号系列内において時間的に離れた２つのシンボルに対応した伝送路推定結果を用いて、周波数誤差を検出する構成とした。そして、この復調処理を繰り返し実行することによって、さらに精度の高い周波数誤差を求め、各周波数誤差除去手段が、前段にて周波数誤差除去後の受信信号から当該周波数誤差を除去する構成とした。これにより、さらに高精度に周波数誤差を除去できるため、ビット誤り率を大幅に改善することができる、という効果を奏する。
【００６０】
つぎの発明によれば、各パラメータの値を復調処理毎に可変としたので、さらに精度の高い周波数誤差除去処理が可能となる、という効果を奏する。
【００６１】
つぎの発明によれば、従来の復調時のように同期語だけを用いて周波数誤差を検出するのではなく、一回の復調時に、同期語およびデータ部分の少なくともいずれか一方を用いて、すなわち、同一受信信号系列内において時間的に離れた２つのシンボルに対応した伝送路推定結果を用いて、周波数誤差を検出する構成とした。これにより、同期語のみを用いて周波数誤差を検出する場合と比較して、精度よく周波数誤差を検出することが可能な受信装置を得ることができる、という効果を奏する。
【００６２】
つぎの発明によれば、受信済みのシンボルから推定された伝送路推定結果に基づいてデータ判定対象のシンボルの位相を調整する構成とした。これにより、さらに精度よく周波数誤差を検出することが可能な受信装置を得ることができる、という効果を奏する。
【００６３】
つぎの発明によれば、一回の復調時に、同一受信信号系列内において時間的に離れた２つのシンボルに対応した伝送路推定結果を用いて、周波数誤差を検出する構成とした。そして、この復調処理を繰り返し実行することによって、さらに精度の高い周波数誤差を求め、各周波数誤差除去手段が、受信信号から現段階でのすべての周波数誤差を除去する構成とした。これにより、高精度に周波数誤差を除去できるため、ビット誤り率を大幅に改善することが可能な受信装置を得ることができる、という効果を奏する。
【００６４】
つぎの発明によれば、前段で検出された周波数誤差またはその定数倍の値と、同一受信信号系列において検出されたそれ以前の周波数誤差またはその定数倍の値と、の加算結果に基づいて、受信信号から周波数誤差を除去する構成とした。これにより、精度の高い周波数誤差除去処理が可能な受信装置を得ることができる、という効果を奏する。
【００６５】
つぎの発明によれば、繰り返し復調に複数の同一構成を用いることなく、タイミング制御手段によるタイミング制御で、さらに精度の高い周波数誤差を求める構成とした。これにより、さらに、回路規模を削減可能な受信装置を得ることができる、という効果を奏する。
【００６６】
つぎの発明によれば、一回の復調時に、同一受信信号系列内において時間的に離れた２つのシンボルに対応した伝送路推定結果を用いて、周波数誤差を検出する構成とした。そして、この復調処理を繰り返し実行することによって、さらに精度の高い周波数誤差を求め、各周波数誤差除去手段が、前段にて周波数誤差除去後の受信信号から当該周波数誤差を除去する構成とした。これにより、さらに高精度に周波数誤差を除去できるため、ビット誤り率を大幅に改善することが可能な受信装置を得ることができる、という効果を奏する。
【００６７】
つぎの発明によれば、各パラメータの値を復調処理毎に可変としたので、精度の高い周波数誤差除去処理が可能となり、復調特性を大幅に向上させることが可能な受信装置を得ることができる、という効果を奏する。
【図面の簡単な説明】
【図１】本発明にかかる復調装置の実施の形態１の構成を示す図である。
【図２】本発明にかかる復調装置を備えた受信装置の構成を示す図である。
【図３】データ復調器の構成例を示す図である。
【図４】一般的な周波数誤差を示す図である。
【図５】繰り返し復調の時間的な制約を示す図である。
【図６】本発明にかかる復調装置の実施の形態２の構成を示す図である。
【図７】復調装置の処理手順を示すフローチャートである。
【図８】本発明にかかる復調装置の実施の形態３の構成を示す図である。
【図９】復調時における周波数誤差の検出にパイロットシンボルを用いる場合の信号フォーマットの一例を示す図である。
【図１０】復調時における周波数誤差の検出に同期語のみを用いる場合の信号フォーマットの一例を示す図である。
【符号の説明】
１，６　受信信号、２　データ判定結果、３，３−１，３−２，３−Ｍ，３−Ｎ　受信信号記憶回路、４，４−１，４−２，４−３，４−Ｎ　周波数誤差補正器、５，５−１，５−２，５−３，５−Ｎ　データ復調器、７　周波数誤差、８位相調整器、９　データ判定器、１０　伝送路推定器、１１　周波数誤差検出器、１２　動作タイミング制御回路、１３−１，１３−２，１４，１５−１，１５−２　乗算器、２１　受信アンテナ、２２　受信装置、２３　無線受信部、２４　復調装置。[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a demodulation device and a reception device that employ an accumulation batch demodulation method, and more particularly to a demodulation device and a reception device capable of detecting a frequency error without using a pilot symbol.
[0002]
[Prior art]
Hereinafter, a conventional demodulation method will be described. FIG. 9 is a diagram illustrating an example of a signal format when a pilot symbol is used to detect a frequency error during demodulation. In FIG. 9, “SW” represents a synchronization word, “P” represents a pilot symbol, and “D” represents data. In this method, a known sequence called a pilot symbol is embedded in a slot, and a phase error of the pilot symbol is detected to detect a frequency error.
[0003]
FIG. 10 is a diagram illustrating an example of a signal format when only a synchronizing word is used to detect a frequency error during demodulation. For example, if the phase shift between the (k-1) th and kth symbols in the sync word is θ, and the phase shift between the (k-1) th and kth symbols in the syncword portion in the received signal is φ, The actual phase shift during this period is given by φ-θ. If this is averaged over the entire synchronizing word, a phase shift during this period, that is, a frequency error can be obtained.
[0004]
[Problems to be solved by the invention]
However, the above-described conventional demodulation method shown in FIG. 9 has a problem in that the use efficiency of a frame is reduced because a redundant signal called a pilot symbol is inserted into a slot.
[0005]
Further, in the conventional demodulation method shown in FIG. 10, a frequency error is detected using only the synchronizing word, but an accurate frequency error cannot be detected only by using the synchronizing word. If the error differs from the frequency error at a time position distant from the synchronization word, the BER characteristic deteriorates.
[0006]
The present invention has been made in view of the above, without using a pilot symbol, using at least one of a synchronization word and a data portion, a demodulation device and a reception device capable of accurately detecting a frequency error. The purpose is to get.
[0007]
[Means for Solving the Problems]
In order to solve the above-mentioned problems and achieve the object, a demodulation device according to the present invention includes a data demodulation unit that demodulates transmission data from a reception signal having a synchronization word and a data part, A transmission path estimating means for performing transmission path estimation processing based on the received signal, and a frequency for detecting a frequency error using the transmission path estimation result corresponding to a plurality of temporally separated symbols in the received signal sequence. Error detecting means.
[0008]
In the demodulation device according to the next invention, the data demodulation unit is configured to adjust a phase of the data determination target symbol based on a transmission path estimation result estimated from a received symbol, Data determining means for determining the input signal after the phase adjustment in symbol units, wherein the transmission path estimating means performs a transmission path estimation process using the determination result and the received signal before the phase adjustment. And
[0009]
In the demodulation device according to the next invention, the data demodulation unit and the received signal after removing the frequency error from the received signal based on the frequency error detected by the frequency error detection unit in the preceding stage, And a frequency error removing means for outputting to the data demodulating means at the next stage.
[0010]
In the demodulation device according to the next invention, the frequency error removing means, the frequency error or a value of a constant multiple thereof, and the previous frequency error detected in the same received signal sequence or a value of a constant multiple thereof. , Based on the result of addition, removes the frequency error from the received signal, outputs the received signal after removing the frequency error to the next-stage data demodulation means, and performs demodulation processing and frequency error removal processing over the plurality of stages. It is repeatedly executed, and the data demodulation means at the last stage demodulates transmission data from the reception signal after frequency error removal at the previous stage.
[0011]
In the demodulation device according to the next invention, further, based on the result of addition of the frequency error and the previous frequency error detected in the same received signal sequence, all the frequency errors at the current stage are calculated from the received signal. Frequency error removing means for outputting the received signal after the frequency error removal to the data demodulating means, and timing for feeding back the frequency error of the data demodulating means output to the frequency error removing means at a predetermined timing. And a controller for repeatedly executing a predetermined number of times a frequency error elimination process generated by the feedback and a demodulation process of the received signal after the frequency error elimination process.
[0012]
In the demodulation device according to the next invention, the data demodulation unit, the frequency error of the output of the data demodulation unit is removed from the reception signal after the frequency error removal in the previous stage, the received signal after the frequency error removal A plurality of combinations of frequency error elimination means input to the next-stage data demodulation means; and repeatedly executing demodulation processing and frequency error elimination processing over the plurality of stages. The transmission data is demodulated from the reception signal after error removal.
[0013]
In the demodulation device according to the next invention, at least the constant, the step size when the LMS algorithm is employed in the transmission path estimating means, and the number of symbols for which data judgment is performed by the frequency error detecting means. It is characterized in that the value of one parameter can be changed for each demodulation process.
[0014]
The receiving apparatus according to the next invention includes a data demodulating unit that demodulates transmission data from the received signal after the predetermined wireless receiving process, and the data demodulating unit performs a transmission path estimation process based on the received signal. A transmission path estimating means for performing the transmission path estimation; and a frequency error detecting means for detecting a frequency error using a transmission path estimation result corresponding to a plurality of temporally separated symbols in the received signal sequence.
[0015]
In the receiving apparatus according to the next invention, the data demodulation unit adjusts a phase of the data determination target symbol based on a transmission path estimation result estimated from a received symbol, and the phase adjustment unit Data determination means for determining a subsequent received signal on a symbol-by-symbol basis, wherein the transmission path estimating means performs a transmission path estimation process using the determination result and the received signal before phase adjustment.
[0016]
In the receiving apparatus according to the next invention, the data demodulation unit and the received signal after removing the frequency error from the received signal based on the frequency error detected by the frequency error detection unit at the preceding stage, And a frequency error removing means for outputting to the data demodulating means at the next stage.
[0017]
In the receiving apparatus according to the next invention, the frequency error removing means includes the frequency error or a value of a constant multiple thereof, and the previous frequency error detected in the same received signal sequence or a value of a constant multiple thereof. , Based on the result of addition, removes the frequency error from the received signal, outputs the received signal after removing the frequency error to the next-stage data demodulation means, and performs demodulation processing and frequency error removal processing over the plurality of stages. It is repeatedly executed, and the data demodulation means at the last stage demodulates transmission data from the reception signal after frequency error removal at the previous stage.
[0018]
In the receiving apparatus according to the next invention, further, the frequency error or a value of a constant multiple thereof and the previous frequency error detected in the same received signal sequence or a value of a constant multiple thereof are added to the addition result. Frequency error removing means for removing all frequency errors at the current stage from the received signal, and outputting the received signal after removing the frequency error to the data demodulating means, and a frequency error of the output of the data demodulating means. Timing control means for feeding back to the frequency error removing means at a predetermined timing, the frequency error removing processing generated by the feedback, and the demodulation processing of the received signal after the frequency error removing processing, a predetermined number of times It is characterized by being repeatedly executed.
[0019]
In the receiving apparatus according to the next invention, the data demodulating means removes a frequency error of the output of the data demodulating means or a value of a constant multiple thereof from the received signal after removing the frequency error in the preceding stage, and A plurality of frequency error removing means for inputting the received signal after removal to the data demodulating means at the next stage, and repeatedly performing demodulation processing and frequency error removing processing over said plurality of stages; Is characterized in that the transmission data is demodulated from the reception signal from which the frequency error has been removed in the preceding stage.
[0020]
In the receiving apparatus according to the next invention, at least the constant, the step size when the LMS algorithm is employed in the transmission path estimating means, and the number of symbols for which data determination is performed by the frequency error detecting means. It is characterized in that the value of one parameter can be changed for each demodulation process.
[0021]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of a demodulation device and a receiving device according to the present invention will be described in detail with reference to the drawings. It should be noted that the present invention is not limited by the embodiment.
[0022]
Embodiment 1 FIG.
FIG. 1 is a diagram illustrating a configuration of a first embodiment of a demodulation device according to the present invention. In FIG. 1, 1 is a received signal, 2 is a data determination result, 3-2,..., 3-N are received signal storage circuits for storing the received signal, and 4-1 and 4-2. ,..., 4-N are frequency error correctors for correcting frequency errors, 5-1, 5-2,..., 5-N are data demodulators for extracting transmission data from received signals. Reference numerals 13-1, 13-2, ... denote multipliers.
[0023]
FIG. 2 is a diagram illustrating a configuration of a receiving device including the demodulation device. In FIG. 2, reference numeral 21 denotes a receiving antenna, 22 denotes a receiving device for extracting transmission data from a signal received by the receiving antenna, and 23 amplifies a signal received by the receiving antenna to a desired level and performs frequency conversion processing and the like. A radio receiving unit that performs a receiving process, and 24 is the demodulation device.
[0024]
Here, the operation of the demodulation device configured as described above will be described. First, a received signal is received by the frequency error corrector 4-1 and the received signal storage circuit 3-2 in a unit of demodulation processing in accumulation batch demodulation. For example, in the case of Quadrature Amplitude Modulation (QAM), the received signal has a cosine wave amplitude (I-axis) that is an in-phase component as I and a sine wave amplitude (Q-axis) that is a quadrature component as Q And expressed as (I, Q) = (1, 1).
[0025]
The frequency error corrector 4-1 removes the frequency error using the received signal 1 received. Here, since there is no data demodulator at the preceding stage and no frequency error has been detected, the frequency error removal processing may be omitted. In the frequency error removal processing, the frequency error may be removed using, for example, a predetermined fixed value or a value detected by a device other than the data demodulator.
[0026]
The data demodulator 5-1 performs data determination on the received signal after removing the frequency error. At the same time, a frequency error, which will be described later, is detected using at least one of the synchronization word (SW) and the data portion (D), and a frequency error is output to the frequency error corrector 4-2.
[0027]
On the other hand, the received signal storage circuit 3-2 stores the received received signal 1 and outputs the received signal 1 to the frequency error corrector 4-2. In the frequency error corrector 4-2, the frequency error received from the data demodulator 5-1 (in this case, the multiplier 13-1 can be omitted) or the frequency error of a constant multiple (α (1)) of the output of the multiplier 13-1 is calculated. , And the previous (corrected) frequency error detected in the same received signal sequence or a constant multiple (α (1)) thereof is added. Then, a frequency error is removed from the reception signal 1 output from the reception signal storage circuit 3-2 using the addition result.
[0028]
The data demodulator 5-2 performs data determination on the received signal after removing the frequency error. At the same time, a frequency error detection process described later is performed using at least one of the synchronization word (SW) and the data portion (D).
[0029]
Similarly, the received signal storage circuit 3-N (N is an integer of 3 or more) stores the received received signal and outputs the received signal to the frequency error corrector 4-N. The frequency error corrector 4-N detects (corrects) the frequency error received from the preceding data demodulator or the frequency error of a constant multiple thereof (α (N−1): not shown) in the same received signal sequence. And) add the previous frequency error or a frequency error that is a constant multiple thereof. Then, a frequency error is removed from the reception signal output from the reception signal storage circuit 3-N using the addition result. Finally, the data demodulator 5-N performs data determination on the received signal after removing the frequency error, and outputs the data determination result 2.
[0030]
FIG. 3 is a diagram showing a configuration example of the data demodulator. In FIG. 3, 6 is a received signal after frequency error correction, 7 is a detected frequency error, 8 is a phase adjuster for adjusting the phase of the received signal 6, and 9 is a phase adjuster after the phase adjustment. Reference numeral 10 denotes a data estimator for estimating a transmission path impulse response (CIR) using a data judgment result and a signal before data judgment. This is a frequency error detector for estimating the frequency error from the estimated CIR.
[0031]
Here, the operation of the data demodulator configured as described above will be described. First, the phase adjuster 8 adjusts the phase of one symbol to be subjected to data determination using the estimated CIR obtained from the previous symbol output from the transmission path estimator 10.
[0032]
The data determination unit 9 performs data determination on the symbols after the phase adjustment. The transmission path estimator 10 updates the estimated CIR by an LMS (Least Mean Square) algorithm based on the three data of the determination data, the received signal 6, and the estimated CIR used for the phase adjustment. . Here, the step size in the LMS algorithm may use a value corresponding to the number of times of demodulation.
[0033]
Thereafter, the phase adjuster 8 adjusts the phase of the received symbol using the estimated CIR updated for each symbol, and the subsequent data decision unit 9 and transmission path estimator 10 repeatedly execute the same operation as described above. I do. The symbol to be determined may be a synchronization word (SW) or a data part (D).
[0034]
Further, the frequency error detector 11 detects a phase rotation amount per symbol, that is, a frequency error, from each estimated CIR corresponding to two temporally separated symbols in the same received signal sequence. When a frequency error is detected, an estimated CIR corresponding to two temporally separated symbols in the same received signal sequence (after synchronization and in the same slot including the data portion) is required, and is not necessarily the same. It is not necessary to perform data determination on all symbols in the received signal sequence. For example, as shown in FIG. 4, the number of data determination symbols at the time of detecting a frequency error may be only N (ET) symbols in the synchronization word portion and the data portion. Further, as shown in FIG. 4, the frequency error detected here generally has a smaller value than the original frequency error due to the presence of the stationary phase error.
[0035]
FIG. 5 is a diagram showing the time constraint of the above-mentioned repetitive demodulation. In the above-mentioned repetitive demodulation, since the collective batch demodulation method is employed, data for one slot must be demodulated within a time corresponding to one slot.
[0036]
Thus, in the present embodiment, instead of detecting the frequency error using only the synchronization word as in the conventional demodulation, at least one of the synchronization word and the data portion is demodulated once. To accurately detect the frequency error. Then, by repeatedly executing this demodulation processing, a frequency error with higher accuracy is obtained. As a result, the bit error rate can be significantly improved.
[0037]
Embodiment 2 FIG.
FIG. 6 is a diagram illustrating a configuration of the demodulation device according to the second embodiment of the present invention. In FIG. 6, reference numeral 3 denotes a received signal storage circuit for storing a received signal, 4 denotes a frequency error corrector for correcting a frequency error, and 5 denotes a data demodulator for extracting transmission data from the received signal. , 12 is an operation timing control circuit for controlling operation timing, and 14 is a multiplier. The configuration of the receiving apparatus is the same as that of the first embodiment.
[0038]
The reception signal storage circuit 3 stores the reception signal in units of demodulation processing in the accumulation batch demodulation, and outputs the reception signal to the frequency error corrector 4 according to the control signal from the operation timing control circuit 12.
[0039]
The frequency error corrector 4 removes the frequency error of the operation timing control circuit 12 output from the received signal and outputs the received signal after the frequency error removal to the data demodulator 5. At this time, in the operation timing control circuit 12, the frequency error detected by the data demodulator 5 (in this case, the multiplier 14 can be omitted) or the frequency error of a constant multiple of the output of the multiplier 14 (α (N)) and the same received signal All of the previous (corrected) frequency error detected in the sequence or the frequency error of a constant multiple (α) thereof are added, and the addition result is output to the frequency error corrector 4.
[0040]
The data demodulator 5 performs data determination on the received signal after the frequency error correction. At the same time, it performs a frequency error detection process and outputs a frequency error to the operation timing control circuit 12. The detailed operation of the data demodulator 5 is the same as in FIG. 3 in the first embodiment. Also, the time constraint in the repeated demodulation is the same as in the first embodiment.
[0041]
Next, the procedure of the demodulation method according to the present embodiment will be described. FIG. 7 is a flowchart showing a processing procedure of the demodulation device.
[0042]
The operation timing control circuit 12 determines whether or not it is necessary to correct a frequency error when demodulating the same received signal sequence, that is, whether or not there is a frequency error already detected by the data demodulator 5 (step). S1).
[0043]
For example, when there is a frequency error to be corrected (Step S1, Yes), the frequency error corrector 4 corrects the received signal according to the frequency error received from the operation timing control circuit 12 (Step S2).
[0044]
If there is no frequency error to be corrected (step S1, No), or after correcting the frequency error (step S2), the data demodulator 5 demodulates the received signal output from the frequency error corrector 4 as described above. (Step S3). Then, the frequency error is detected as described above, and the result is output to the operation timing control circuit 12 (step S4).
[0045]
The operation timing control circuit 12 determines whether the demodulation processing has been completed, that is, whether the number of times of demodulation for the same received signal sequence has reached a specified number (step S5). Then, for example, when the specified number has been reached (step S5, Yes), the demodulation device ends the demodulation processing. On the other hand, if the specified number has not been reached (step S5, No), the above processing (steps S1 to S5) is repeatedly executed until the specified number is reached.
[0046]
As described above, in the present embodiment, an even more accurate frequency error is obtained by timing control by the operation timing control circuit without using a plurality of identical configurations for repeated demodulation. Thereby, the same effect as in the first embodiment can be obtained, and the circuit scale can be further reduced.
[0047]
Embodiment 3 FIG.
FIG. 8 is a diagram illustrating a configuration of the demodulation device according to the third embodiment of the present invention. 8, 3-1, 3-2,..., 3-M (M = N-1) are reception signal storage circuits for storing reception signals. ,..., 4-N are frequency error correctors for correcting frequency errors, and 5-1, 5-2, 5-3,..., 5-N are data demodulators for extracting transmission data from received signals. , 15-1, 15-2,... Are multipliers. The configuration of the receiving apparatus is the same as that of the first embodiment.
[0048]
Here, the operation of the demodulation device configured as described above will be described. First, the received signal is received by the frequency error corrector 4-1 in a unit of demodulation processing in accumulated batch demodulation. For example, in the case of quadrature amplitude modulation (QAM), the received signal is represented by I where the amplitude (I axis) of a cosine wave which is an in-phase component and Q is the amplitude (Q axis) of a sine wave which is a quadrature component. , Q) = (1, 1).
[0049]
The frequency error corrector 4-1 removes the frequency error using the received signal. Then, the received signal after the frequency error correction is output to the data demodulator 5-1 and the received signal storage circuit 3-1. Here, since there is no data demodulator at the preceding stage and no frequency error has been detected, the frequency error removal processing may be omitted. In the frequency error removal processing, the frequency error may be removed using, for example, a predetermined fixed value or a value detected by a device other than the data demodulator.
[0050]
The data demodulator 5-1 performs data determination on the received signal after removing the frequency error. At the same time, the above-described frequency error detection processing is performed using at least one of the synchronization word (SW) and the data portion (D), and a frequency error is output to the frequency error corrector 4-2. On the other hand, the received signal storage circuit 3-1 stores the received received signal after the frequency error correction, and outputs the received signal to the frequency error corrector 4-2.
[0051]
In the frequency error corrector 4-2, the frequency error detected by the data demodulator 5-1 from the received signal from the received signal storage circuit 3-1 (in this case, the multiplier 15-1 can be omitted) or the multiplier 15- A frequency error that is a constant multiple of one output (α (1)) is removed. Then, the received signal after the frequency error correction is output to the data demodulator 5-2 and the received signal storage circuit 3-2.
[0052]
Similarly, in the frequency error corrector 4-N (N is an integer of 3 or more), reception is performed using the frequency error received from the data demodulator at the preceding stage or the frequency error thereof (α (N−1)). The frequency error is removed from the received signal output from the signal storage circuit 3-M. Finally, the data demodulator 5-N performs data determination on the received signal after removing the frequency error, and outputs the data determination result 2. The detailed operation of each data demodulator is the same as in FIG. 3 in the first embodiment.
[0053]
Thus, in the present embodiment, instead of detecting the frequency error using only the synchronization word as in the conventional demodulation, at least one of the synchronization word and the data portion is demodulated once. To accurately detect the frequency error. Then, by repeatedly executing this demodulation processing, a frequency error with higher accuracy is obtained. As a result, the bit error rate can be significantly improved.
[0054]
【The invention's effect】
As described above, according to the present invention, instead of detecting the frequency error using only the synchronization word as in the conventional demodulation, at least one of the synchronization word and the data portion is performed in one demodulation. , That is, using a transmission path estimation result corresponding to two temporally separated symbols in the same received signal sequence, to detect a frequency error. As a result, there is an effect that the frequency error can be detected with higher accuracy as compared with the case where the frequency error is detected using only the synchronization word.
[0055]
According to the next invention, the phase of the data determination target symbol is adjusted based on the transmission path estimation result estimated from the received symbols. Thereby, there is an effect that the frequency error can be detected with higher accuracy.
[0056]
According to the next invention, at the time of one demodulation, a frequency error is detected by using a transmission path estimation result corresponding to two temporally separated symbols in the same received signal sequence. By repeating this demodulation process, a more accurate frequency error is obtained, and each frequency error removing means removes all frequency errors at the present stage from the received signal. As a result, the frequency error can be removed with high accuracy, and the bit error rate can be greatly improved.
[0057]
According to the next invention, based on the addition result of the frequency error detected in the previous stage or the value of the constant multiple thereof, and the previous frequency error detected in the same received signal sequence or the value of the constant multiple thereof, The frequency error is removed from the received signal. As a result, there is an effect that a highly accurate frequency error removal process can be performed.
[0058]
According to the next invention, the configuration is such that a more accurate frequency error is obtained by timing control by the timing control means without using a plurality of identical configurations for repeated demodulation. Thereby, there is an effect that the circuit scale can be further reduced.
[0059]
According to the next invention, at the time of one demodulation, a frequency error is detected by using a transmission path estimation result corresponding to two temporally separated symbols in the same received signal sequence. By repeating this demodulation process, a more accurate frequency error is obtained, and each frequency error removing means removes the frequency error from the received signal after the frequency error removal in the previous stage. As a result, the frequency error can be removed with higher accuracy, and the bit error rate can be greatly improved.
[0060]
According to the next invention, since the value of each parameter is made variable for each demodulation process, it is possible to perform a frequency error removal process with higher accuracy.
[0061]
According to the next invention, instead of detecting the frequency error using only the synchronization word as in the conventional demodulation, at the time of one demodulation, using at least one of the synchronization word and the data portion, The configuration is such that the frequency error is detected by using the transmission path estimation result corresponding to two temporally separated symbols in the same received signal sequence. As a result, there is an effect that a receiving apparatus capable of detecting a frequency error with higher accuracy can be obtained as compared with a case where a frequency error is detected using only the synchronization word.
[0062]
According to the next invention, the phase of the data determination target symbol is adjusted based on the transmission path estimation result estimated from the received symbols. As a result, it is possible to obtain a receiving device capable of detecting a frequency error with higher accuracy.
[0063]
According to the next invention, at the time of one demodulation, a frequency error is detected by using a transmission path estimation result corresponding to two temporally separated symbols in the same received signal sequence. By repeating this demodulation process, a more accurate frequency error is obtained, and each frequency error removing means removes all frequency errors at the present stage from the received signal. As a result, since a frequency error can be removed with high accuracy, it is possible to obtain a receiving device capable of greatly improving the bit error rate.
[0064]
According to the next invention, based on the addition result of the frequency error detected in the previous stage or the value of the constant multiple thereof, and the previous frequency error detected in the same received signal sequence or the value of the constant multiple thereof, The frequency error is removed from the received signal. As a result, it is possible to obtain a receiving device capable of performing a highly accurate frequency error removal process.
[0065]
According to the next invention, the configuration is such that a more accurate frequency error is obtained by timing control by the timing control means without using a plurality of identical configurations for repeated demodulation. Thereby, there is an effect that a receiving device capable of further reducing the circuit scale can be obtained.
[0066]
According to the next invention, at the time of one demodulation, a frequency error is detected by using a transmission path estimation result corresponding to two temporally separated symbols in the same received signal sequence. By repeating this demodulation process, a more accurate frequency error is obtained, and each frequency error removing means removes the frequency error from the received signal after the frequency error removal in the previous stage. As a result, since the frequency error can be removed with higher accuracy, it is possible to obtain a receiving device capable of greatly improving the bit error rate.
[0067]
According to the next invention, since the value of each parameter is made variable for each demodulation process, it is possible to perform a highly accurate frequency error elimination process, and to obtain a receiver capable of greatly improving demodulation characteristics. The effect is as follows.
[Brief description of the drawings]
FIG. 1 is a diagram illustrating a configuration of a first embodiment of a demodulation device according to the present invention.
FIG. 2 is a diagram illustrating a configuration of a receiving device including a demodulation device according to the present invention.
FIG. 3 is a diagram illustrating a configuration example of a data demodulator.
FIG. 4 is a diagram illustrating a general frequency error.
FIG. 5 is a diagram showing a time constraint of repeated demodulation.
FIG. 6 is a diagram illustrating a configuration of a demodulation device according to a second embodiment of the present invention.
FIG. 7 is a flowchart illustrating a processing procedure of the demodulation device.
FIG. 8 is a diagram illustrating a configuration of a demodulation device according to a third embodiment of the present invention.
FIG. 9 is a diagram illustrating an example of a signal format when a pilot symbol is used to detect a frequency error during demodulation.
FIG. 10 is a diagram illustrating an example of a signal format when only a synchronizing word is used to detect a frequency error during demodulation.
[Explanation of symbols]
1, 6 received signal, 2 data decision result, 3,3-1,3-2,3-M, 3-N received signal storage circuit, 4,4-1,4-2,4-3,4-N Frequency error corrector, 5,5-1,5-2,5-3,5-N data demodulator, 7 frequency error, 8 phase adjuster, 9 data discriminator, 10 transmission line estimator, 11 frequency error detection Device, 12 operation timing control circuit, 13-1, 13-2, 14, 15-1, 15-2 multiplier, 21 receiving antenna, 22 receiving device, 23 radio receiving unit, 24 demodulating device.

Claims

In a demodulation device comprising a data demodulation means for demodulating transmission data from a reception signal having a synchronization word and a data portion,
The data demodulation means,
Transmission path estimation means for performing transmission path estimation processing based on the received signal,
Frequency error detection means for detecting a frequency error using the transmission path estimation result corresponding to a plurality of temporally separated symbols in the received signal sequence,
A demodulation device comprising:

The data demodulation means,
A phase adjustment unit that adjusts the phase of the data determination target symbol based on a transmission path estimation result estimated from the received symbols,
Data determination means for determining the input signal after the phase adjustment in symbol units;
With
The demodulator according to claim 1, wherein the transmission path estimating means performs a transmission path estimation process using the determination result and the received signal before the phase adjustment.

Said data demodulation means,
Frequency error removing means for removing a frequency error from a received signal based on the frequency error detected by the frequency error detecting means at the preceding stage, and outputting the received signal after removing the frequency error to the data demodulating means at the next stage,
The demodulation device according to claim 1 or 2, comprising a plurality of combinations of (1) and (2).

The frequency error removing means, based on a result of addition of the frequency error or a constant multiple thereof and a previous frequency error detected in the same received signal sequence or a constant multiple thereof, calculates a frequency from a received signal. The error is removed, and the received signal after the frequency error is removed is output to the next-stage data demodulating means,
4. The method according to claim 3, wherein the demodulation process and the frequency error elimination process are repeatedly performed over the plurality of stages, and the data demodulation unit in the last stage demodulates transmission data from the reception signal after the frequency error elimination in the previous stage. Demodulator.

Further, based on a result of addition of the frequency error or a value of a constant multiple thereof, and a previous frequency error detected in the same received signal sequence or a value of a constant multiple thereof, all of the received signals at the present stage are obtained from the received signal. Frequency error removing means for removing the frequency error and outputting the received signal after the frequency error removal to the data demodulating means,
Timing control means for feeding back the frequency error of the data demodulation means output to the frequency error removal means at a predetermined timing,
With
3. The demodulation device according to claim 1, wherein the frequency error elimination process generated by the feedback and the demodulation process of the received signal after the frequency error elimination process are repeatedly performed a predetermined number of times.

Said data demodulation means,
A frequency error of the output of the data demodulation means or a value multiplied by a constant multiple thereof is removed from the reception signal after the frequency error removal in the previous stage, and the received signal after the frequency error removal is input to the data demodulation means in the next stage. Means,
With multiple combinations of
3. The method according to claim 1, wherein the demodulation process and the frequency error elimination process are repeatedly performed in the plurality of stages, and the data demodulation unit in the final stage demodulates transmission data from the reception signal after the frequency error elimination in the previous stage. 3. The demodulator according to claim 1.

The value of at least one parameter of the constant, the step size when the LMS algorithm is used in the transmission path estimating means, and the number of symbols for which data judgment is performed by the frequency error detecting means is changed for each demodulation process. The demodulation device according to claim 3, wherein the demodulation device is enabled.

In a receiving device provided with a data demodulation means for demodulating transmission data from a reception signal after predetermined radio reception processing,
The data demodulation means,
Transmission path estimation means for performing transmission path estimation processing based on the received signal,
Frequency error detection means for detecting a frequency error using a transmission path estimation result corresponding to a plurality of temporally separated symbols in the received signal sequence,
A receiving device comprising:

The data demodulation means,
A phase adjustment unit that adjusts the phase of the data determination target symbol based on a transmission path estimation result estimated from the received symbols,
Data determination means for determining the received signal after the phase adjustment in symbol units,
With
The receiving apparatus according to claim 8, wherein the transmission path estimating means performs a transmission path estimation process using the determination result and the received signal before the phase adjustment.

Said data demodulation means,
Frequency error removing means for removing a frequency error from a received signal based on the frequency error detected by the frequency error detecting means at the preceding stage, and outputting the received signal after removing the frequency error to the data demodulating means at the next stage,
The receiving device according to claim 8, wherein the receiving device includes a plurality of stages.

The frequency error removing means, based on a result of addition of the frequency error or a constant multiple thereof and a previous frequency error detected in the same received signal sequence or a constant multiple thereof, calculates a frequency from a received signal. The error is removed, and the received signal after the frequency error is removed is output to the next-stage data demodulating means,
11. The method according to claim 10, wherein the demodulation process and the frequency error removal process are repeatedly performed in the plurality of stages, and the data demodulation unit in the last stage demodulates transmission data from the reception signal after the frequency error removal in the previous stage. Receiving device.

Further, based on a result of addition of the frequency error or a value of a constant multiple thereof, and a previous frequency error detected in the same received signal sequence or a value of a constant multiple thereof, all of the received signals at the present stage are obtained from the received signal. Frequency error removing means for removing the frequency error and outputting the received signal after the frequency error removal to the data demodulating means,
Timing control means for feeding back the frequency error of the data demodulation means output to the frequency error removal means at a predetermined timing,
With
The receiving apparatus according to claim 8, wherein the frequency error removal processing generated by the feedback and the demodulation processing of the received signal after the frequency error removal processing are repeatedly performed a predetermined number of times.

Said data demodulation means,
A frequency error of the output of the data demodulation means or a value multiplied by a constant multiple thereof is removed from the reception signal after the frequency error removal in the previous stage, and the received signal after the frequency error removal is input to the data demodulation means in the next stage. Means,
With multiple combinations of
10. The method according to claim 8, wherein the demodulation process and the frequency error elimination process are repeatedly performed over the plurality of stages, and the data demodulation unit at the last stage demodulates the transmission data from the reception signal after the frequency error elimination at the previous stage. The receiving device according to claim 1.

The value of at least one parameter of the constant, the step size when the LMS algorithm is used in the transmission path estimating means, and the number of symbols for which data judgment is performed by the frequency error detecting means is changed for each demodulation process. The receiving device according to claim 10, wherein the receiving device is enabled.