JP2023071215A - demodulation circuit - Google Patents

Abstract

To achieve both high detection accuracy and a reduced pull-in time by a same control flow independently of a symbol rate.SOLUTION: A demodulation circuit has: an automatic frequency control circuit 2 that corrects a frequency error of a reception signal; a roll-off filter 3 provided at a rear stage of the automatic frequency control circuit 2 to apply band limit processing on the reception signal and output the resultant; and a carrier reproduction circuit 5 provided at a rear stage of the roll-off filter 3 to correct a phase error of the reception signal. The automatic frequency control circuit 2 comprises: a frequency controller 21 that generates a plurality of offset frequencies while shifting the frequency; a numerical value control oscillator 22 for AFC (automatic frequency control) that converts each offset frequency into a complex number; and a multiplier 23 for AFC that applies complex multiplication processing on the reception signal using the complex number. The automatic frequency control circuit 2 corrects the frequency error of the reception signal using an offset frequency at maximum intensity of the reception signal outputted from the roll-off filter 3.SELECTED DRAWING: Figure 1

Description

The present invention relates to a demodulator circuit that is applied to wireless communication performed via a communication satellite, for example, and realizes synchronous detection.

In a wireless communication system in which wireless communication is performed between a transmitting-side device and a receiving-side device via a communication satellite, the total frequency error between transmission and reception is due to the large frequency error of the communication satellite. It may be out of range. In order to cope with a radio communication system in which there is a local frequency error outside the frequency pull-in range for carrier recovery of the receiver demodulator, the receiving side device searches for the frequency error by changing the local frequency within a range that allows frequency pull-in for carrier recovery. An Automatic Frequency Controller (AFC) circuit is used for the purpose of coarsely adjusting the local frequency error by As a conventional automatic frequency control device, the C/N of the control channel signal notified from the C/N measurement unit and the U/W (unique word) detection unit corresponding to the predetermined C/N value are notified The number of times of U/W detection is collated, and the adjustment procedure of outputting an oscillation frequency control signal that reduces Δf, which is the difference between the carrier frequency and the current local signal, to the NCO and correcting the frequency is repeated until the required number of times is satisfied. There is known a device that, when a predetermined number of U/W detections is obtained, determines that the carrier capture and lock procedures required for AFC are completed, and shifts to a tracking mode (see Patent Document 1).

JP 2011-87191 A

By the way, in conventional automatic frequency control processing such as that disclosed in Patent Document 1, frequency error detection is determined based on whether a unique word can be detected. Therefore, there is a problem that it takes a long time to lock-in at a low symbol rate, which takes a long time for synchronization. Further, in a wireless communication system such as a satellite communication system that supports communication at various symbol rates (symbol frequencies), the lock-in range and lock-in time greatly differ depending on the symbol rate. For this reason, when the symbol rate is low, the initial pull-in of automatic frequency control takes a long time due to the long pull-in time of carrier recovery, and the wait time becomes longer when the receiving side device searches for the frequency error. The problem is that it takes time. Also, when the symbol rate is high, there are cases where the correct frequency error cannot be detected because the carrier synchronization pull-in range is wide and the pull-in time is short. There is a problem that complicated control such as re-inputting and waiting again for synchronization of carrier reproduction is required.

SUMMARY OF THE INVENTION Accordingly, it is an object of the present invention to provide a demodulation circuit capable of achieving both high detection accuracy and shortened lock-in time with the same control flow regardless of the symbol rate.

In order to solve the above problems, the demodulation circuit according to the present invention includes an automatic frequency control circuit for correcting a frequency error of a received signal, and a band limiting process for the received signal provided after the automatic frequency control circuit. and a carrier recovery circuit that is provided after the roll-off filter and corrects the phase error of the received signal, and the automatic frequency control circuit shifts the frequency while a frequency control unit that generates a plurality of offset frequencies; a numerically controlled oscillator that converts the offset frequencies into complex numbers; and a multiplier that performs complex multiplication processing on the received signal using the complex numbers, The frequency error of the received signal is corrected using the offset frequency when the intensity of the received signal output from the off-filter is maximized.

In the demodulation circuit according to the present invention, the intensity of the received signal is determined by an intensity detector connected between the roll-off filter and the carrier recovery circuit and receiving the received signal output from the roll-off filter. may be measured.

The demodulation circuit according to the present invention is provided between the roll-off filter and the carrier regeneration circuit and receives the received signal output from the roll-off filter, and the automatic gain control section receives the input of the received signal to determine the strength of the received signal. may be measured.

The demodulation circuit according to the present invention may measure the strength of a signal whose frequency band is narrower than the frequency band used for communication.

According to the demodulation circuit of the present invention, the frequency error can be detected without relying on clock synchronization, so it is possible to detect the frequency error at high speed even at a low symbol rate. Regardless, it is possible to achieve both high detection accuracy and shortened pull-in time with the same control flow. According to the demodulation circuit according to the present invention, control for correcting frequency errors that differ for each symbol frequency becomes unnecessary.

According to the demodulation circuit of the present invention, automatic frequency control is completed without carrier synchronization (correction of phase error) in the carrier recovery circuit and known pattern synchronization (phase synchronization/asynchronization detection/determination) in the synchronization detection section. Therefore, it is possible to shorten the pull-in time.

According to the demodulation circuit according to the present invention, when the strength of the received signal is measured by the automatic gain control section, the complexity of the circuit configuration can be suppressed while achieving high detection accuracy and shortening of the pull-in time. It is possible to achieve both

According to the demodulation circuit according to the present invention, when the strength of a signal whose frequency band is narrower than the frequency band used in communication is measured, the strength/level peak of the signal of the channel to be detected can be detected. It is possible to reliably detect it.

1 is a functional block diagram showing a schematic configuration of a demodulation circuit according to Embodiment 1 of the present invention; FIG. It is a functional block diagram showing a schematic configuration of a demodulation circuit according to Embodiment 2 of the present invention. FIG. 4 is a diagram showing an example of the relationship between a detection target channel and other channels;

BEST MODE FOR CARRYING OUT THE INVENTION The present invention will be described below based on the illustrated embodiments.

(Embodiment 1)
FIG. 1 is a functional block diagram showing a schematic configuration of a demodulation circuit 1 according to Embodiment 1 of the present invention. The demodulation circuit 1 is, for example, a receiving device (or , a mechanism for processing received signals in each device when two-way communication is performed between a transmitting device and a receiving device).

The demodulator circuit 1 is a mechanism for performing synchronous detection of modulated signals, and mainly includes an automatic frequency control circuit 2, a roll-off filter 3, an intensity detector 4, a carrier recovery circuit 5, and a demodulator 6. , and a synchronization detector 7 . Although the modulation/demodulation method in the present invention is not limited to a specific method, for example, a QPSK (Quadrature Phase Shift Keying) method can be used.

In an automatic frequency controller (AFC) circuit 2, for example, a radio frequency (RF) radio signal received via an antenna is frequency-converted into an intermediate frequency (IF) signal. A digital reception signal (modulation signal) that has been analog-to-digital converted is also input.

The automatic frequency control circuit 2 controls the frequency error (in other words, frequency deviation), and mainly includes a frequency control unit 21, a numerically controlled oscillator 22 for AFC, and a multiplier 23 for AFC.

The frequency control unit 21 outputs frequency information corresponding to the frequency error between the transmission local frequency of the transmission side device and the reception local frequency of the reception side device.

A numerically controlled oscillator 22 (NCO: Numerically Controlled Oscillator) for AFC receives frequency information output from the frequency control section 21, converts the frequency information into a complex number, and outputs the complex number.

AFC multiplier 23 receives a received signal (modulated signal) input to automatic frequency control circuit 2 and receives a complex input output from numerically controlled oscillator 22 for AFC. The modulated signal) is subjected to complex multiplication processing (that is, complex multiplication processing according to the frequency information) using the complex number, and output.

In the present invention, the automatic frequency control circuit 2 is not provided with a synchronization determination circuit for detecting and determining synchronization/asynchronization of frequencies.

The roll-off filter 3 (ROF: Roll-Off Filter) is composed of a low-pass filter (LPF: Low Pass Filter) realized as a finite-length impulse response, and the automatic frequency control circuit 2 (specifically, for AFC It receives the input of the signal output from the multiplier 23), applies band-limiting processing to the signal, and outputs the signal.

The intensity detector 4 is connected between the roll-off filter 3 and the carrier regeneration circuit 5, receives the signal output from the roll-off filter 3, and detects the intensity/level (specifically, power ) is measured.

A carrier recovery (CR) circuit 5 recovers the phase of the transmission signal/carrier wave from the transmitting device and the phase of the received signal (modulated signal)/carrier wave at the receiving device included in the signal output from the roll-off filter 3. It is a mechanism for removing/correcting the phase error (in other words, the phase error/shift of the received signal with respect to the ideal phase) between the phase error detector 51, the low-pass filter 52, It has a numerically controlled oscillator 53 for CR and a multiplier 54 for CR.

The phase error detection unit 51 receives the signal output from the CR multiplier 54 and detects the phase error included in the signal (that is, the phase error/shift of the signal with respect to the ideal phase). and outputs a signal indicative of the phase error.

The low-pass filter 52 (LPF) receives the signal indicating the phase error output from the phase error detecting section 51, performs band-limiting processing on the signal indicating the phase error, and outputs the signal (specifically, essentially pass only low-frequency components).

A numerically controlled oscillator 53 (NCO: Numerically Controlled Oscillator) for CR receives a signal indicating a phase error output from the low-pass filter 52, converts the phase error into a complex number, and outputs the complex number.

The multiplier 54 for CR receives the input of the signal output from the roll-off filter 3 and also receives the input of the complex number output from the numerically controlled oscillator 53 for CR. Multiplication processing (that is, complex multiplication processing according to the phase error) is performed and output.

The demodulator 6 receives the signal output from the carrier recovery circuit 5 (specifically, the multiplier 54 for CR), detects the signal, and demodulates it into predetermined data (for example, QPSK demodulation). output as a signal frame (bit string signal).

A synchronization detector 7 receives the input of the signal frame output from the demodulator 6, and detects the phase using detection of a known pattern such as a unique word (UW), which is a synchronization signal included in the signal frame. synchronous/asynchronous detection/judgment processing.

The demodulation circuit 1 according to the first embodiment includes an automatic frequency control circuit 2 that corrects a frequency error of a received signal (modulated signal), and a frequency control circuit that is provided after the automatic frequency control circuit 2 and controls the frequency of the received signal. The automatic frequency control circuit 2 has a roll-off filter 3 that performs limiting processing for output, and a carrier recovery circuit 5 that is provided after the roll-off filter 3 and corrects the phase error of the received signal. , a numerically controlled oscillator 22 for AFC that converts the offset frequency into a complex number, and an AFC that performs complex multiplication processing on the received signal using the complex number. and a multiplier 23 for correcting the frequency error of the received signal using the offset frequency when the strength of the received signal output from the roll-off filter 3 is maximized, and the roll-off filter 3 and the carrier The intensity of the received signal is measured by an intensity detector 4 connected between the reproducing circuit 5 and supplied with the received signal output from the roll-off filter 3 .

When starting the automatic frequency control process, the frequency control part 21 outputs a signal indicating the start of the automatic frequency control process to the intensity detection part 4 .

As a process of automatic frequency control, the frequency control unit 21 performs a predetermined unit shift amount so as to cover the expected frequency error range (or the range in which the demodulation circuit 1 can pull in the frequency for carrier reproduction). (In other words, a plurality of offset frequencies (in other words, a plurality of frequencies for performing frequency search/frequency sweep) are sequentially output while shifting/changing the frequency by the step amount or pitch amount.

Let femax be the absolute value of the maximum expected frequency error, and let Δf be the unit shift amount of the frequency.

femax and Δf are not limited to specific values. It is appropriately set to an appropriate value after taking into account the possibility of accurate synchronization and the prevention of an extremely long processing time.

The frequency control unit 21 sequentially outputs offset frequencies Δf_n (where n=1, 2, 3, .

For example, the frequency control unit 21 adjusts the offset frequency Δf_n (where n=1, 2 , 3, . . . ) are repeated, and the values of the calculated offset frequencies Δf_n are sequentially output. The offset frequency Δf_n corresponds to the frequency error between the transmission local frequency of the transmission side device and the reception local frequency of the reception side device.
(Formula 1) Δf_n = -femax + Δf x (n-1)
Here, Δf_n: Offset frequency [kHz]
femax: Absolute value of maximum frequency error [kHz]
Δf: Unit shift amount of frequency [kHz]
n: ordinal number (n = 1, 2, 3, ...)

The frequency control unit 21 repeats the calculation of the following formula 2A until the calculated value of the offset frequency Δf_n becomes greater than +femax (where n=1, 2, 3, . . . ) to determine the value of the offset frequency Δf_n. are sequentially output, and then the calculation of the following formula 2B is repeated until the value of the calculated offset frequency Δf_n becomes smaller than -femax (where n = 1, 2, 3, . . . ). You may make it output the value of (DELTA)f_n sequentially.
(Formula 2A) Δf_n = Δf×(n−1)
(Formula 2B) Δf_n = Δf×(1−n)

The numerically controlled oscillator 22 for AFC sequentially calculates the phase error Δθ according to Equation 3 below using the values of the offset frequencies Δf_n sequentially output from the frequency control section 21 . A clock that generates a symbol clock, for example, is used as the reference clock Fref.
(Equation 3) Δθ = 360/(Fref/Δf_n)
Here, Δθ : phase error [deg]
Fref: Reference clock [kHz]
Δf_n: Offset frequency [kHz]

Then, the numerically controlled oscillator 22 for AFC sequentially converts the calculated phase error Δθ into a complex number using a table or the like and outputs the complex number.

The multiplier 23 for AFC performs complex multiplication processing on the received signal (modulated signal) input to the automatic frequency control circuit 2 using complex numbers sequentially output from the numerically controlled oscillator 22 for AFC, and sequentially Output.

As described above, from the automatic frequency control circuit 2 (specifically, the multiplier 23 for AFC), the offset frequency Δf_n (where n=1, 2, 3, . Signals after complex multiplication processing corresponding to each are sequentially output. Signals sequentially output from the automatic frequency control circuit 2 are input to the roll-off filter 3 , and signals output from the roll-off filter 3 are sequentially supplied to the intensity detector 4 .

The intensity detection unit 4 has a counter function and a function of counting a counter value C (where C=0, 1, 2, 3, . . . ). The intensity detection unit 4 sets the counter value C to the initial value 0 upon receiving the signal indicating the start of the automatic frequency control process output from the frequency control unit 21 .

The intensity detector 4 also detects the value of the intensity/level of the signal measured each time the signal sequentially output from the roll-off filter 3 is supplied, and the counter value C obtained by adding 1 to the original counter value C. Equipped with a function to store combinations in chronological order.

Each time the signal sequentially output from the roll-off filter 3 is supplied, the intensity detection unit 4 adds 1 to the counter value C and measures the intensity/level of the signal, and measures the intensity of the signal obtained as the measurement result. The combination of the / level value (specifically, the power value) and the counter value C to which 1 is added is retained in time series.

The counter value C to which 1 is added is equal to the value of the ordinal number n of the offset frequency Δf_n corresponding to the signals sequentially output from the roll-off filter 3 when using the above equation 1.

The intensity detection unit 4 has a function of detecting the intensity/level peak of the signal obtained as the measurement result. counter value C (referred to as “peak time counter value Cpeak”) is output to the frequency control unit 21 .

The intensity detection unit 4 may output the peak-time counter value Cpeak to the frequency control unit 21 when it is determined that the peak of the intensity/level of the signal has been detected. In this case, the frequency control unit 21 ends the calculation of the offset frequency Δf_n at the time of receiving the input of the peak counter value Cpeak, and does not calculate the offset frequency Δf_n for part of the range from -femax to +femax. Sometimes.

The frequency control unit 21 receives the input of the peak counter value Cpeak output from the intensity detection unit 4, calculates the offset frequency Δf_n according to the above equation 1 using the peak counter value Cpeak as n, and determines the reception frequency error. Output as fre.

Note that when the above formulas 2A and 2B are used in the calculation of the offset frequency Δf_n, the frequency control unit 21 holds the value of the ordinal number n immediately before the value of the offset frequency Δf_n in the calculation result becomes greater than +femax, and the intensity When the peak hour counter value Cpeak output from the detection unit 4 is greater than the value of the held ordinal number n, the value obtained by subtracting the held ordinal number n value from the peak hour counter value Cpeak is n is used to calculate the offset frequency Δf_n (ie, the received frequency error fre) according to Equation 2B above.

As described above, the value of the reception frequency error fre corresponding to the frequency error between the transmission local frequency of the transmission side device and the reception local frequency of the reception side device is output to the numerically controlled oscillator 22 for AFC.

Subsequently, the numerically controlled oscillator 22 for AFC calculates the phase error Δθ according to Equation 4 below using the reception frequency error fre.
(Formula 4) Δθ = 360/(Fref/fre)
Here, Δθ : phase error [deg]
Fref: Reference clock [kHz]
fre : Receiving frequency error (offset frequency) [kHz]

The numerically controlled oscillator 22 for AFC converts the calculated phase error Δθ into a complex number using a table or the like and outputs the complex number.

Subsequently, the multiplier 23 for AFC performs complex multiplication processing (i.e., , complex multiplication processing according to the phase error Δθ corresponding to the received frequency error fre) and output. This completes the automatic frequency control process.

A signal output from the automatic frequency control circuit 2 (specifically, the multiplier 23 for AFC) is input to the carrier regeneration circuit 5 via the roll-off filter 3, and the carrier regeneration circuit 5, the demodulator 6, and the Processing by the synchronization detector 7 is performed.

(Embodiment 2)
FIG. 2 is a functional block diagram showing a schematic configuration of demodulation circuit 1 according to Embodiment 2 of the present invention. The demodulation circuit 1 according to the second embodiment does not have the intensity detector 4, has the automatic gain controller 8, and the frequency controller 21 is output from the automatic gain controller 8 instead of the intensity detector 4. The input of the peak time counter value Cpeak, and the input of the signal output from the automatic gain control unit 8 instead of the roll-off filter 3 to the carrier recovery circuit 5 (specifically, the multiplier 54 for CR). Although the configuration is different from that of the above-described first embodiment in terms of receiving, other configurations are the same as those of the above-described first embodiment. Description is omitted.

A demodulation circuit 1 according to Embodiment 2 includes an automatic frequency control circuit 2 for correcting a frequency error of a received signal (modulated signal), and a band limiting process for the received signal provided after the automatic frequency control circuit 2. and a carrier regeneration circuit 5 provided after the roll-off filter 3 and correcting the phase error of the received signal, and the automatic frequency control circuit 2 shifts the frequency. A frequency control unit 21 for generating a plurality of offset frequencies while increasing the frequency, a numerically controlled oscillator 22 for AFC for converting the offset frequencies into complex numbers, and an AFC for performing complex multiplication processing on the received signal using the complex numbers. and a multiplier 23 for correcting the frequency error of the received signal using the offset frequency when the strength of the received signal output from the roll-off filter 3 is maximized, and the roll-off filter 3 and the carrier recovery circuit. 5 and receives the input of the received signal outputted from the roll-off filter 3, the strength of the received signal is measured.

An automatic gain control (AGC) unit 8 is provided between the roll-off filter 3 and the carrier regeneration circuit 5, receives the input of the signal output from the roll-off filter 3, and adjusts the intensity/ Adjust the level (specifically, power).

Specifically, the automatic gain control unit 8 measures the strength/level of the signal output from the roll-off filter 3, and also measures the strength/level of the signal obtained as a measurement result and a predetermined target signal level (for example, A signal level predetermined as an appropriate level for processing/circuits subsequent to the automatic gain control unit 8) is detected.

The automatic gain control unit 8 further determines a gain based on the detected level difference so that the strength/level of the signal output from the roll-off filter 3 converges to the target signal level, Using the determined gain, the strength/level of the signal output from the roll-off filter 3 is amplified and output.

In the second embodiment, when starting the automatic frequency control process, the frequency control section 21 outputs a signal indicating the start of the automatic frequency control process to the automatic gain control section 8 .

In the second embodiment, as in the first embodiment, an offset frequency Δf_n (where , n=1, 2, 3, . Signals sequentially output from the automatic frequency control circuit 2 are input to the roll-off filter 3 , and signals output from the roll-off filter 3 are sequentially input to the automatic gain control section 8 .

The automatic gain control unit 8 has a counter function and a function of counting a counter value C (where C=0, 1, 2, 3, . . . ). The automatic gain control unit 8 sets the counter value C to an initial value of 0 upon receiving the signal indicating the start of the automatic frequency control process output from the frequency control unit 21 .

The automatic gain control unit 8 also obtains a counter value C obtained by adding 1 to the intensity/level value of the signal measured each time the signal sequentially output from the roll-off filter 3 is supplied, and the original counter value C. It has a function to hold the combination of in chronological order.

The automatic gain control unit 8 adds 1 to the counter value C each time the signal sequentially output from the roll-off filter 3 is input, measures the strength/level of the signal, and measures the strength/level of the signal obtained as a measurement result. Combinations of strength/level values (specifically, power values) and counter values C to which 1 is added are retained in time series.

The counter value C to which 1 is added is equal to the value of the ordinal number n of the offset frequency Δf_n corresponding to the signals sequentially output from the roll-off filter 3 when using the above equation 1.

The automatic gain control unit 8 has a function of detecting a peak of the intensity/level of the signal obtained as the measurement result, and when the peak of the intensity/level of the signal is detected, the intensity/level of the signal corresponding to the peak is detected. The combined counter value C (referred to as “peak counter value Cpeak”) is output to the frequency control section 21 .

The automatic gain control section 8 may output the peak-time counter value Cpeak to the frequency control section 21 when it determines that the peak of the strength/level of the signal has been detected. In this case, the automatic gain control unit 8 ends the calculation of the offset frequency Δf_n at the time of receiving the input of the peak counter value Cpeak, and calculates the offset frequency Δf_n for a part of the range from -femax to +femax. sometimes not.

Alternatively, the automatic gain control unit 8 has a function of retaining, in time series, a combination of a gain (gain) value calculated when performing automatic gain control and the counter value C obtained by adding 1 to the value of the gain. It has a function to detect a minimum value, and when the minimum value of the gain is detected, the counter value C combined with the gain corresponding to the minimum value (referred to as "minimum counter value Cmin") is sent to the frequency control unit 21. You can also output

The frequency control unit 21 receives the input of the peak counter value Cpeak (or the minimum counter value Cmin) output from the automatic gain control unit 8, and adjusts the peak counter value Cpeak (or the minimum counter value Cmin). is used as n, the offset frequency Δf_n is calculated according to Equation 1 above and output as the received frequency error fre.

Note that when the above formulas 2A and 2B are used in the calculation of the offset frequency Δf_n, the frequency control unit 21 holds the value of the ordinal number n immediately before the value of the offset frequency Δf_n in the calculation result becomes larger than +femax, and automatically When the peak counter value Cpeak (or the minimum counter value Cmin) output from the gain control unit 8 is greater than the held ordinal value n, the peak counter value Cpeak (or the minimum counter value Cmin Using the value obtained by subtracting the value of the held ordinal number n from the hour counter value Cmin) as n, the offset frequency Δf_n (that is, the reception frequency error fre) is calculated according to the above equation 2B.

As described above, the value of the reception frequency error fre corresponding to the frequency error between the transmission local frequency of the transmission side device and the reception local frequency of the reception side device is output to the numerically controlled oscillator 22 for AFC.

Subsequently, the numerically controlled oscillator 22 for AFC calculates the phase error Δθ according to the above equation 4 using the value of the reception frequency error fre, converts the calculated phase error Δθ into a complex number using a table or the like, and outputs it. do.

Subsequently, the multiplier 23 for AFC performs complex multiplication processing (i.e., , complex multiplication processing according to the phase error Δθ corresponding to the received frequency error fre) and output. This completes the automatic frequency control process.

A signal output from the automatic frequency control circuit 2 (specifically, the multiplier 23 for AFC) is input to the carrier regeneration circuit 5 via the roll-off filter 3, and the carrier regeneration circuit 5, the demodulator 6, and the Processing by the synchronization detector 7 is performed.

(Use of signals with narrow frequency bands)
For example, as shown in FIG. 3A, the center frequency of the channel to be detected (in other words, the target of synchronous detection, for frequency error detection) (for example, the numerically controlled oscillator for AFC according to the transmission local frequency of the transmission side device 22 oscillation frequencies (local frequencies)) plus the center frequencies of other (eg, adjacent) channels may be included between -femax and +femax.

In this case, a plurality of intensity/level peaks of the signal exist, and in the intensity detector 4 and the automatic gain controller 8, the intensity/level peaks of the signals of other channels, not the signal of the channel to be detected, are detected. may be detected (in other words, selected).

Therefore, as shown in FIG. 3B, a signal with a narrower frequency band than the frequency band used in communication is transmitted from the transmitting device to the channel to be detected, and the signal with the narrower frequency band is transmitted from the receiving device. It may be used.

The receiving device (specifically, the intensity detector 4 and the automatic gain controller 8) detects the width of the intensity/level peaks of other signals among the plurality of signal intensity/level peaks (in other words Then, a signal having a narrower peak width than the widening of the hem is specified as the signal of the detection target channel, and a peak hour counter is calculated based on the intensity/level peak of the specified detection target channel signal. Specify the value Cpeak (or the minimum counter value Cmin).

In this case, a signal with a narrow frequency band is transmitted from the transmitting device for a predetermined period of time, or notifies that the process of detecting the strength/level peak of the signal for the channel to be detected has ended. until the signal is sent from the receiving device to the sending device.

According to the demodulation circuits 1 according to Embodiments 1 and 2, it is possible to detect frequency errors without relying on clock synchronization. makes it possible to achieve both high detection accuracy and shortened lock-in time with the same control flow regardless of the symbol rate. According to the demodulation circuits 1 according to Embodiments 1 and 2, control for correcting frequency errors that differ for each symbol frequency becomes unnecessary.

According to the demodulation circuit 1 according to Embodiments 1 and 2, carrier synchronization (correction of phase error) in the carrier reproduction circuit 5 and known pattern synchronization (detection and determination of phase synchronization/asynchronization) in the synchronization detection unit 7 are performed. Since the automatic frequency control is completed without any delay, it is possible to shorten the pull-in time.

According to the demodulation circuit 1 according to the second embodiment, since the automatic gain control section 8, which is considered to be provided when the demodulation circuit requires level adjustment, is used, the circuit configuration is complicated. It is possible to realize both high detection accuracy and shortening of the pull-in time while suppressing the occurrence of the

According to the demodulation circuits 1 according to Embodiments 1 and 2, when the strength of a signal whose frequency band is narrower than the frequency band used in communication is measured, the strength of the signal for the detection target channel is / level peak can be reliably detected.

Although the embodiments of the present invention have been described above, the specific configuration is not limited to the above-described embodiments. Included in the invention.

For example, the carrier reproducing circuit 5, the demodulator 6, and the synchronization detector 7 are not limited to specific configurations in the present invention, and are not limited to the configurations in the above embodiments.

1 demodulation circuit 2 automatic frequency control circuit (AFC)
21 frequency control unit 22 numerically controlled oscillator (NCO) for AFC
23 multiplier for AFC 3 roll-off filter (ROF)
4 intensity detector 5 carrier regeneration circuit (CR)
51 phase error detector 52 low-pass filter 53 numerically controlled oscillator (NCO) for CR
54 multiplier for CR 6 demodulator 7 synchronization detector 8 automatic gain controller

Claims (4)

an automatic frequency control circuit that corrects the frequency error of the received signal;
a roll-off filter that is provided after the automatic frequency control circuit and that applies band-limiting processing to the received signal and outputs the received signal;
a carrier regeneration circuit that is provided after the roll-off filter and corrects a phase error of the received signal;
The automatic frequency control circuit is
a frequency control unit that generates a plurality of offset frequencies while shifting the frequency;
a numerically controlled oscillator that converts the offset frequency into a complex number;
a multiplier that performs complex multiplication processing on the received signal using the complex number,
correcting the frequency error of the received signal using the offset frequency when the strength of the received signal output from the roll-off filter is maximized;
A demodulation circuit characterized by: The strength of the received signal is measured by a strength detector connected between the roll-off filter and the carrier recovery circuit and receiving the received signal output from the roll-off filter.
2. The demodulator circuit according to claim 1, wherein: The strength of the received signal is measured by an automatic gain control unit that is provided between the roll-off filter and the carrier recovery circuit and receives the input of the received signal output from the roll-off filter.
2. The demodulator circuit according to claim 1, wherein: The strength is measured for a signal with a narrower frequency band than the frequency band used in communication,
4. The demodulator circuit according to any one of claims 1 to 3, characterized in that:

Images