JP5761748B2 - Symbol synchronization acquisition system and method - Google Patents

Description

  The present invention relates to a symbol synchronization acquisition system and method, and more particularly to a symbol synchronization acquisition system and method in a digital demodulator used in a wireless communication system or the like.

  The demodulator in today's general digital communication system estimates the time of occurrence of each symbol in the time series of the received signal and demodulates it from the extracted symbol sequence while utilizing the structural characteristics of the received signal itself. I do. The symbol time is estimated because each symbol is transmitted at an equal time interval. Therefore, the symbol transmission timing included in the feature quantity sequence determined depending on the modulation format of the received signal includes symbol extraction timing that is repeated at a constant period. This is performed by synchronizing with the symbol clock component corresponding to the period. Usually, symbol synchronization in digital communication refers to this.

  What is most suitable as the time series of this feature amount varies depending on the modulation format of digital communication and the situation assumed for the communication channel and communication equipment, but basically, it depends on the modulation format in advance (that is, , Before the start of demodulation). For example, in phase shift (PSK) modulation, a time series of amplitude components of received signals or square values (power) of amplitude components is often used as a time series of feature values.

  In any case, the achievement of symbol synchronization under these circumstances results in the achievement of highly accurate estimation of the frequency of the symbol clock component in the time series of the feature quantity and its phase at each time.

  However, in reality, since the symbol clock fluctuates due to various factors in any situation, adaptive control is required for the symbol synchronization tracking mechanism, and the operation of the symbol synchronization mechanism is stable. This is one of the most important factors that affect the demodulation performance.

  Various methods for achieving this object have been devised in the past, but many are based on sequential phase control using a PLL (Phase Locked Loop) circuit.

  FIG. 8 shows a block diagram of an example of a general digital demodulator, and shows an example of a configuration for symbol synchronization acquisition and tracking function for symbol extraction used in the digital demodulator.

  In FIG. 8, the received signal becomes a baseband demodulated signal by passing through the process from the frequency shift circuit 1 to the matched filter 4 through the resampler 2 and the baseband demodulating circuit 3. The details of these parts 1 to 4 are the same as those of the present invention, and will be described in the description of FIGS.

  The baseband demodulated signal is input to the symbol extraction circuit 10, and is also input to the symbol synchronization function unit for symbol extraction in the symbol extraction circuit 10 through the feature amount series calculation circuit 6. The symbol synchronization function unit is composed of a symbol synchronization acquisition / follow-up circuit 15 and a clock generation circuit 9. Specific examples of the symbol synchronization acquisition / follow-up circuit 15 and the clock generation circuit 9 are the same as those shown in FIG. It will be described later.

  Each time the symbol extraction signal (pulse) output from the clock generation circuit 9 is generated, the symbol extraction circuit 10 samples the baseband signal to make a symbol series. The symbol series is output as a demodulation result through the carrier synchronization circuit 11 and the symbol determination circuit 12.

  The symbol synchronization acquisition / follow-up circuit 15 obtains the phase difference between the feature quantity sequence of the baseband signal and the complex sine wave signal generated by the clock generation circuit 9, and feeds back this value. The frequency and phase of the clock generation circuit 9 are corrected.

  FIG. 9 shows a specific example of the clock generation circuit 9 and the symbol synchronization acquisition / tracking circuit 15 in FIG. The feature amount series from the feature series calculation circuit 6 is input to the exponent-weighted integration circuit via the multiplier 81. This exponential weighted integration circuit has a well-known configuration, and includes an adder 82, a delay unit 83, and an exponential weighting coefficient unit 84, and performs weighted integration with the feature sequence of the previous symbol. , And input to the phase calculation circuit 85.

  Based on the calculation result by the phase calculation circuit 85, the phase correction and frequency correction of the complex sine wave oscillator 91 are performed via the buffers 86 and 87. The output of the oscillator 91 is fed back to the multiplier 81, input to the symbol timing determination circuit 92, derived as a symbol extraction signal, and supplied to the symbol extraction circuit 10.

  In addition, there are the following documents as related technologies.

JP 2002-314505 A JP 2007-027987 A JP 2010-226348 A

  In recent years, a software demodulator using a program logic of a digital computer has been put into practical use with the advance of hardware. The software demodulator can be realized with a relatively small circuit configuration as compared with a demodulator using a conventional analog electronic circuit, and has an advantage that its performance is stable.

  However, the existing software demodulator configuration replaces the functions and operations of the analog electronic circuit with the program logic of the digital computer as it is, that is, the realization of a theoretical equivalent, which is an essential performance improvement over the conventional method. It does not bring

  Assuming ideal conditions for circuit operation, a signal that cannot be demodulated by a demodulator based on an analog electronic circuit cannot naturally be demodulated even by a theoretically equivalent software demodulator. Alternatively, in capturing and following symbol synchronization in demodulation under a low C / N environment, it does not bring about an essential performance improvement in order to cut off or reduce the influence of stationary noise or sudden disturbance on the communication path.

  In the conventional symbol synchronization circuit for a received signal in a demodulator using an analog electronic circuit, as described above, a phase control circuit such as a PLL circuit is used. Therefore, a software demodulator that is the theoretical equivalent of the software demodulator is obtained by replacing the operation of a PLL circuit, which is originally an electronic circuit, with the program logic of a computer.

  In general, in phase control using a PLL circuit, there are two performance indexes that are mutually contradictory with respect to the purpose. Even in symbol synchronization using a PLL circuit, these indices are reflected as they are. In other words, the symbol clock (frequency) pull-in performance and the tracking range performance determined from the characteristics of a filter (hereinafter referred to as a PLL filter) constituting the PLL circuit are the two.

  These two performance indexes are in contradiction with each other. Therefore, as long as the phase control is performed by the PLL circuit, the following problems are inevitable in realizing the symbol synchronization. In order to accurately synchronize with the symbol clock pull-in performance, that is, with the symbol clock, the PLL filter needs to have such a sensitive characteristic as to extract only the frequency component of the symbol clock. This means that the frequency range followed by the PLL circuit is immediately narrowed.

  That is, as the PLL filter characteristic becomes more sensitive, the synchronization itself becomes more accurate. On the other hand, fluctuations caused by sudden disturbances in the communication path cannot be followed because the information is removed by the filter. That is, the synchronization becomes fragile.

  Conversely, in order to flexibly follow such fluctuations, the PLL filter characteristic needs to have a wider effective base (the width of this base is the tracking range). Such a filter naturally picks up more noise components than the symbol clock. This noise component appears as jitter (fluctuation) at the symbol (extraction) timing of the demodulator, and as a result, the S / N ratio is lowered at the time of symbol determination, that is, the bit error rate is deteriorated.

  Therefore, in the software demodulation using the symbol synchronization method by the conventional PLL circuit as it is, when trying to obtain a stable demodulation performance, the initial synchronization supplement speed, the constant C / N is exactly the same as the demodulator by the analog electronic circuit. The demodulation performance and the performance to cope with symbol jitter in an environment below the value are determined by the PLL filter characteristics.

  In general, it is theoretically difficult or impossible to optimize the performance of the demodulator with respect to these two contradictory performance indicators, and it requires trial and error in a realistic environment. The optimum filter characteristics under the environment will be determined. This also leads to a loss of feasibility of a variable configuration according to signal conditions, which should be an advantage of the software demodulator.

  In Patent Document 1, in the symbol synchronization method using a pilot tone other than a signal to be transmitted, when performing fine adjustment after coarse adjustment, phase information of the pilot tone based on the FFT processing result of sample data A technique for obtaining and fine-tuning is disclosed.

  In this technique, the FFT processing result is used to obtain phase information of the pilot tone at the time of fine adjustment. As will be described later, the digitally modulated input to be transmitted as in the present invention is used. It is not used for initial setting of a PLL circuit for extracting a symbol clock existing in a signal series.

  An object of the present invention is to stably perform high-speed and high-accuracy symbol synchronization and tracking in a low C / N environment and in a communication channel environment that may include sudden disturbance. It is an object of the present invention to provide a symbol synchronization acquisition system and a method thereof.

The symbol synchronization acquisition system according to the present invention comprises:
A symbol synchronization acquisition system for synchronously acquiring a symbol clock of a digitally modulated input sequence using a PLL circuit,
Means for calculating a feature quantity series of the input series;
Means for FFT processing the feature amount sequence of the first N samples (N is an integer of 2 or more);
Means for searching for the maximum spectral component based on the FFT processing result;
Means for estimating the phase of the symbol clock at the time of the N / 2th sample based on the FFT processing result,
The frequency of the spectrum maximum component and the phase estimation value obtained by the phase estimation are set as initial setting values of the PLL circuit.

The symbol synchronization acquisition method according to the present invention comprises:
A symbol synchronization acquisition method for acquiring a symbol clock of a digitally modulated input sequence using a PLL circuit,
Calculating a feature quantity sequence of the input sequence;
FFT processing of the feature amount series of the first N samples (N is an integer of 2 or more);
Searching for a spectrum maximum component based on the FFT processing result;
Performing a phase estimation of the symbol clock at the time of the N / 2 sample based on the FFT processing result;
A step of setting the frequency of the spectrum maximum component and the phase estimation value obtained by the phase estimation as an initial setting value of the PLL circuit.

The program according to the present invention is:
A program for causing a computer to execute a symbol synchronization acquisition method of acquiring a symbol clock of a digitally modulated input sequence using a PLL circuit.
A process of calculating a feature amount series of the input series;
Processing for FFT processing of the feature amount series of the first N samples (N is an integer of 2 or more);
A process for searching for the maximum spectral component based on the FFT processing result;
Processing for estimating the phase of the symbol clock at the time of the N / 2th sample based on the FFT processing result;
And a process of setting the frequency of the spectrum maximum component and the phase estimation value obtained by the phase estimation as an initial set value of the PLL circuit.

  According to the present invention, since the frequency and phase of the symbol clock component hidden in the received signal are realized by performing precise estimation by fast Fourier transform, it is expressed by a sampling sequence with a specific sampling frequency. There is an effect that the intensity and phase of all individual frequency components can be instantaneously and simultaneously calculated practically over the entire frequency component band. As a result, it is possible to expand the capture frequency range of symbol synchronization to the maximum possible, and it is possible to supplement synchronization even for low C / N received signals.

  In addition, under the condition that the frequency of the symbol clock component is constant (except for a very small fluctuation), the target period (number of input samples) of the fast Fourier transform is arbitrarily extended, thereby causing a sudden change. By interpolating the loss of the symbol clock component in the received signal due to disturbance, synchronization tracking can be achieved.

It is a functional block diagram on the receiving side to which an embodiment of the symbol synchronization acquisition circuit according to the present invention is applied. FIG. 2 is a schematic functional block diagram of a transmission side corresponding to the reception side of FIG. 1. It is a figure which shows the specific example of the feature-value series calculation circuit 6 of FIG. A functional block diagram of an embodiment of the symbol synchronization acquisition circuit 7 according to the present invention is shown in relation to the synchronization tracking circuit 8 and the clock generation circuit 9 of FIG. It is a figure which shows the example of the power spectrum of a feature-value time series (amplitude square value). FIG. 2 is a functional block diagram of a PLL circuit including the synchronization tracking circuit 8 and the clock generation circuit 9 of FIG. 1. It is a flowchart which shows the outline | summary of operation | movement in embodiment of this invention. It is a functional block diagram of the receiving side relevant to this invention. FIG. 9 is a functional block diagram of a PLL circuit including a clock generation circuit 9 and a symbol synchronization acquisition / tracking circuit 15 in FIG. 8.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. FIG. 1 is a functional block diagram on the receiving side to which an embodiment of the symbol synchronization acquisition circuit according to the present invention is applied. In FIG. 1, the same parts as those in FIG. The example shown in FIG. 1 is an example applied to a demodulator of a signal subjected to phase shift keying (PSK) modulation.

  FIG. 2 is a diagram for explaining a model of a PSK modulation signal that is an input signal in FIG. 1 together with a signal generation (modulator) process on the transmission side. First, referring to FIG. Explain the model. Assuming that the number of bits per symbol is n (n is an integer of 2 or more), the input bit string is divided into n bits by the bit dividing circuit 21 to form a numerical value (symbol value) series.

  Each symbol value of this series is converted into a corresponding complex symbol by the symbol conversion circuit 22 and then up-sampled into a symbol period by the up-sampler 23, and then a filter (shaping filter) for symbol pulse shaping 24 is applied to form a baseband signal. This is multiplied by a carrier wave (26) in a multiplier 25 and transmitted as a modulated wave.

  The demodulation of the PSK modulation signal on the receiving side follows the modulation process shown in FIG. In FIG. 1, first, the frequency shift circuit 1 has a function of shifting the frequency of the entire received signal in the direction opposite to the carrier frequency and adjusting the signal to the baseband (center frequency 0).

  Next, the input sequence is resampled by the resampler 2 to make the number of samples per symbol time constant. This is because the parameter that determines the operating characteristics of symbol synchronization depends on the number of samples per symbol. By making the number of samples per symbol substantially constant, the symbol synchronization characteristic does not depend on the carrier band or the symbol rate.

  Then, the baseband demodulation circuit 3 demodulates the output of the resampler 2 into a baseband signal. The matched filter 4 at the next stage is a filter having the same characteristics as the shaping filter 24 on the modulation side in FIG. Applying this matched filter 4 to the baseband signal means taking a series correlation with the symbol pulse shaped by the shaping filter 24, and this correlation value becomes maximum at the symbol time.

  Based on the assumption that the noise included in the received signal (added on the transmission line) is additive white Gaussian noise, the error rate (variance of residual) of the symbol extracted at this time (symbol time) is theoretically minimum. It becomes.

  The output of the matched filter 4 is sent to the delay circuit 5 and the feature quantity (power) sequence calculation circuit 6 in the symbol clock detection circuit 13. The delay circuit 5 sets a delay corresponding to N / 2 samples when the number of samples used in the fast Fourier transform (FFT) in the symbol synchronization acquisition circuit 7 is N (an integer of 2 or more).

  The output of the delay circuit 5 is derived as a demodulation result by passing through the symbol extraction circuit 10, the carrier synchronization circuit 11, and the symbol determination circuit 12 in this order. In this embodiment, the received signal is an example applied to demodulation of a modulated wave obtained by digitally modulating a carrier wave, and a (hard or soft) bit string resulting from demodulating the received signal is output. To do.

The symbol clock detection circuit 13 includes a feature amount (power) series calculation circuit 6, a symbol synchronization acquisition circuit 7, a synchronization tracking circuit 8, and a clock generation circuit 9. When the input signal is a PSK modulated signal, the feature amount (power) sequence calculation circuit 6 generally has a symbol synchronization feature amount sequence as follows:
Power sequence P [k] = I [k] squared + Q [k] squared (1)
(Where k is the sample number, I [k] is the in-phase component of the complex sequence of the matched filter output, and Q [k] is also the quadrature component).

  FIG. 3 shows an example of the feature amount (power) series calculation circuit 6 in this case together with the peripheral portion. In FIG. 3, the direct output (complex) from the matched filter 4 is obtained by the arithmetic circuit including the multipliers 61 and 62 and the adder 63 to obtain the power sequence of the above expression (1). This power sequence is input to the symbol synchronization acquisition circuit 7.

  Further, the output of the matched filter 4 (complex) through the delay circuit 5 can be similarly obtained by the arithmetic circuit including the multiplier 6465 and the adder 66 to obtain the power sequence of the above expression (1). This power sequence is input to the synchronization tracking circuit 8.

  FIG. 4 shows a more detailed configuration of the symbol synchronization acquisition circuit 7 in relation to the synchronization tracking circuit 8 and the clock generation circuit 9. The first N samples of the feature quantity (power) series are fast Fourier transformed by the FFT circuit 7. The result of the fast Fourier transform by the FFT circuit 7 is a complex coefficient vector of each frequency component, and the spectrum of the frequency component can be obtained as the square value of the amplitude from each of the coefficients.

  If this result is searched in an appropriate range, the frequency component that gives the maximum value of the spectrum can be set as a precise estimate of the symbol clock frequency. Therefore, a spectrum maximum component search circuit 72 that receives the FFT result is provided.

  If this frequency is fclock, the phase component of the Fourier coefficient aclock of fclock is an estimated value of the symbol clock phase at the time of the N / 2 sample. Therefore, a phase calculation circuit 73 for the maximum spectral component is provided.

  By setting the symbol clock frequency thus obtained and the estimated value of the phase of the symbol clock in the N / 2th sample as an initial value for clock generation of the PLL circuit by the synchronization tracking circuit 8 and the clock generation circuit 9, The following operation is started from a state where symbol synchronization is achieved (captured).

  FIG. 5 shows the power spectrum of the time series of the feature quantity time series of the signal subjected to quaternary phase shift (QPSK) modulation with a sampling frequency of 10 MHz and a symbol rate of 1 M symbol / second, that is, the time spectrum of the squared amplitude value (coefficient vector after Fourier transform The amplitude square value of each of the components is represented in dB along the frequency value corresponding to each component). A frequency component of the symbol clock appears strongly at a position of ± 1 MHz corresponding to the symbol rate.

  Since the amplitude square value series is a real number series, the spectrum is left-right symmetric. Therefore, a linear search within a given range for the frequency component that gives the maximum value of the spectrum on either the positive or negative side is symbol clock frequency estimation. . The symbol clock frequency and initial phase obtained in this way are set as the initial state of the PLL circuit for symbol synchronization tracking (tracking circuit 8).

  Thereafter, the time at which the clock generation circuit 9 in FIG. 1 takes a specific state (phase of the generated single-cycle signal) is taken as symbol timing. The symbol extraction signal based on the symbol timing is generated every clock cycle, and the symbol extraction 10 reproduces (extracts) the symbol string by sampling the signal state at the time when the signal occurs as a complex value.

  Symbol timing synchronization tracking is configured as shown in FIG. 6 using a normal PLL circuit (equivalent to the example of the PLL circuit of FIG. 9). The synchronization tracking circuit 8 sequentially obtains the exponential weighted series correlation between the feature quantity sequence and the symbol clock, that is, the Fourier coefficient of the symbol clock frequency component in the feature quantity series, and the phase error detected from the phase component and its time change Is achieved by feeding back to the clock generation circuit 9. Since FIG. 6 is equivalent to FIG. 9, detailed description thereof is omitted.

  The symbol extraction signal from the clock generation circuit 9 is supplied to the symbol extraction circuit 10, and the carrier frequency and phase setting errors and fluctuations of the symbol string extracted by the symbol extraction circuit 10 are corrected by the carrier synchronization circuit 11. The The corrected symbol sequence is converted to a symbol sequence by the symbol determination circuit 12 to convert the phase component of each symbol into a corresponding bit sequence (a hard value that directly converts to a 0/1 bit value, or a real value that means bit value estimation). The soft decision is made to convert the data into (), and this result is output as a demodulation result.

  FIG. 7 is a flowchart showing an outline of the operation of the embodiment of the present invention described above. First, a feature amount (power) sequence of a PSK-modulated received signal is calculated by the feature amount sequence calculation circuit 6 (step S1), and then the first N samples of this feature amount sequence are subjected to FFT processing by the FFT circuit 71. (Step S2). Based on the FFT processing result, the maximum spectrum component search circuit 72 searches for the maximum spectrum component (step S3), and the phase calculation circuit 73 calculates the phase of the symbol clock at the time of the N / 2th sample. ((Step S4). In this case, as described above, the phase component of the Fourier coefficient of the frequency of the maximum spectrum component is estimated as the phase of the symbol clock at the time of the N / 2 sample.

  The frequency of the spectrum maximum component searched in step S3 is set as the initial frequency of the PLL circuit by the synchronization tracking circuit 8 and the clock generation circuit 9 (step S5), and the phase estimation value estimated in step S4 is the PLL. It is set as the initial phase of the circuit (step S6). The PLL circuit starts the follow-up operation after the initial setting, and then continues the follow-up (step S7).

  As described above, according to the present invention, the symbol clock frequency and the estimated value of the phase at each time corresponding to the symbol clock frequency can be calculated directly and all at once from a fixed amount of feature amount series data. In other words, the symbol synchronization acquisition mechanism calculates the estimated value of the direct symbol clock frequency and the corresponding phase at each time using the fast Fourier transform, and reflects this in the initial state of the PLL circuit of the synchronization tracking mechanism. I try to let them.

  Furthermore, even in synchronous tracking, by extracting the symbol clock from a certain amount of feature amount sequence, even if the symbol clock is lost due to sudden disturbance, etc., an appropriate symbol clock exponentially weighted sequence correlation It is possible to operate stably by selecting.

  Therefore, according to the present invention, the frequency range in which symbol synchronization can be captured can be theoretically maximized (the entire band of the received signal). The C / N that can correspond to the accuracy of acquisition is simply determined by the number of input samples of FFT (Fast Fourier Transform), and trial and error as in the case of using a PLL circuit is unnecessary.

  In addition, since both the acquisition and tracking functions are independent from each other in the configuration of the demodulator, optimization of symbol synchronization tracking can be performed only for the purpose of tracking. Even in tracking, the only parameter to be adjusted is an exponential weight (attenuation) coefficient that determines the effective length of the exponentially weighted correlation integral of the PLL circuit, and fine adjustment of the PLL coefficient is not necessary.

  In the block diagram of FIG. 1, the baseband demodulation circuit 3 is an FM detection method in the case of frequency shift (FSK) modulation, envelope detection in the case of amplitude shift (ASK) modulation, and phase shift. In the case of (PSK) modulation or quadrature amplitude modulation (QAM), there is nothing in particular.

  In the block diagram of FIG. 1, the characteristics of the matched filter 4 can vary depending on the time characteristics of the symbol pulse. Furthermore, the feature quantity may vary depending on the modulation format and the assumed communication situation. For example, in the offset QPSK, the absolute value of the complex difference is used.

  Furthermore, in the block diagram of FIG. 1, the carrier synchronization circuit 11 is required only when synchronous detection is performed by PSK, QAM, MSK, etc., and when differential modulation is performed by PSK modulation. Alternatively, the processing when a symbol-by-symbol phase shift is added may be performed here.

  Details of the baseband demodulating circuit 3, the matched filter 4, the carrier synchronization circuit 11, and the like are well-known techniques and are not directly related to the present invention, and thus are not described in detail.

  The present invention is not limited to the above-described embodiment, and can be applied to general digital communication that requires a symbol synchronization mechanism. That is, (1) a communication system that transmits and receives symbol signal pulses at a finite and constant time interval (period), and (2) information that can be referred to is provided in addition to estimating the symbol timing from the received signal itself. It is possible to apply the present invention to all cases where this is not possible.

  The processing shown in FIG. 7 can be configured so that the operation procedure is stored in advance in a recording medium as a program and is read and executed by a computer.

DESCRIPTION OF SYMBOLS 1 Frequency shift circuit 2 Resampler 3 Baseband demodulation circuit 4 Matching filter 5 Delay circuit 6 Feature quantity calculation series output circuit 7 Symbol synchronization acquisition circuit 8 Synchronization tracking circuit 9 Clock generation circuit 10 Symbol extraction circuit 11 Carrier synchronization circuit 12 Symbol determination circuit 13 Symbol clock detection circuit 71 FFT circuit 72 Spectral maximum component search circuit 73 Phase calculation circuit of maximum spectral component

Claims (9)

A symbol synchronization acquisition system for synchronously acquiring a symbol clock of a digitally modulated input sequence using a PLL circuit,
When the input sequence is received and the number of samples used in the FFT processing is N (N is an integer of 2 or more), a delay corresponding to N / 2 samples is set for the received input sequence and output. A delay circuit;
Means for receiving the input series and the output from the delay circuit, and separately calculating each feature quantity series;
Means for performing FFT processing on the feature amount sequence of the first N samples (N is an integer of 2 or more) of the input sequence ;
Means for searching for the maximum spectral component based on the FFT processing result;
Means for estimating the phase of the symbol clock at the time of the N / 2th sample based on the FFT processing result,
The frequency of the spectrum maximum component and the phase estimation value by the phase estimation are set as initial setting values of the PLL circuit ,
The feature amount series calculated for the output from the delay circuit is input to the PLL circuit,
The system, wherein the PLL circuit performs a follow-up operation on a feature amount sequence calculated for an output from the delay circuit using the initial setting value . A symbol extraction circuit for extracting a symbol string using an output from the delay circuit
  Further comprising
  The PLL circuit performs the following operation to derive a symbol extraction signal, and supplies the symbol extraction signal to the symbol extraction circuit;
  The symbol extraction circuit extracts the symbol string based on the symbol extraction signal.
  The system of claim 1.   The system according to claim 1, wherein the digital modulation is phase shift (PSK) modulation, and the feature amount sequence is a power amount sequence.   The system according to claim 1, wherein the phase estimation value is a phase component of a Fourier coefficient of a frequency of the spectrum maximum component. A symbol synchronization acquisition method for acquiring a symbol clock of a digitally modulated input sequence using a PLL circuit,
In the delay circuit, when the input sequence is received and the number of samples used in the FFT processing is N (N is an integer of 2 or more), a delay corresponding to N / 2 samples is set for the received input sequence And output step,
Receiving the input series and the output from the delay circuit, and separately calculating each feature quantity series;
FFT processing the feature amount sequence of the first N samples (N is an integer of 2 or more) of the input sequence ;
Searching for a spectrum maximum component based on the FFT processing result;
Performing a phase estimation of the symbol clock at the time of the N / 2 sample based on the FFT processing result;
Setting the frequency of the spectrum maximum component and the phase estimation value by the phase estimation as an initial setting value of the PLL circuit ;
Inputting the feature quantity sequence calculated for the output from the delay circuit to the PLL circuit;
Performing a tracking operation on a feature amount sequence calculated for an output from the delay circuit using the initial setting value in the PLL circuit . In the symbol extraction circuit, a step of extracting a symbol string using an output from the delay circuit
  Further including
  The PLL circuit performs the following operation to derive a symbol extraction signal, and supplies the symbol extraction signal to the symbol extraction circuit;
  The symbol extraction circuit extracts the symbol string based on the symbol extraction signal.
  The method of claim 5.   The method according to claim 5 or 6, wherein the digital modulation is phase shift (PSK) modulation, and the feature amount sequence is a power amount sequence.   The method according to claim 5, wherein the phase estimation value is a phase component of a Fourier coefficient of a frequency of the spectrum maximum component. A program for causing a computer to execute a symbol synchronization acquisition method of acquiring a symbol clock of a digitally modulated input sequence using a PLL circuit.
When the input sequence is received and the number of samples used in the FFT processing is N (N is an integer of 2 or more), a delay corresponding to N / 2 samples is set for the received input sequence and output. Receiving the output from the delay circuit;
Processing for receiving the input series and the output from the delay circuit, and calculating each feature quantity series separately ;
A process of performing FFT processing on the feature amount sequence of the first N samples (N is an integer of 2 or more) of the input sequence ;
A process for searching for the maximum spectral component based on the FFT processing result;
Processing for estimating the phase of the symbol clock at the time of the N / 2th sample based on the FFT processing result;
A process of setting the frequency of the spectrum maximum component and the phase estimation value by the phase estimation as an initial setting value of the PLL circuit ;
A process of inputting the feature quantity sequence calculated for the output from the delay circuit to the PLL circuit that performs a tracking operation on the feature quantity sequence calculated for the output from the delay circuit using the initial setting value; A program characterized by including />.

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