JPH0567816A - Superconducting field-effect transistor and its manufacture - Google Patents

Abstract

PURPOSE:To provide a quantum well type superconducting field-effect transistor which has a long coherent length zeta and excellent transistor characteristics and further enables its practical use and to provide easy manufacturing processes for the transistor at an excellent yield rate by the use of a self- alignment method. CONSTITUTION:On an InP substrate 1, the first barrier layer 2 consisting of InXAl1-XAs which are grid-matched at least with the InP substrate, a channel layer 3 consisting of InXGa1-XAs, a channel supplying layer 4 consisting of an n type InP, the second barrier layer 5 consisting of InXAl1-XAs which is grid-matched with the InP substrate and a contact layer 6 consisting of an n type InAs are provided for constituting an epitaxial layer structure. Further, a gate electrode 7 consisting of Wsi is formed, and, by using the gate electrode 7 as a mask, a transistor is manufactured in a self-matching manner.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a superconducting field effect transistor and its manufacturing method.

[0002]

2. Description of the Related Art Superconducting transistors are attracting attention as next-generation devices that combine ultra-high speed and ultra-low power consumption. In particular, superconducting transistors that have a three-terminal structure and can use a DC power supply are It is optimal for promoting the integration of superconductor devices. The superconducting field effect transistor, which is one of the above-mentioned transistors, uses the principle that the Cooper pair that penetrates into the semiconductor is modulated by the electric field due to the proximity effect of the superconductor, and in particular, the input and output are completely separated. It is extremely superior to other superconducting transistors in the point that it exists, and its realization is a major issue.

A first superconducting field effect transistor having a silicon MOSFET structure has been proposed. (T. Nishino
et al .: Tech. Dig. IEDM, 1988 p. 286) Figure 3a is the first
FIG. 7 is an element cross-sectional view of a conventional superconducting field effect transistor of FIG. The superconducting field effect transistor is a gate oxide film 12 on a Si substrate 11, a poly-Si gate electrode 13, a nitride film 14 in the form of an overhang on the gate electrode 13, and a nitride film formed as an insulating film on the gate sidewall. 15, a channel layer 16 formed at the interface between the gate oxide film 12 and the Si substrate 11, a source region 18a formed by arsenic ion implantation, and a drain region 17b. The overhang-shaped nitride film 14 is used. , Superconductor material N
The source electrode 17b and the drain electrode 18b made of b are formed in a self-aligned manner without short circuit. 3b and 3
FIG. 3C is a diagram for explaining the operation of the superconducting field effect transistor, which shows the superconductivity that has exuded into the semiconductor from the superconductor side by the superconducting proximity effect as a spatial change of the pair potential. When there is no gate voltage, the case where the gate voltage is applied is shown, but the potential pair attenuates with the coherent length ζ. That is, in the same figure (b), since no voltage is applied to the gate,
The Cooper pair (arrow in the figure) barely emerges from the superconductor. Therefore, its potential is also low. However, when a voltage is applied to the gate, the Cooper pair can be exuded considerably from the superconductor as shown in (c) of the figure, so as shown in the figure, the Cooper pair from the source and drain overlap and their potentials are continuous. Therefore, the superconducting current flows.

The coherent length ζ is given by the following equation in the case of the clean-limit approximation.

Ζ = h ² √N _s / √2πk _b Tm ^* Ns is the electron sheet carrier concentration, and m ^* is the effective electron mass. When a voltage is applied to the gate, the sheet carrier concentration N _{s of} electrons directly under the gate fluctuates, the coherent length ζ changes, and as a result, the superconducting current can be controlled. In order to operate the superconducting field effect transistor, it is necessary to make the coherent length ζ or less in order to set the source-drain distance. Although the effective mass of electrons in Si is large and the coherence length ζ is short, the electron mobility in Si is small and the influence of ionized impurity scattering etc.
The n-limit approximation cannot be applied, and the coherent length ζ becomes even shorter. Even in the above conventional example, the source-drain interval is 0.1 μm, and it is difficult to perform patterning of 0.1 μm with a high yield at the current photolithography technology level, and coherent to enable device practical use. Length ζ needs to be as long as possible.

FIG. 4 is a device sectional view of a second conventional superconducting field effect transistor proposed to solve the problem of the first conventional example. (C. Nguyenet al. Appl. Phys.
Lett., Vol. 57, (1990) p. 87) The manufacturing process of the superconducting field effect transistor will be described. Ga on the GaAs substrate 21
The first buffer layer 22a made of Sb and the second buffer layer made of AlSb
Buffer layer 22b, superlattice layer 2 composed of GaSb and AlSb
3, a first barrier layer 24 made of AlSb, a channel layer 25 made of InAs, a second barrier layer 2 made of AlSb
6, an etching stopper layer 27 made of GaSb, a first gate contact layer 28a made of InAs, and a second gate contact layer 28b made of GaSb are sequentially stacked, and a second gate is formed by reactive ion etching using the gate pattern as a mask. A part of the gate contact layer 28b and the first gate contact layer 28a is removed by etching, and the remaining first gate contact layer 28a made of InAS is removed by wet etching to form the gate electrode region and the region directly below it. An undercut portion 28c is formed between the etching surfaces of the formed first gate contact layer, and an etching stopper layer 27 made of GaSb is formed.
The first barrier layer 26 made of AlSb is removed by wet etching to expose the channel layer 25 on the surface,
A source electrode 29 and a drain electrode 30 are formed in a self-aligned manner by depositing a superconductor film made of Nb by an electron beam vapor deposition method. Since the quantum well field effect transistor has no impurities doped in the channel,
Since electrons are not scattered by ionized impurities, the mobility of electrons is extremely high, the clean-limit approximation can be applied, and since the channel is formed of InAs, the effective mass of electrons is extremely small and the coherence length ζ is sufficient. Can be long. For example, if the sheet carrier concentration is 10
^When the effective mass of electrons is ¹² cm ^-2 and 0.023 m _e , the coherent length ζ is about 0.4 μm, which is much larger than that of Si-based MOSFET. However, the second conventional superconducting field effect transistor has the following problems.
AlSb used as a barrier layer is a chemically unstable material and is oxidized and deteriorated immediately when left in the air, which causes a problem in the manufacturing process and reliability of the transistor. The band lineup of InAs and AlSb is a stagger type, and the band gap energy of InAs is
Since it is as small as 0.36eV, when voltage is applied to the gate,
The barrier between InAs and AlSb becomes very thin, and the electrons in the channel easily leak to the gate side, and good transistor operation cannot be obtained. InAlAs / In lattice-matched to an InP substrate to solve the problems of the superconducting field effect transistor.
Although GaAs quantum well superconducting field effect transistors can be studied, selective etching of InAlAs layer and InGaAs layer is not possible at present in the manufacturing process, and the channel layer is formed on the surface with good reproducibility when forming the source and drain electrodes. The problem is that it is difficult to expose.

[0007]

Since the Si MOS type superconducting field effect transistor has a very short coherence length ζ, it is difficult to put it into practical use by the current photolithography technology. The InAs / AlSb quantum well type superconducting field effect transistor proposed to solve the above problems cannot obtain good transistor characteristics due to the gate leakage current, and also has problems in terms of reliability and manufacturing process. Is difficult to convert. Even in the InAlAs / InGaAs quantum well type superconducting field effect transistor, there is a problem in the manufacturing process such as selective etching not being possible. Furthermore, since the barrier height between the gate electrode and InAlAS is as low as 0.6 eV, the breakdown voltage is poor. However, there is a problem that the gate material is also limited.

The present invention solves the above-mentioned drawbacks, has a sufficiently long coherent length ζ, can be manufactured by the current photolithography technology, has excellent transistor characteristics, and has no problem of reliability. (EN) Provided is a conductive field effect transistor, and a method for manufacturing a superconducting field effect transistor capable of achieving a high yield by an easy manufacturing process, despite a short source-drain electrode distance limited by a coherent length ζ. Has a purpose.

[0009]

The present invention has been made in view of the above points, and a first barrier layer made of In _x Al _1-x As, which is lattice-matched with at least the InP substrate, is formed on the InP substrate.
Channel layer made of _x Ga _1-x As, n-type impurities introduced
Channel supply layer made of InP, lattice-matched with InP substrate
Has In _x Al _1-x As epitaxial layer structure composed of a second barrier layer made of, consists In _x Al _1-x As made of InAs in the second barrier layer made of the contact layer and WSi InAs on the source and drain regions, forming the gate electrode
On the channel layer made of In _x Ga _1-x As exposed on the surface by removing the contact layer made of InP, the channel supply layer made of InP and the second barrier layer made of In _x Al _1-x As A superconducting field effect transistor having source and drain electrodes made of is used.

The long axis of the gate electrode having a rectangular shape has a <110> direction of the substrate or 45 ° from the <110> direction.
Installed in the rotated direction, and using the gate electrode as a mask
The contact layer made of As, the second barrier layer made of In _x Al _1-x As, and the channel supply layer made of InP are selectively removed, and n-type impurities are ion-implanted using the gate electrode as a mask to improve crystallinity. After recovering and forming the source / drain regions, a method of manufacturing a superconducting field effect transistor in which source and drain electrodes made of a superconductor material are formed in a self-aligning manner is used.

[0011]

The operation of the superconducting field effect transistor having the above structure and the method of manufacturing the same is as follows. InGaAs
Since it is a quantum well field effect transistor with a layer as a channel, electron mobility is extremely high due to little electron scattering due to ionized impurities in the channel where impurities are not introduced, and the clean-limit approximation is applicable. In addition, since the effective mass of electrons is extremely smaller than that of the Si device, the coherent length ζ can be increased. Since the upper barrier is composed of InAlAs and InP, InAlAs is formed by conventional wet etching technology.
The channel layer can be easily exposed on the surface with good reproducibility by utilizing the characteristics of selective etching of InP and InP or InGaAs and InP. If the upper barrier is only InP, good Schottky characteristics cannot be obtained with the gate electrode, but if the InAlAs layer is placed on top, the Schottky characteristics are improved, and if a contact layer made of InAs is placed on top of it, InAs And InAlAs
Has a conduction band offset of about 0.9 eV,
Compared to the height of the barrier between lAs and the gate electrode (about 0.6 eV), the gate breakdown voltage can be improved, and the superconducting field-effect transistor with the above configuration has a leakage current to the gate in InAs / AlSb quantum well superconducting field-effect transistor Does not occur,
It is also good in terms of material reliability. Further, in the method of manufacturing the superconducting field effect transistor, when the source / drain electrodes are formed in a self-aligned manner by using the gate electrode as a mask, a sufficient step between the channel layer and the gate electrode and the gate electrode and the layer directly under the gate electrode are formed. It is necessary to form an undercut portion between the etching surfaces of the contact layer, etc., but since the contact layer made of InAs acts as a gate metal, the thickness of the contact layer can be set arbitrarily, so a sufficient step can be secured. Since the long axis of the rectangular shaped gate electrode is installed in the <110> direction of the substrate or in a direction rotated by 45 ° from the <110> direction, the etching surface is formed perpendicular to the substrate or in an inverted mesa. Therefore, an undercut portion is formed immediately below the gate electrode. When WSi is used as the gate electrode, it has an ohmic junction with the contact layer made of InAS, WSi can be easily processed by dry etching, and WSi has heat resistance, and is etched by using the gate electrode made of WSi as a mask. After exposing the channel layer of the source and drain regions to the surface,
N-type impurities are ion-implanted using the gate electrode as a mask,
A high-temperature heat treatment can be applied to a manufacturing process such as recovery of crystallinity, and as described above, a superconducting field effect transistor can be manufactured by the easy manufacturing process using the self-alignment method.

[0012]

EXAMPLES Examples of the present invention will be described below.

FIG. 1 is a main sectional view of an embodiment of a superconducting field effect transistor of the present invention. The structure of this embodiment is different from the structure of the second conventional example shown in FIG. 4 in that a barrier layer made of In _x Al _1-x As and InP lattice-matched with the InP substrate and I
It is a quantum well type superconducting field effect transistor with a channel layer made of n _x Ga _1-x As, and its gate electrode is made of WSi.

Next, the superconducting field effect transistor will be described with reference to FIG.
A method of manufacturing the transistor will be described. Semi-aborted as shown in Figure 2a
Thickness of 300 nm on a limbal InP substrate 1 by molecular epitaxy
In _0.53Al_0.47First barrier layer 2 of As, thickness 25
nm In_0.53Ga_0.47Channel layer 3 made of As, thickness 1.5n
m InP, thickness 8nm 5X1018 / cm³Contains n-type impurities
Channel consisting of n-type InP (n-InP) and InP with a thickness of 10 nm
Supply layer 4, 20 nm thick In_0.53Al_0.47The second bar made of As
Rear layer 5, contact layer 6 made of 200 nm thick InAs
Are sequentially laminated. As shown in FIG. 2b, electron beam evaporation method
WSI with a thickness of 200 nm was vapor-deposited on the substrate with a gate length of 0.
A pattern of 5 μm and a gate width of 50 μm is formed by photoresist.
Formed, and using the gate pattern as a mask, SF6 and CF4
By reactive ion etching with mixed gas of
The gate electrode 7 is formed. As shown in Figure 2c
Contact layer 6 made of InAs using the electrode 7 as a mask, InAl
The second barrier layer 5 composed of As is formed of phosphoric acid and hydrogen peroxide.
Selectively etched away with aqueous solution, then hydrochloric acid and phosphorus
The channel supply layer 4 made of InP is selected by the mixed solution of acids.
Selective etching removal_0.53Ga_0.47Chi consisting of As
Although the surface of the channel layer 3 is exposed, a rectangular gate pattern is formed.
The direction in which the turn is rotated 45 ° from the <110> direction of the substrate
Since it is formed on the channel layer 3
It becomes vertical with respect to, and is between the gate electrode 7 and the etching surface.
An undercut portion is formed. As shown in Figure 2d,
70KV acceleration voltage, 5X10 with the gate electrode 7 as a mask¹3 / cm³
Ion implantation at a dose of 10 ℃ and heat treatment at 600 ℃ for 10 seconds.
The crystallinity is restored by the reason, and the source region 8a and the drain are
Area 8b respectively, and then the electron beam evaporation method is applied.
Evaporate Nb with a thickness of 100 nm and etch with the gate electrode
Gate electrode due to the undercut portion formed between the surfaces
It is made of superconducting material Nb in a self-aligning manner without short-circuiting
A source electrode 9a and a drain electrode 9b are formed,
The elements are separated by etching, and the superconducting field effect transistor is
The manufacturing process of the transistor is completed.

[0015] Characteristics of exemplary but In _0.53 Ga _0.47 As and In _0.52 Al _{0.4 8} As is used which is lattice matched to the InP substrate in the example, a transistor as long as the lattice mismatch does not occur a transfer defects of the present invention Does not deteriorate.

[0016]

As described above, according to the present invention, a quantum well type superconducting field effect transistor having InGaAs as a channel can be put into practical use by adopting a two-layer structure of a channel supply layer made of InP and a barrier layer made of InAlAs. Further, by using the contact layer made of InAs, it is possible to provide a superconducting field effect transistor capable of improving characteristics such as improvement of gate breakdown voltage and realizing extremely low power consumption and ultra high speed. Further, the self-alignment technique makes the manufacturing process very easy, and the superconducting field effect transistor can be provided with high yield.

[Brief description of drawings]

FIG. 1 is a main sectional view of a superconducting field effect transistor according to an embodiment of the present invention.

FIG. 2 is a manufacturing process diagram of a superconducting field effect transistor according to an embodiment of the present invention.

FIG. 3A is a main cross-sectional view of a first conventional superconducting field effect transistor, and FIG. 3B illustrates control of the superconducting proximity effect inside the superconducting field effect transistor when no gate voltage is applied. FIG. 3C is a diagram for explaining control of the superconducting proximity effect inside the superconducting field effect transistor when a gate voltage is applied.

FIG. 4 is a main sectional view of a second conventional superconducting field effect transistor.

[Explanation of symbols]

 1 semi-insulating InP substrate 2 first barrier layer (InAlAs) 3 channel layer (InGaAs) 4 channel supply layer (3 layer structure of InP, n-type InP and InP) 5 second barrier layer (InAlAs) 6 contact layer (InAs) 7 Gate electrode (WSi) 8 Source region 8b Drain region 9a Source electrode (WSi) 9b Drain electrode (WSi)

Claims (4)

[Claims] 1. A first barrier layer made of In _x Al _1-x As, which is lattice-matched to at least the InP substrate, and In _x Ga _1-x As.
Channel layer made of InP, a channel supply layer made of InP doped with n-type impurities, In _x Al lattice-matched with the InP substrate
_It has an epitaxial layer structure composed of a second barrier layer made of _1-x As, a gate electrode is formed on the second barrier layer made of In _x Al _1-x As, and it is formed on the source and drain regions. In exposed on the surface by removing the channel supply layer made of n-type InP and the second barrier layer made of In _x Al _1-x As
A superconducting field-effect transistor characterized in that source and drain electrodes made of a superconducting material are formed on a channel layer made of _x Ga _1-x As. 2. The superconducting transistor according to claim 1, wherein a contact layer made of InAs is inserted between the second barrier layer made of In _x Al _1-x As and the gate electrode. A superconducting field effect transistor characterized by acting as a gate metal. 3. The superconducting field effect transistor according to claim 1, wherein the major axis of the rectangular gate electrode is the <110> direction of the substrate or a direction rotated by 45 ° from the <110> direction. And using the gate electrode as a mask, the contact layer made of InAs, the second barrier layer made of In _x Al _1-x As, and the channel supply layer made of InP are selectively removed to mask the gate electrode. A method of manufacturing a superconducting field effect transistor, characterized in that the source and drain electrodes made of a superconducting material are formed in a self-aligning manner. 4. The method for manufacturing a superconducting field effect transistor according to claim 3, wherein the gate electrode is formed of WSi, and the contact layer made of InAs is masked with the gate electrode, In _x Al _1-x. With a second barrier layer made of As
The channel supply layer made of InP is selectively removed, and after ion implantation of n-type impurities into the In _x Ga _1-x As layer corresponding to the source and drain regions and recovery of crystallinity, the gate electrode is formed. A method of manufacturing a superconducting field effect transistor, which comprises forming source and drain electrodes made of a superconductor material in a self-aligning manner as a mask.