JPH11111968A - Manufacture of semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To avoid thermal deterioration due to inactivation of donors which is caused by inclusion of impurities by forming a first electrode structure on a semiconductor lamination structure, and moving negatively ionized impurities such as fluorine and oxygen in the second layer to the first layer through electric filed stress. SOLUTION: Inclusion of at least fluorine impurities contributes significantly to inactivation of an N-type InAlAs layer 5. At least a part of fluorine which inactivates donors is discharged from the doped N-type InAlAs layer 5 to an undoped InAlAs layer 6 on the electric field applying electrode side, by applying an electric field while applying thermal stress. In this phenomenon, a negative bias is applied to a gate electrode 8a, fluorine existing in the undoped InAlAs layer 6 is mixed in the InAlAs doped layer 5 as a donor layer, and a drain current for inactivating silicon donors decreases.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor technology, and more particularly, to a method for manufacturing a semiconductor device using a compound semiconductor.

[0002]

2. Description of the Related Art In recent years, ternary and quaternary mixed crystal semiconductors such as InGaAs and InGaAsP have been receiving attention. In particular, InGaAs lattice-matched to the InP substrate
Is promising as a material for various field effect transistors as well as optical semiconductor devices. In particular, research on a field-effect transistor using a two-dimensional electron gas at a hetero interface with InP or InAlAs has been actively conducted.

[0003] The reason why InGaAs is also considered promising as an electron transport semiconductor device is that the peak value of the electron drift velocity is larger than that of GaAs or the like.
High mobility of electrons in low electric field, easy contact with ohmic electrode, low contact resistance, high overshoot of electron velocity can be expected, low noise due to valley scattering, comparison of interface characteristics with insulator Good, etc. Furthermore, one of the major reasons is that the above-described two-dimensional electron gas semiconductor device can be realized.

At present, a field effect transistor using a two-dimensional electron gas at an InAlAs / InGaAs interface is regarded as a promising high-performance microwave / millimeter-wave device, and research and development are being carried out in various fields. In particular, its effectiveness as a low-noise element has been confirmed at the experimental level.
E Microwave and Guided Wave Letters, Volume 1, Issue 7, Pages 114-116,
1991 (IEEEMICROWAVE AND G
UIDED WAVE LETTERS, VOL. 1,
NO. 5, p. 114-116, 1991) reported a noise figure of 1.2 d at 94 GHz at room temperature, as reported by KH Duh et al.
B, until the associated gain of 7.2 dB has been confirmed. Semiconductor devices are manufactured by using a system in which these are lattice-matched on an InP substrate, that is, a material system in which In _0.52 Al ^0.48 As / In _0.53 Ga ^0.47 As and the In composition are specified.

In this system, a two-dimensional electron gas is formed in the In _0.53 Ga ^0.47 As layer. For the purpose of further improving the characteristics, for example, IEE, E-electron, semiconductor device, letters, and Vol. 10, No. 3, 114-11
6, 1989 (IEEEELECTRON DEV
ICE LETTERS, VOL. 10, NO. 3,
P. 114-116, 1989) to G.I.
et al. ), Attempts have been made to improve the semiconductor device characteristics by setting the In composition of the channel InGaAs layer to a value greater than 0.53.

[0006] However, an InP substrate and an In composition of 0.1% are used.
In InGaAs of 53 or more, lattice irregularity exists, and the film thickness that can be grown on the crystal is limited by the In composition ratio.
The thickness of the InGaAs channel is limited.

Further, InAs is formed in an InGaAs channel.
A semiconductor device intended to form a two-dimensional electron gas layer with a high confinement effect by inserting a thin layer of
IE Electron Semiconductor Device Letters, Vol. 13, No. 6, pp. 325-327, 1992 (IE
EE ELECTRON DEVICE LETTER
S, VOL. 13, NO. 6, p. 325-327, 1
992) and Akasaki et al. (T. Akazaki et a).
l. ).

In recent years, various high semiconductor device characteristics have been reported for the InAlAs / InGaAs heterojunction field-effect transistor formed on such an InP substrate. On the other hand, thermal instability factors include: It has been reported that impurities such as fluorine, which are not constituent materials of a semiconductor device, are mixed into the epitaxial layer from the outside and inactivate a donor in an impurity-doped InAlAs layer generally used as a donor layer. . For example, Applied Physics Letters, Vol. 66, No. 7,
863-865, 1995 (Applied Ph.
ysics Letters, Vol. 66, no.
7, p. 863-865, 1995) by Hayafuji
Deterioration of the semiconductor device due to fluorine by i et al.
Proceedings of the 7th International Conference on Indium Phosphorus and Related Materials, 59
7-600, 1995 (Proc. 7th In
t. Conf. InP and Related Ma
terials, pp. 597-600, 1995) discusses the deterioration of semiconductor devices due to oxygen by Takahashi et al.

Further, IEICE Technical Report (ED95-105, 13)
Fujihara et al. Point out that the mixing of these impurities can be reduced by reducing the composition of Al in the InAlAs Schottky layer formed on the InAlAs donor layer. That is, InAl
In the case where As is used, it can be understood that the thermal instability can be improved by forming a barrier layer that suppresses the entry of impurities thereon. In fact, in this report, a thermal storage experiment was performed on each crystal sample in which the Schottky layer was made of InAlGaAs with no impurity added and the composition of Al and Ga was changed. It has been reported that the amount was reduced and the amount of reduction in the sheet electron density was also suppressed accordingly.

As described above, InAlAs is used as the donor layer.
In the case of using, the inactivation of the donor due to the contamination with impurities is a serious problem that significantly impairs the reliability of the semiconductor device. Generally, most of heterojunction field effect transistors formed on an InP substrate have InAlAs as a donor supply layer.
Layers are often used. However, an example in which InAlAs is not used at all and InP is used as the material of the donor layer is disclosed in, for example, IEE Electron Semiconductor Device Letters, Vol. 16, No. 9, pp. 396-398, 1
995 (IEEE ELECTRON DEVICE)
LETTERS, VOL. 16, NO. 9, p. 39
6-398, 1995).
s) et al.

As described above, InAlA is used as the donor supply layer.
By not using s, as a result, there is also a structure that avoids the inactivation of the donor due to the contamination of impurities such as fluorine and secures thermal reliability.

[0012]

As described above, for example, an InAlAs / InGaAs system and an AlGaAs /
In a heterojunction field-effect transistor represented by a GaAs system, impurities such as fluorine adhering to the surface of a sample during a process of manufacturing a semiconductor device are mixed into an epitaxial layer in a heat storage process, and an n-type impurity is formed. Inactivating the donor in the donor layer to which is added is a major factor that impairs reliability.

The present invention has been made in view of the above circumstances. Accordingly, it is an object of the present invention to provide a method for manufacturing a semiconductor device in which impurities mixed in a semiconductor layer such as fluorine can be discharged from the semiconductor layer.

Another object of the present invention is to provide a semiconductor device formed on an InP substrate or a GaAs substrate which can avoid thermal deterioration due to inactivation of a donor due to contamination of impurities. It is to provide a method of manufacturing.

[0015]

According to the present invention, there is provided a method of manufacturing a semiconductor device, comprising the steps of: forming a semiconductor laminated structure including a plurality of semiconductor layers; and providing the semiconductor laminated structure with a first layer and a carrier. Forming a first electrode structure on the semiconductor multilayer structure, comprising:
And moving negatively ionized impurities, such as fluorine or oxygen, in the second layer to the first layer by electric field stress.

The second layer is made of impurity-doped InAlAs.
It may be a layer or an impurity-doped AlGaAs layer. When the second layer is an impurity-doped InAlAs layer, the first layer is an impurity-free InAlAs layer.
The s layer. Further, the second layer is made of an impurity-added AlG
When the first layer is an aAs layer, the first layer is
It is an lGaAs layer or a GaAs layer with no impurity added.

When transferring the negative ion impurity,
By applying a positive bias voltage greater than a predetermined value to the first electrode structure, negatively ionized impurities in the second layer are moved to the first layer. At this time, it is desirable to apply the bias voltage at a temperature higher than room temperature.

[0018] The first electrode structure is a Schottky electrode structure, and the predetermined value is a threshold value of the Schottky electrode structure.

On the semiconductor laminated structure, second and third electrode structures are formed on both sides of the first electrode structure apart from the first electrode structure. Thus, an FET structure is formed. Also, the FET structure may be applied to a heterojunction.

The method may further include forming a recess except at least a part of an uppermost layer in the semiconductor multilayer structure, wherein the first electrode structure is formed in the recess.

[0021]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A method for manufacturing a semiconductor device according to the present invention will be described in detail with reference to the accompanying drawings.

FIG. 1 shows an example of the structure of a semiconductor device manufactured by the method of manufacturing a semiconductor device according to the present invention. In the epitaxial multilayer structure of the semiconductor device, the impurity-free InAlAs layer 2 is 500 nm, the impurity-free InGaAs layer 3 is 20 nm, and the impurity-free InAlAs layer 4 is 5 nm, 3 × 10 ¹⁸ cm ⁻³ on the semi-insulating InP substrate 1. InAlAs layer 5 with silicon added to 150 nm, InAlAs layer 6 without impurities 20 nm, 3 × 10 ¹⁸ cm ⁻³
InGaAs layers 7 each having an impurity (silicon) added thereto are stacked in this order by 20 nm.

The ohmic electrodes 8b and 8c are composed of Au-Ge, Ni and Au layers on the uppermost impurity-doped InGaAs layer 7. By heat treatment, the alloy layer becomes a undoped InGaAs layer corresponding to a channel layer. 3
Has been reached.

The gate electrode 8a is formed in a recess formed between the source / drain ohmic electrodes 8b and 8c, and its contact is made of an impurity-free InAlAs.
Made on layer 6. The gate electrode 8a is a Schottky electrode. Mo, Ti, Pt,
Au having a gate length of 1 μm in which Au is stacked in this order is used.

The gate electrode and the recess are formed by plasma CV.
It is covered with a SiN film 9 deposited by the D method.

The initial characteristics of this semiconductor device are that the transconductance is 400 mS / mm, the Schottky barrier height of the gate electrode is 0.6 eV, and the gate reverse breakdown voltage is 7 V.

FIG. 2 is a diagram showing a change in drain current when an electric field thermal stress is applied to the semiconductor device shown in FIG. When the semiconductor device is heated at a storage temperature of 300 ° C. for 1 hour without applying a bias, the drain current becomes 200 m.
It deteriorated greatly from A / mm to 100 mA / mm. When elemental composition analysis was performed on each part in the depth direction of this semiconductor device by two-dimensional ion mass spectrometry (SIMS), a large amount of fluorine that was not detected before thermal storage was observed, and the detected location was almost doped with impurities. It was limited to the InAlAs layer 5. Therefore, this fluorine is an n-type I doped with impurities.
This is considered to be related to the passivation of the nAlAs layer 5.

Next, the semiconductor device whose current was reduced was stored at a storage temperature of 300 ° C. with a gate voltage of +0.8 V applied for 2 hours. As a result, the drain current of the semiconductor device was restored to 150 mA. This is because the fluorine impurity causing the inactivation of the donor is ionized negatively in the donor layer, and the impurity-free In
It is considered that the gas was discharged to the AlAs layer 6.

When SIMS analysis of the semiconductor device is performed again, the amount of fluorine detected in the n-type InAlAs layer 5 is greatly reduced as compared with that before applying the electric field heat stress, and the value is reduced to the recovery of the current deterioration. They are qualitatively responsive.

From the above results, it can be seen that at least the incorporation of fluorine impurities greatly contributes to the passivation of the n-type InAlAs layer 5. Fluorine that has caused donor inactivation is applied at least partially to the impurity-doped n-type InAlAs layer 5 from the impurity-doped n-type InAlAs layer 5 by applying an electric field while applying thermal stress.
It can be seen that it is discharged to the nAlAs layer 6.

This phenomenon is caused by negatively ionized semiconductor impurities,
In the case of this semiconductor device, it is fluorine ionized negatively,
This is because the bias applied to the gate electrode 8a moves back and forth between the semiconductor device surface and the donor layer. That is, as shown in FIG. 2, by applying a negative bias to the gate electrode 8a, fluorine existing in the undoped InAlAs layer 6 is changed to undoped AlGa as a donor layer.
It mixes in the As layer 5 and inactivates the silicon donor, so that the amount of drain current decreases. Further, as shown in FIG. 3, when a positive bias is applied to the gate electrode 8a, fluorine mixed in the donor layer to inactivate the silicon donor is dissociated by obtaining thermal energy, and the surface of the semiconductor device is formed again. It is considered that the impurities are also discharged to the impurity-free InAlAs layer 6.

Here, InA fabricated on an InP substrate is used.
Although shown by the heterojunction FET using the lAs / InGaAs material, this phenomenon is essentially a fluctuation phenomenon of the activation rate due to mixing and discharging of impurities into the n-type doped InAlAs material. Therefore, even when the present invention is applied to a structure in which only n-type InAlAs is formed on an InP substrate, impurities of fluorine ions can be similarly discharged.

Next, another example of the semiconductor device manufactured by the manufacturing method of the present invention will be described. FIG. 5 shows the structure of the semiconductor device. In the epitaxial structure of the semiconductor device, undoped Al is formed on a semi-insulating GaAs substrate 21.
GaAs layer 22 is 500 nm, impurity-doped InGaAs
the s layer 23 is 20 nm, and the impurity-free AlGaAs layer 24
Is 3 nm, 3 × 10 ¹⁸ cm ^-3 to which silicon is added
lGaAs layer 25 is 150 nm, and impurity-free AlGa
The As layer 26 is 20 nm, and the GaAs layer 27 to which silicon is added at 3 × 10 ¹⁸ cm ⁻³ is 20 nm, and the GaAs layers 27 are stacked in this order.

The ohmic electrodes 28b and 28c as the source and drain electrodes are composed of Au—Ge, Ni and Au on the uppermost GaAs layer 27, and the alloy layer is doped with impurities corresponding to the channel by heat treatment. It reaches the InGaAs layer 23.

The gate electrode 28a is an ohmic electrode 28
The contact is formed in the AlGaAs layer 26 with no impurity added, formed in a recess formed between b and 28c. Mo, Ti, Pt, A
u having a gate length of 1 μm in this order. The semiconductor device is covered with a SiN film 29 deposited by a plasma CVD method.

As an initial characteristic of the semiconductor device, the transconductance is 350 mS / mm. The Schottky barrier height is 0.7 eV, and the gate reverse breakdown voltage is 12 V.

When this semiconductor device was heated at a storage temperature of 400 ° C. for one hour, the drain current was significantly deteriorated from 180 mA / mm to 120 mA / mm, as in the first example shown in FIG.

When elemental composition analysis is performed on each part in the depth direction of the semiconductor device by two-dimensional ion mass spectrometry (SIMS),
A large amount of undetected fluorine was observed before the heat storage, and the detected portion was almost limited to the impurity-added n-type AlGaAs layer 25 portion. Therefore, this fluorine is n-type A
This is considered to be related to the passivation of the lGaAs layer 25.

The semiconductor device was stored at a storage temperature of 400 ° C. for 2 hours with a gate voltage of +0.8 V applied. As a result, the drain current of the semiconductor device was 150 m
It recovered to A. This is considered that the fluorine impurity causing the inactivation of the donor was negatively ionized in the donor layer, and was discharged to the impurity-free AlGaAs layer 26 by the heat energy and the electric field.

When SIMS analysis of the same semiconductor device is performed again, the amount of fluorine detected in the n-type AlGaAs layer 25 becomes
The value is significantly reduced as compared with that before applying the electric field heat stress, and the value qualitatively corresponds to the recovery from the current deterioration. From the above results, it can be seen that at least the incorporation of fluorine impurities greatly contributes to the passivation of the impurity-added n-type AlGaAs layer 25. Fluorine that has caused donor inactivation is at least partially doped with n-type AlGaAs by applying an electric field while applying thermal stress.
It can be seen that the s-layer 25 is discharged to the impurity-free AlGaAs layer 26 on the electrode side to which the electric field is applied.

From the above experimental results and measurement results, a method of manufacturing a semiconductor device in a case where even if fluorine is mixed in as an impurity, the impurity is discharged and normal operation is performed will be described below.

As shown in FIG. 6, the semi-insulating InP substrate 1
On top, the undoped InAlAs layer 2 is 500 nm, the undoped InGaAs layer 3 is 20 nm,
The nAlAs layer 4 is 5 nm, the InAlAs layer 5 with 3 × 10 ¹⁸ cm ⁻³ doped with silicon is 150 nm, the InAlAs layer 6 without impurities is 20 nm, and the InGaAs layer 7 with 3 × 10 ¹⁸ cm ⁻³ doped with silicon. Are laminated in this order to form a semiconductor laminated structure.

Subsequently, a photoresist 11 is applied on the semiconductor laminated structure, and a mesa-shaped pattern is transferred by an exposure and development process. Subsequently, mesa etching is performed by solution etching. The etching depth is the same as the impurity-free I
It reaches halfway through the nAlAs layer 6. For the etching, a mixed solution of phosphoric acid, hydrogen peroxide and water is used. FIG.
(A) does not show the state of the mesa etching, but will be apparent to those skilled in the art.

Subsequently, as shown in FIG. 7A, a photoresist 11 is applied, and an ohmic pattern is transferred by exposure and development.

Next, as shown in FIG. 7B, Au, Ge, and Ni were added to the pattern at 100 nm and 50 nm, respectively.
and a lift-off of 50 nm. Thus, a laminated metal pattern is formed at the position where the ohmic electrode is formed. Subsequently, a heat treatment at 400 ° C. is performed in a hydrogen atmosphere. As a result, the laminated metal becomes an alloy. The formation of the source electrode 8a and the drain electrode 8b is completed by alloying the electrodes.

Subsequently, as shown in FIG. 8A, a photoresist 12 is applied on the semiconductor laminated structure, and a gate recess opening pattern is transferred by exposure and development. The gate opening by the pattern is 1 μm. The opening pattern matches the center of the opening substantially at the center between the ohmic electrodes. Subsequently, as shown in FIG. 8B, a gate recess is formed on the pattern by solution etching. As an etchant used for the etching, for example, a mixed solution of phosphoric acid, hydrogen peroxide solution and water is used. The depth of the recess ends in the middle of the undoped InAlAs layer 6.

Next, as shown in FIG. 9A, a gate electrode is formed on the gate opening photoresist pattern by vapor deposition lift-off of a gate metal. Here, as the gate electrode metal, 50 nm, 50 nm, and 500 n, respectively.
m of Ti, Pt and Au are laminated.

Finally, as shown in FIG. 9B, after forming the gate electrode, for example, an SiN film is entirely formed by a plasma CVD method at a film forming temperature of 330 ° C., and a photoresist is coated and exposed and developed again. To form an opening pattern in a part of each electrode, and perform patterning to enable electrical conduction to the electrodes.

The SiN film in the opening pattern is removed from the above pattern by etching with buffered hydrofluoric acid.

As the initial characteristics of the device, a transconductance of 400 mS / mm was obtained. Further, a Schottky barrier height of 0.6 eV was obtained, and a gate reverse breakdown voltage of 7 V was obtained.

Next, as shown in FIG. 10, a positive bias voltage of 0.6 V or more is applied to the gate electrode at room temperature or more, for example, at an environmental temperature of 100 ° C. or more. The application time is 2
Time. By this step, impurity-added InAlAs
Fluorine ions can be discharged from the layer 5 to the impurity-free InAlAs layer 6.

As described above, the potential of the electrode formed on the surface side is reduced when negatively ionized impurities such as fluorine and oxygen enter the semiconductor, and the potential of the electrode formed on the surface side is reduced to about the Fermi level or lower. By setting to, it is possible to intentionally discharge to the surface.

When ions are moved in the semiconductor laminated structure, the mobility of the ions is a function of the temperature, the polarity and magnitude of the applied bias voltage, and the application time. Therefore, if electric field thermal stress is applied at a temperature higher than room temperature, for example, at an environmental temperature of 400 ° C., ions can be moved faster even when the same bias voltage is applied. Also, at the same environmental temperature, ions can be moved faster by applying a high bias voltage. In addition, if the bias voltage application time is long, more ions can be moved. In this case, since the ion mobility depends more on the environmental temperature than on the applied bias voltage, it is desirable to perform the electric field thermal stress step at a temperature higher than room temperature.

Although the above embodiment has been described using a specific material and a specific value, this is for easy understanding, and the present invention is not limited to this. For example, the impurity that inactivates the donor, which is the point of the present invention, is exemplified by fluorine here. However, any ion that can move relatively freely by obtaining heat energy in a semiconductor is similarly used. The effect can be expected.

In the crystal structure to which the present semiconductor process is applied, the thickness of each layer, the doping concentration, etc. do not need to be the values shown here.
A structure in which an AlAs layer or an AlGaAs layer is subjected to planar doping of Si or the like is also effective in the present invention.

Although silicon is used here as an original donor impurity, this is not particularly limited to silicon as long as it is a material that enables n-type doping. Even so, the process of the present invention is effective.

The material constituting the electrode to which the electric field is applied is not limited to the Mo / Ti / Pt / Au laminated structure, but may be WSi, W, Ti / Al, Ti / P.
It is possible to use a single layer or a stack of various metals such as t / Au, Pt / Ti / Pt / Au, and Al.

[0058]

According to the present invention, it becomes possible to mix and discharge impurity ions that cause donor inactivation due to thermal stress, which has become a problem, in a semiconductor device using n-type InAlAs or n-type AlGaAs. In addition, a semiconductor memory can be manufactured using the phenomenon.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view showing a structure of a semiconductor device manufactured by a manufacturing method of the present invention.

FIG. 2 is a cross-sectional view of the semiconductor device for explaining the principle of the manufacturing method of the present invention.

FIG. 3 is a sectional view of a semiconductor device for explaining the principle of the manufacturing method of the present invention.

FIG. 4 is a diagram showing characteristics of drain current for explaining the principle of the manufacturing method of the present invention.

FIG. 5 is a diagram showing a structure of another semiconductor device manufactured by applying the manufacturing method of the present invention.

FIG. 6 is a cross-sectional view of the semiconductor device for explaining the manufacturing method of the present invention.

FIG. 7 is a cross-sectional view of the semiconductor device for explaining the manufacturing method of the present invention.

FIG. 8 is a cross-sectional view of the semiconductor device for explaining the manufacturing method of the present invention.

FIG. 9 is a cross-sectional view of the semiconductor device for explaining the manufacturing method of the present invention.

FIG. 10 is a cross-sectional view of the semiconductor device for explaining the manufacturing method of the present invention.

[Explanation of symbols]

 Reference Signs List 1 semi-insulating InP substrate 2 undoped InAlAs layer 3 undoped InGaAs layer 4 undoped InAlAs layer 5 undoped InAlAs layer 6 undoped InAlAs layer 7 undoped InGaAs layer 8a gate electrode 8b source electrode 8c drain electrode 9 SiN protective film 11, 12 resist 21 semi-insulating GaAs substrate 22 impurity-free AlGaAs layer 23 impurity-free InGaAs layer 24 impurity-free AlGaAs layer 25 impurity-doped AlGaAs layer 26 impurity-free AlGaAs layer 27 impurity-doped GaAs layer 28a gate electrode 28b source electrode 28c drain electrode 29 SiN protective film

Claims (11)

[Claims] A step of forming a semiconductor multilayer structure including a plurality of semiconductor layers, wherein the semiconductor multilayer structure includes a first layer and a second layer for supplying carriers, and Forming a first electrode structure, and transferring negatively ionized impurities in the second layer to the first layer by electric field stress. 2. The method according to claim 1, wherein the second layer is made of an impurity-doped InAlA.
The method according to claim 1, wherein the semiconductor device is an s layer. 3. The method according to claim 1, wherein the first layer is made of undoped InAl.
3. The method according to claim 2, wherein the semiconductor device is an As layer. 4. The method according to claim 1, wherein the second layer is made of AlGaAs doped with impurities.
The method according to claim 1, wherein the semiconductor device is an s layer. 5. The method according to claim 1, wherein the first layer is made of an impurity-free AlGa.
5. The method according to claim 4, wherein the semiconductor device is an As layer or a GaAs layer containing no impurities. 6. The method according to claim 1, wherein the moving includes applying a positive bias voltage greater than a predetermined value to the first electrode structure to cause the negatively ionized impurities in the second layer to move to the first layer. The method of manufacturing a semiconductor device according to claim 1, further comprising a step of moving. 7. The step of moving comprises applying a positive bias voltage greater than a predetermined value to the first electrode structure at a temperature higher than room temperature to remove negatively ionized impurities in the second layer. The method for manufacturing a semiconductor device according to claim 6, further comprising a step of moving the semiconductor device to the first layer. 8. The Schottky electrode structure according to claim 6, wherein the first electrode structure is a Schottky electrode structure, and the predetermined value is a threshold value of the Schottky electrode structure.
Or a method for manufacturing a semiconductor device according to item 7. 9. The semiconductor device according to claim 1, further comprising a second and a third electrode on both sides of the first electrode structure apart from the first electrode structure.
9. The method for manufacturing a semiconductor device according to claim 1, further comprising the step of forming said electrode structure. 10. The semiconductor device according to claim 1, further comprising forming a recess except at least a part of an uppermost layer of the semiconductor multilayer structure, wherein the first electrode structure is formed in the recess. A method for manufacturing a semiconductor device according to claim 1. 11. The method for manufacturing a semiconductor device according to claim 1, wherein said negatively ionized impurity is fluorine or oxygen.