JPH0566988A - Access controller for computer system - Google Patents

Abstract

PURPOSE:To change the continuous time of each select signal each time an access request is generated, to omit the secure of a useless recovery period, to shorten average required access time and to improve the throughput of an entire system by detecting whether a relevant circuit member is under the recovery period or not for each circuit member. CONSTITUTION:A recovery period detecting circuit 11 is provided to detect whether respective relevant circuit members 7 and 8 are under the recovery period or not for the respective circuit members 7 and 8 and to output an under- recovery period signal when the members are under the recovery period. Further, a control logic circuit is provided to inhibit the outputs of select signals to the relevant circuit members 7 and 8 when this under-recovery period signal is under an output period. When access is generated to the same circuit member, the control logic circuit is operated so as to prevent the select signal of the next access from being inputted to the relevant circuit members 7 and 8 during the recovery period. Since the select signal of the next access is immediately inputted to the relevant circuit members just after the preceding access is completed, in this case, it is not necessary to wait for the lapse of the recovery period.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a computer system using a processor such as a CPU (central processing unit), and more particularly to a peripheral L incorporated in this computer system.
The present invention relates to an access control device for a computer system capable of efficiently executing access to a circuit member such as SI.

[0002]

2. Description of the Related Art Generally, in a computer system of a relatively small scale such as a microcomputer or a personal computer in which a CPU is incorporated, as shown in FIG.
For the PU1, for example, a ROM 2 that stores fixed data such as a control program and an R that temporarily stores various variable data.
The AM 3 is connected via the address bus 4, the data bus 5 and the control bus 6. Further, a plurality of circuit members 7 such as an input / output interface for inputting data from the outside or outputting a calculation result to the outside and an input / output port for inputting / outputting data to / from a display device or an external storage device. , 8 are connected. In general, these circuit members 7 and 8 are formed of an LSI (Large Scale Integrated Circuit) and are generally called peripheral LSIs.

The address decoder 9 also selects signals (chip selector signals) CS _RO , CS _RA , CS for designating the electronic components 2, 3, 7, 8 which the CPU 1 should access.
Outputs _A , CS _BR , and CS _BW . The circuit member 8 selects the signal C for writing data to the circuit member 8.
S _BW and the selection signal CS _BR for reading data are output independently.

In such a computer system, the CP
Each electronic component 2, 3, 7, 8 can be specified by an address signal and a control signal of a plurality of bits such as 16 bits or 32 bits output from U1. That is, when the CPU 1 executes access to the circuit member 7, for example,
An address signal AD _A specifying the corresponding circuit member 7 is output to the address bus 4 and a control signal is output to the control bus 6.
Then, the selection signal C output from the address decoder 9
Only S _A is in the operating state (L level). Therefore,
When the CPU 1 outputs the read signal RD via the control bus 6, data is output from the circuit member 7 to the data bus 5,
The CPU 1 can read this data.

Further, the CPU 1 uses, for example, a specific circuit member 7
When writing data to the address decoder 9
When the write signal WR is output to the control bus 6 and the data is output to the data bus 5 while the selection signal CS _A is output from the target circuit member 7 to the target circuit member 7, the corresponding data is written to the circuit member 7. ..

[0006]

However, there are still the following problems to be improved in the computer system which executes the access to the circuit members 7 and 8 formed of the LSI by the above-mentioned procedure. ..

That is, as shown in FIG. 7 (a), the actual access processing is performed within the operation state (L level) period T ₁ of the selection signal CS for the target circuit members 7, 8.

However, in the circuit members 7 and 8 composed of peripheral LSI such as the above-mentioned input / output interface, input / output port, and various converters which are generally commercially available, FIG.
As shown in (a), a predetermined recovery time is set in advance from the time when the actual access processing is completed to the time when the circuit members 7 and 8 are restored to the original access acceptable state. The time required for this recovery is the normal recovery period T ₂
That.

Then, during the recovery period T ₂ , execution of access processing is prohibited. On the other hand, when accessing the same circuit member continuously,
Since the selection signal CS for the relevant circuit member has been restored immediately after the end of the previous access processing, the CPU 1 immediately outputs the selection signal CS for the next access. Then,
The next access cannot be executed when the recovery period T ₂ for the previous access is not completed.

In order to prevent such a recovery time violation in advance, as shown in FIG. 7B, even if the actual access processing is finished and the selection signal CS is immediately restored,
A method is adopted in which the dummy cycle is executed to restore the access processing after the recovery period T _{2 has} elapsed. Therefore, in this case, even if access requests are successively issued to the same circuit member 7, the access processing does not overlap the recovery period T ₂ .

As a method of extending the access processing for one circuit member to the time T ₀ obtained by adding the recovery period T ₂ from the time T ₁ corresponding to the original access time, a software means using a program, Address decoder 9
For example, a method of providing a counter therein and extending it by hardware is adopted.

However, if the access process for one circuit member is uniformly delayed by the recovery period T ₂ , the following problem occurs. For example, as shown in FIG. 7C, when access requests are successively issued to different circuit members 7 and 8, even if the two access processes are close to each other, the recovery period T of each other is reduced. ₂ is sufficiently secured.
Therefore, in such a case, the access processing time for each circuit member should be set to the time T ₁ corresponding to the access time shown in FIG.

However, as described above, if the access processing to one circuit member is uniformly delayed by the recovery period T ₂ , the time required for one access becomes long, and the processing speed of the entire computer system decreases. Occurs.

The present invention has been made in view of such circumstances, and each detection is made for each circuit member by detecting whether or not the corresponding circuit member is in the recovery period. An object of the present invention is to provide an access control device for a computer system, which can change the signal duration, omit unnecessary recovery periods, shorten the average access time, and improve the processing efficiency of the entire system.

[0015]

In order to solve the above problems, an access control device of the present invention connects a plurality of circuit members composed of LSI to a CPU via a bus line, and
The address signal output from the PU is converted into a selection signal indicating whether or not the corresponding circuit member is selected for each circuit member by the decoder, and the CPU selects the selection signal while the selection signal is output to each circuit member. In a computer system that executes access to a circuit member specified by a signal, it is provided for each circuit member and outputs a signal during the recovery period from the end of access to each circuit member until the lapse of a predetermined recovery required time A plurality of recovery period detection circuits, and is inserted in the signal path of the selection signal for each circuit member,
The corresponding circuit member is provided with a plurality of control logic circuits that prohibit the output of the selection signal to the corresponding circuit member during the recovery period.

[0016]

According to the access control device of the computer system configured as described above, the recovery period detection circuit provided for each circuit member outputs a signal during the recovery period after the end of access to the corresponding circuit member during the recovery period. Is output. The signal during this recovery period is input to the control logic circuit inserted in the signal path of the selection signal from the decoder which is input to the corresponding circuit member. The control logic circuit prohibits the selection signal input during the recovery period from being output to the circuit member.

As described above, when consecutive access requests to the same circuit member are generated, the control logic circuit operates and the selection signal for the next access is not input to the corresponding circuit member within the recovery period. .. On the other hand, when consecutive access requests to different circuit members occur,
Immediately after the previous access is completed, a signal during the recovery period is input to the control logic circuit corresponding to the circuit member of the access request. However, no signal is input during the recovery period to the control logic circuit of the circuit member to be accessed later. Therefore, as soon as the previous access is completed, the selection signal for the next access is input to the corresponding circuit member. Therefore, in this case, it is not necessary to wait for the recovery period to elapse.

[0018]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing the entire computer system in which the access control device of the embodiment is incorporated. Figure 6
The same parts as those in FIG.

In this embodiment, the CPU 1 and the RO
M2, RAM3, and circuit members 7, 8 each composed of an LSI are connected by an address bus 4, a data bus 5, and a control bus 6, respectively.

The address bus 4 and the control bus 6 connected to the CPU 1 are input to the address decoder section 10. Further, the control bus 6 is the recovery period detection circuit 1
It is also input to 1. Further, a clock signal CLK is applied to the CPU 1, the address decoder section 10 and the recovery period detection circuit section 11.

The address decoder section 10 is constructed as shown in FIG. That is, from outside the address bus 4
Address signal AD and control bus 6 input via
The control signal input via the
Input to decoders 12a-12d dedicated to 7 and 8.

The ROM decoder 12a applies an L level selection signal CS _RO to the CS terminal of the ROM 2 when the address signal AD and the control signal match the logical values set in advance for the ROM 2. Similarly, the RAM decoder 12b
When the address signal AD and the control signal match the logical values set in the RAM 3 in advance, the L level selection signal CS _{RA is changed} to R
Apply to the CS terminal of AM3.

Further, when the address signal AD and the control signal coincide with the logical value set in the circuit member 7 in advance, the LSIA decoder 12c sends the H level selection signal to one input terminal of the AND gate 13a as the control logic circuit. Send to. At the other input end of the ANDCADE 13a, a recovery period signal RC _A output from the recovery period detection unit 11
Is entered. When the selection signal of H level is input to the AND gate 13a during the recovery period when the signal RC _A is in the H level period, that is, in the period other than the recovery period, the AND gate 13a outputs the selection signal CS _{A of} L level to the CS terminal of the circuit member 7. Is entered.

Further, the LSIB reading decoder 12d
Sends an H level selection signal to one input terminal of an AND gate 13b as a control logic circuit when the address signal AD and the control signal match the logic value set in advance for the read operation of the circuit member 8. The recovery period signal RC _B output from the recovery period detection unit 11 is input to the other input terminal of the ANDCADE 13b. AND gate 13b
When the signal RC _B during the recovery period receives the H-level selection signal during the H-level period, outputs the selection signal to the input terminal D of the D-type flip-flop 15a. Then, this selection signal is synchronized with the next falling edge of the clock signal CLK input through the inverter 16 and the flip-flop 1
It is output as an L level selection signal CS _BR from the inverting output terminal of 5a and applied to the reading CS terminal of the circuit member 8.

Similarly, an LSIB writing decoder 12e
Sends an H level selection signal to one input terminal of the AND gate 13c as a control logic circuit when the address signal AD and the control signal match the logic value set in advance for the writing operation of the circuit member 8. The signal RC _B during the recovery period is input to the other input terminal of the ANDCADE 13c. When the selection signal is input while the signal RC _B is in the H level during the recovery period, the selection signal is input from the ANDCADE 13b to the input terminal D of the flip-flop 15b and is inverted and output in synchronization with the next falling edge of the clock signal CLK. From terminal to L
The level selection signal CS _BW is applied to the writing CS terminal of the circuit member 8.

A system reset signal RES is applied to each clear terminal C of the flip-flops 15a and 15b via the control bus 6 when the computer system is powered on.

FIG. 3 is a detailed circuit diagram of the recovery period detector 11. The recovery period detector 11 is roughly divided into the circuit member 7 from the end of access to the circuit member 7.
Recovery period detection circuit 11a that outputs a recovery period signal RC _A that indicates that a predetermined recovery period that is determined by the specifications of No. 1 and a recovery period signal RC _B that indicates that the recovery period for the circuit member 8 is also being recovered. And a recovery period detection circuit 11b that outputs

In the recovery period detection circuit 11a, the selection signal CS _A input from the address decoder unit 10 is input to one input terminal of the NOR gate 17. An address strobe signal STB is applied to the other input end of the NOR gate 17 via the control bus 6. The output signal of the NOR gate 17 is six D-type flip-flops 18.
It is input to the delay circuit composed of a to 18f. The selection signal CS _A output from the inverting output terminal of the final stage flip-flop 18 f of the delay circuit is input to the OR gate 19. The output signal of the NOR gate 17 is applied to the other input terminal of the OR gate 19. The output signal of the OR gate 19 is sent to the address decoder unit 10 as a signal RC _A during the recovery period.

In such a recovery period detecting circuit 11a, each flip-flop 18a-1
Since 8f is in the clear state, the output signal of the inverting output terminal of the final stage flip-flop 18f is in the H level state. Therefore, the recovery period signal RC _A output from the recovery period detection circuit 11a is also in the H level state. In this state, the address strobe signal STB
There when the selection signal CS _A in L level state changes to the L level, the output signal of the NOR gate 17 but rises to H level, the output of the OR gate 19 maintains the L level,
The signal RC _A maintains the H level state during the recovery period.

The rising operation of the output signal of the NOR gate 17 to the H level is sequentially transmitted in synchronization with the clock signal CLK input through the inverter 20 to the flip-flops 18a to 18f forming the delay circuit. ..

When the access operation is completed and selection signal CS _A and address strobe signal STB rise to H level, the output signal of NOR gate 17 falls to L level. Further, at this point, if the previous rising operation of the output signal to the H level reaches the final flip-flop 18f, the output of the OR gate 19 changes to the L level, and the signal RC _A during the recovery period changes to the L level state. To do. This L level state is an address tove signal or a selection signal CS.
The rising operation of _A continues for a period while reaching the flip-flop 18f at the final stage of the delay circuit.

Therefore, this recovery period detection circuit 1
1a outputs a signal RC _A during the recovery period in which the L level is maintained for a predetermined recovery period from the end of the access operation to the circuit member 7.

The recovery period detection circuit 11b for the other circuit member 8 also has the structure and operation according to the recovery period detection circuit 11a for the circuit member 7 described above. That is, the selection signals CS _BR and CS _BW input from the address decoder unit 10 are input to the NAND gate 21. The output signal of the NAND gate 21 is input to the OR gate 23 via the delay circuit composed of five flip-flops 22a to 22e, and is also directly input to the OR gate 23. The output signal of the OR gate 23 is the address decoder unit 1 as the signal RC _B during the recovery period.
Sent to 0.

Also in the recovery period detection circuit 11b, one of the selection signals CS _BR and CS _BW changes to the L level in the process of the CPU 1 accessing the corresponding circuit member 8 and goes to the H level after the access is completed. When returning, the signal RC _B during the recovery period which is at the L level for a predetermined recovery period from the end of access is output.

Next, the operation of the entire computer system in which the access control device thus constructed is incorporated will be described with reference to the time charts of FIGS. 4 and 5.

First, FIG. 4 shows a case where the same circuit member 8 is continuously accessed. CPU1 is time t
_In order to perform read access to the circuit member 8 at _1, the address signal AD _BR and the control signal designating the read corresponding to the corresponding circuit member 8 are output to the address bus 4 and the address strobe signal STB is changed to the L level. .. Then, the next falling time t of the clock signal CLK
_{At 2} , the LSIB reading decoder 12d outputs a selection signal. Then, the signal RC _B during the recovery period from the recovery period detection circuit 11b is H level at the AND gate 13b.
When it is confirmed that the address strobe signal STB is in the level state and the address strobe signal STB is in the level state, the address decoder unit 10 outputs the selection signal CS _BR at the L level to the circuit member 8.

Thus, the CPU 1 reads the data of the circuit member 8 via the data bus 5. When the data read access processing is completed, the address strobe signal STB is released to H level at time t ₃ , and the selection signal CS _BR is also released.

Therefore, the CPU 1 subsequently continues to the same circuit member 8
In order to execute a read access to the memory _{cell, the} same address signal AD _BR and control signal as described above are output at time t ₄ . At the same time, the address strobe signal STB is changed to L level. However, this time, as described above, since the signal RC _B is changing to the L level during the recovery period of the same circuit member 8, the AND gate 13b is not established at the time t ₅ , so the LSI B reading is performed. The selection signal output from the decoder 12d for AND gate 1
It is cut off at 3b. As a result, the selection signal CS _BR for the circuit member 8 is not output. Therefore, the CPU 1 cannot access the circuit member 8.

Since the access processing is not completed, the address signal AD _BR and the address strobe signal STB maintain the output state. Then, when the signal RC _B is released during the recovery period at time t ₆ , the AND gate 13b is established at the next falling time t ₇ of the clock signal CLK and the selection signal CS _BR is applied to the circuit member 8. It

Next, a case in which different circuit members 8 and 7 are continuously accessed will be described with reference to FIG.

When the CPU 1 outputs the address signal AD _BR and the control signal corresponding to the circuit member 8 at the time t _{1 and} sets the address strobe signal STB to the L level, the circuit at the time t ₂ is the same as in FIG. The selection signal CS _BR for the member 8 changes to the L level, and the CPU 1 executes the data read access. Then, the access ends, and the time t
_{At 3} , the address strobe signal STB and the selection signal CS _BR return to H level.

Next, at time t ₄ , the CPU 1 outputs the address AD _A and the control signal corresponding to the other circuit member 7 and sets the address strobe signal STB to L level. Then, at this time, since the signal RC _A during the recovery period of the circuit member 7 is in the H level state, the time t
_The AND gate 13a is established at _5, and the corresponding circuit member 7
Selection signal CS _A for changes to L level, and CPU1
Performs a read access to the data. Then, the access is completed, and at time t ₆ , the address strobe signal ST
B and the selection signal CS _A are returned to the H level.

As described above, when consecutive accesses are made to the same circuit member, as shown in FIG. 4, a recovery period is forcibly inserted between the access operation periods. Further, when performing continuous access to different circuit members, the recovery period is excluded as shown in FIG.

In general, the probability of continuously accessing the same circuit member is small, and as a result, the average access time required by the CPU 1 is compared with the case where the recovery period is forcibly added uniformly. Is greatly shortened. Therefore, the processing efficiency of the computer system as a whole is improved.

[0046]

As described above, according to the computer system of the present invention, it is detected for each circuit member whether or not the corresponding circuit member is in the recovery period, and if it is in the recovery period, the recovery period signal is output. During the recovery period, the selection signal output to the corresponding circuit member is prohibited during the output period. Therefore, the duration of each selection signal can be changed each time an access request is generated, unnecessary recovery period can be omitted, and the average access time can be shortened. As a result, the processing efficiency of the entire computer system can be improved.

[Brief description of drawings]

FIG. 1 is a block diagram showing an entire computer system incorporating an access control device according to an embodiment of the present invention,

FIG. 2 is a block diagram showing an address decoder section of the apparatus of the embodiment.

FIG. 3 is a block diagram showing a recovery period detection unit of the apparatus of the embodiment.

FIG. 4 is a time chart showing the operation of the apparatus of the embodiment.

FIG. 5 is a time chart showing the operation of the apparatus of the same embodiment,

FIG. 6 is a block diagram showing a general computer system,

FIG. 7 is a diagram for explaining a relationship between a selection signal and a recovery period in the same general computer system.

[Explanation of symbols]

1 ... CPU, 2 ... ROM, 3 ... RAM, 4 ... Address bus, 5 ... Data bus, 6 ... Control bus, 7, 8 ... Circuit member, 10 ... Address decoder section, 11 ... Recovery period detection section, 11a, 11b ... Recovery period detection circuit, 12c
... LSIA decoder, 12d ... LSIB reading decoder, 12e ... LSIB writing decoder, 13a, 13
b, 13c ... AND gate (control logic circuit), 18a ...
18f, 22a-22e ... Flip-flops.

Claims (1)

[Claims] 1. A plurality of circuit members (7, 8) composed of LSI are connected to a CPU (1) via bus lines (4,5, 6),
The address signal output from the CPU is decoded by the decoder (12
c, 12d, 12e) is converted into a selection signal indicating whether or not the corresponding circuit member is selected for each of the circuit members, and the CPU outputs the selection signal to each of the circuit members. In a computer system that executes an access to a circuit member specified by a selection signal, a signal is provided for each circuit member, a period from the end of access to each circuit member until a predetermined recovery required time elapses, and a recovery period signal. Outputting a plurality of recovery period detection circuits (11a, 11b) and the signal path of the selection signal for each circuit member, the corresponding circuit member prohibits the output of the selection signal to the corresponding circuit member during the recovery period. An access control device for a computer system including a plurality of control logic circuits (13a, 13b, 13c) that perform