JPH056688Y2 - - Google Patents
Info
- Publication number
- JPH056688Y2 JPH056688Y2 JP3560786U JP3560786U JPH056688Y2 JP H056688 Y2 JPH056688 Y2 JP H056688Y2 JP 3560786 U JP3560786 U JP 3560786U JP 3560786 U JP3560786 U JP 3560786U JP H056688 Y2 JPH056688 Y2 JP H056688Y2
- Authority
- JP
- Japan
- Prior art keywords
- thin film
- layer
- thick film
- solder
- circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000010409 thin film Substances 0.000 claims description 13
- 229920005989 resin Polymers 0.000 claims description 9
- 239000011347 resin Substances 0.000 claims description 9
- 239000004020 conductor Substances 0.000 claims description 7
- 239000010408 film Substances 0.000 description 18
- 229910000679 solder Inorganic materials 0.000 description 11
- 239000000758 substrate Substances 0.000 description 9
- 238000005476 soldering Methods 0.000 description 7
- 238000000034 method Methods 0.000 description 5
- 239000011521 glass Substances 0.000 description 4
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 3
- 230000007547 defect Effects 0.000 description 2
- 238000004806 packaging method and process Methods 0.000 description 2
- 239000004593 Epoxy Substances 0.000 description 1
- 239000004642 Polyimide Substances 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 230000002950 deficient Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000010292 electrical insulation Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000004927 fusion Effects 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 238000002161 passivation Methods 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 238000007650 screen-printing Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 238000011179 visual inspection Methods 0.000 description 1
Landscapes
- Parts Printed On Printed Circuit Boards (AREA)
- Non-Metallic Protective Coatings For Printed Circuits (AREA)
Description
【考案の詳細な説明】
〔産業上の利用分野〕
本考案は厚膜基板上に、搭載電子部品の半田付
け接続が行なわれる薄膜の回路パターンが形成さ
れた混成集積回路基板に関する。[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a hybrid integrated circuit board in which a thin film circuit pattern to which mounted electronic components are soldered is formed on a thick film board.
従来、この種の混成集積回路基板は、アルミナ
等からなる絶縁基板上に厚膜導体層、厚膜抵抗体
層、厚膜絶縁体ガラス層、厚膜回路保護層を設け
た厚膜基板上に、薄膜回路を形成しただけであつ
た。
Conventionally, this type of hybrid integrated circuit board has been fabricated on a thick film substrate in which a thick film conductor layer, a thick film resistor layer, a thick film insulator glass layer, and a thick film circuit protection layer are provided on an insulating substrate made of alumina or the like. , only a thin film circuit was formed.
厚膜基板上に薄膜回路を形成した、いわゆる、
厚膜薄膜融合基板は、高密度実装を行なうため
に、配線間隔が最小数10μm程度までの高密度配
線パターンの形成ができる薄膜回路が、厚膜回路
と共に用いられているものである。このような高
密度配線パターンを有する回路基板に半田付け工
程を加える場合、半田ブリツジによるシヨート、
あるいは半田くわれ等の発生する危険性が高く、
且つこのような欠陥箇所の手直しは困難を要する
ために、半田付け工程の歩留まりが低いという欠
点があつた。
A so-called thin film circuit formed on a thick film substrate.
A thick-thin film fusion board uses a thin-film circuit that can form a high-density wiring pattern with a minimum wiring spacing of several tens of micrometers together with a thick-film circuit in order to perform high-density packaging. When adding a soldering process to a circuit board with such a high-density wiring pattern, shorts due to solder bridges,
Or, there is a high risk of solder cracks, etc.
Moreover, since it is difficult to repair such defective parts, there is a drawback that the yield of the soldering process is low.
本考案による混成集積回路基板は、厚膜基板上
に形成された薄膜回路パターン上の必要部分に、
ソルダレジストおよび回路パターン保護用の樹脂
層を備えている。
The hybrid integrated circuit board according to the present invention has a thin film circuit pattern formed on a thick film substrate.
Equipped with a resin layer to protect solder resist and circuit patterns.
本考案の実施例について、図面を参照して説明
する。
Embodiments of the present invention will be described with reference to the drawings.
第１図は本考案の一実施例の部分断面図であ
る。第１図において、１はアルミナ等からなるセ
ラミツクス製ベース基板、２は厚膜導体層、３は
絶縁体ガラス層、４は厚膜抵抗体層、５は厚膜回
路保護層、６はNiCr−Pd−Au等の薄膜導体構造
からなる薄膜回路パターン、７はソルダレジスト
および回路保護を目的とした樹脂層部、８は半
田、９は搭載電子部品の外部リードを示す。図に
示されるように、基板上の半田付け用薄膜電極近
傍および微細配線パターン部分に、スクリーン印
刷等の方法を用いて、半田付け工程前にあらかじ
め樹脂層７を形成しておく。この樹脂層形成に用
いられる素材としては、基板表面との密着性、電
気絶縁性、耐熱性、作業性を満たすものが望まし
く、従来よりソルダレジスト、回路保護膜、半導
体パツシベーシヨン膜等に用いられてきたエポキ
シ系、シリコン系、ポリイミド系の樹脂、あるい
は、紫外線硬化型樹脂等の適用が考えられる。ま
た、場合に応じて、低融点ガラスの使用あるいは
絶縁性樹脂フイルムの貼り付け等も用いられる。 FIG. 1 is a partial sectional view of an embodiment of the present invention. In FIG. 1, 1 is a ceramic base substrate made of alumina or the like, 2 is a thick film conductor layer, 3 is an insulating glass layer, 4 is a thick film resistor layer, 5 is a thick film circuit protection layer, and 6 is a NiCr- A thin film circuit pattern made of a thin film conductor structure such as Pd-Au, 7 a solder resist and a resin layer part for circuit protection, 8 solder, and 9 external leads of mounted electronic components. As shown in the figure, a resin layer 7 is previously formed in the vicinity of the thin film electrode for soldering on the substrate and in the fine wiring pattern portion using a method such as screen printing before the soldering process. The material used to form this resin layer is preferably one that satisfies adhesion to the substrate surface, electrical insulation, heat resistance, and workability, and has traditionally been used for solder resists, circuit protection films, semiconductor passivation films, etc. Possible applications include epoxy-based, silicon-based, polyimide-based resins, or ultraviolet curable resins. Further, depending on the case, use of low melting point glass or attachment of an insulating resin film may be used.
厚膜基板上へ薄膜導体による回路構成を行なつた
混成集積回路基板に本考案を適用することによ
り、半田ブリツジによるシヨートおよび半田くわ
れ等半田付け工程におけるトラブルを事前に防ぐ
ことが可能となり、半田不良率を大幅に低減でき
る。また、本考案を適用した混成集積回路基板
は、半田付けされる部分が微細パターン部分を除
いた部分に限定されるため、半田の外観検査に要
する時間の節減がなされる。さらに、本考案の厚
膜薄膜融合基板は、微細回路パターンを有する高
密度実装混成集積回路装置に適用されることで、
半田付け不良が防止される。よつて、半田付手直
し工数の削減という点でも重要な意味をもつ。
By applying the present invention to a hybrid integrated circuit board in which a circuit is constructed using thin film conductors on a thick film board, it becomes possible to prevent troubles in the soldering process such as shorts caused by solder bridges and solder holes. The solder defect rate can be significantly reduced. Further, in the hybrid integrated circuit board to which the present invention is applied, the soldered portion is limited to the portion excluding the fine pattern portion, so that the time required for visual inspection of the solder can be reduced. Furthermore, the thick-thin film fused substrate of the present invention can be applied to high-density packaging hybrid integrated circuit devices having fine circuit patterns.
Soldering defects are prevented. Therefore, it has an important meaning in terms of reducing the number of man-hours required for soldering.
第１図は、本考案の一実施例の部分断面図であ
る。
１……アルミナセラミツク基板、２……厚膜導
体層、３……絶縁体ガラス層、４……厚膜抵抗体
層、５……回路保護層、６……薄膜導体層、７…
…樹脂層、８……半田、９……電子部品外部リー
ド。
FIG. 1 is a partial sectional view of an embodiment of the present invention. DESCRIPTION OF SYMBOLS 1...Alumina ceramic substrate, 2...Thick film conductor layer, 3...Insulating glass layer, 4...Thick film resistor layer, 5...Circuit protection layer, 6...Thin film conductor layer, 7...
...Resin layer, 8...Solder, 9...Electronic component external lead.
Claims (1)
膜絶縁体ガラス層、厚膜回路保護層などを設けた
厚膜基板上に、上層導体として、NiCr−Au，
NiCr−Pd−Au，Ti−Au，Ti−Pd−Auなどの
うちのいずれかの構成の薄膜導体層により回路パ
ターンを形成し、該パターン上部に樹脂パターン
層を形成したことを特徴とする混成集積回路基
板。 NiCr-Au, NiCr-Au,
A hybrid structure characterized in that a circuit pattern is formed by a thin film conductor layer having one of NiCr-Pd-Au, Ti-Au, Ti-Pd-Au, etc., and a resin pattern layer is formed on top of the pattern. integrated circuit board.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3560786U JPH056688Y2 (en) | 1986-03-11 | 1986-03-11 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3560786U JPH056688Y2 (en) | 1986-03-11 | 1986-03-11 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS62147380U JPS62147380U (en) | 1987-09-17 |
| JPH056688Y2 true JPH056688Y2 (en) | 1993-02-19 |
Family
ID=30845256
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3560786U Expired - Lifetime JPH056688Y2 (en) | 1986-03-11 | 1986-03-11 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH056688Y2 (en) |
-
1986
- 1986-03-11 JP JP3560786U patent/JPH056688Y2/ja not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPS62147380U (en) | 1987-09-17 |
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