JP3503232B2 - Structure of printed wiring board - Google Patents

Structure of printed wiring board

Info

Publication number
JP3503232B2
JP3503232B2 JP31959594A JP31959594A JP3503232B2 JP 3503232 B2 JP3503232 B2 JP 3503232B2 JP 31959594 A JP31959594 A JP 31959594A JP 31959594 A JP31959594 A JP 31959594A JP 3503232 B2 JP3503232 B2 JP 3503232B2
Authority
JP
Japan
Prior art keywords
land
paint layer
solder resist
solder
component
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP31959594A
Other languages
Japanese (ja)
Other versions
JPH08181419A (en
Inventor
豊 榎戸
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nissan Motor Co Ltd
Original Assignee
Nissan Motor Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nissan Motor Co Ltd filed Critical Nissan Motor Co Ltd
Priority to JP31959594A priority Critical patent/JP3503232B2/en
Publication of JPH08181419A publication Critical patent/JPH08181419A/en
Application granted granted Critical
Publication of JP3503232B2 publication Critical patent/JP3503232B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/30Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/303Surface mounted components, e.g. affixing before soldering, aligning means, spacing means
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/30Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341Surface mounted components
    • H05K3/3431Leadless components
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/30Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/3452Solder masks
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02PCLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50Manufacturing or production processes characterised by the final manufactured product

Landscapes

  • Non-Metallic Protective Coatings For Printed Circuits (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)
  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】この発明は、プリント配線板の構
造に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a printed wiring board structure.

【0002】[0002]

【従来の技術】従来のプリント配線板の構造としては、
例えば図3に示すようなものがある。まず、構成を説明
する。プリント配線板は、絶縁体である基体部分1があ
り、その上には導電体(銅箔)である配線パターン2が
形成されている。基体部分1の上で一つの配線パターン
2と他の配線パターン2との間には、プリント配線板の
表面を覆い、はんだ付けの際、不要な場所にはんだ4が
付着するのを防ぐためのソルダレジスト7が形成されて
いる。さらに部品を実装機などでマウントする際の認識
や目視確認の目安とするための文字や図形を示す塗料層
3がシルク印刷によってソルダレジスト7の上に形成さ
れている。また、近年電子部品の小型・高密度化が急速
に進展しており、シルク印刷による塗料層3は、上記の
認識や目視確認のほかに、狭ピッチな表面実装部品5
(例えばチップ抵抗器、チップコンデンサ、QFP:ク
ワッド・フラット・パッケージ等)のはんだブリッジを
防ぐ役割をもたせるアイデアも見られる。なお、6は表
面実装部品5の端子である。
2. Description of the Related Art As a conventional printed wiring board structure,
For example, there is one as shown in FIG. First, the configuration will be described. The printed wiring board has a base portion 1 which is an insulator, and a wiring pattern 2 which is a conductor (copper foil) is formed thereon. Between the one wiring pattern 2 and the other wiring pattern 2 on the base portion 1, the surface of the printed wiring board is covered to prevent the solder 4 from adhering to unnecessary places during soldering. The solder resist 7 is formed. Furthermore, a paint layer 3 showing characters and figures for the purpose of recognition and visual confirmation when the component is mounted by a mounting machine or the like is formed on the solder resist 7 by silk printing. Further, in recent years, electronic parts are rapidly becoming smaller and higher in density. In addition to the above-mentioned recognition and visual confirmation, the paint layer 3 formed by silk printing has a narrow pitch surface mount component 5.
There is also an idea of having a role of preventing a solder bridge of a chip resistor, a chip capacitor, a QFP (quad flat package, etc.). In addition, 6 is a terminal of the surface mount component 5.

【0003】[0003]

【発明が解決しようとする課題】しかしながら、このよ
うな従来のプリント配線板の構造においては、シルク印
刷による塗料層の用途が、視認性の向上とブリッジ防止
などの工程歩留まりの向上を目的としたものに止まって
おり、最終的に構成したユニットの長期の耐久信頼性に
注意が払われていなかったため、構成要素の組み合わせ
で、所要の部品の歩留まりは改善されてきているが、長
期の耐久信頼性の観点では何ら進歩が見られず、電子部
品の小型化・高密度に伴って携帯性や耐環境性の性能向
上が望まれるなかで、長期の耐久信頼性の改善だけが取
り残されているという問題点があった。
However, in such a conventional printed wiring board structure, the purpose of the paint layer by silk printing is to improve the visibility and to improve the process yield such as prevention of bridges. However, the yield of required parts has been improved by the combination of components, but the long-term durability and reliability have been improved by combining components. From the standpoint of reliability, no progress has been made, and with the miniaturization and high density of electronic components being required for improved portability and environmental resistance, only long-term durability and reliability have been left behind. There was a problem.

【0004】本発明は、上記のごとき従来技術の問題を
解決するためになされたものであり、簡単な構成で長期
の耐久信頼性を向上させることの出来るプリント配線板
の構造を提供することを目的とする。
The present invention has been made to solve the problems of the prior art as described above, and it is an object of the present invention to provide a structure of a printed wiring board capable of improving long-term durability and reliability with a simple structure. To aim.

【0005】[0005]

【課題を解決するための手段】上記の目的を達成するた
め、本発明においては、特許請求の範囲に記載するよう
に構成している。すなわち、請求項1に記載の発明にお
いては、絶縁体上に導電体配線を形成し、該導電体配線
の上に表面実装部品をはんだ接合する、いわゆるプリン
ト配線板の構造において、上記表面実装部品の搭載予定
部分の直下に位置する上記導電体配線のランドの一部に
ソルダレジストを重ね、かつ、上記ランドと上記ソルダ
レジストとの重なった部分の上に、さらにシルク印刷に
よる塗料層を設け、上記導電体配線のランドの一部と
記ソルダレジストと上記塗料層とを重ねた上に、上記塗
料層と接触させて上記表面実装部品を配置するように構
成したものである。上記の構造は、例えば後記図1の実
施例に相当する。また、導電体配線のランドとは、導電
体配線のうち、その上にはんだを設けて搭載部品を接続
する部分を意味する。また、シルク印刷による塗料層
は、通常は部品を実装機などでマウントする際の認識や
目視確認の目安とするための文字や図形を示す目的で設
けられるが、本発明においては、部品のはんだスタンド
オフ高さを得るために設けられている。
In order to achieve the above object, the present invention is constructed as described in the claims. That is, in the invention according to claim 1, in the structure of a so-called printed wiring board in which a conductor wiring is formed on an insulator and a surface mounting component is solder-bonded on the conductor wiring, the surface mounting component is The solder resist is overlapped on a part of the land of the conductor wiring located immediately below the mounting planned portion, and the paint layer by silk printing is further provided on the overlapping portion of the land and the solder resist, on overlaid a part of the land of the conductor lines and the upper <br/> Symbol solder resist and the coating layer, the coating
The surface mount component is arranged in contact with the material layer . The above structure corresponds to, for example, the embodiment shown in FIG. 1 described later. In addition, the land of the conductor wiring means a portion of the conductor wiring to which solder is provided to connect the mounted components. In addition, the paint layer by silk printing is usually provided for the purpose of showing characters and figures for the purpose of recognition and visual confirmation when mounting a component by a mounting machine or the like. It is provided to get the standoff height.

【0006】た、請求項に記載の発明においては、
上記のランドとソルダレジストとシルク印刷による塗料
層との重なる部分を、上記表面実装部品のランド外周に
沿ってランドを囲むように配置したものである。なお、
この構成は、例えば後記図2の実施例に相当する。
[0006] Also, in the invention described in claim 2,
The land, the solder resist, and the portion of the paint layer formed by silk printing overlapping each other are arranged so as to surround the land along the outer periphery of the land of the surface-mounted component. In addition,
This configuration corresponds to, for example, the embodiment shown in FIG. 2 described later.

【0007】[0007]

【作用】上記のように、本発明においては、シルク印刷
による塗料層とソルダレジストとを従来とは異なった構
成に配置したものである。すなわち、配線パターンのラ
ンド上にソルダレジストとシルク印刷による塗料層を重
ね合わせ、部品のはんだスタンドオフ高さを稼ぐことに
より、簡単な構造で、工程コストアップなしに、はんだ
接合部の長期の耐久信頼性を向上させたものである。な
お、詳細を後述するように、特に苛酷な環境では、スタ
ンドオフ高さが長期の耐久信頼性の確保に大きな影響を
及ぼし、本発明者の実験によれば、スタンドオフ高さが
2倍になると寿命は4倍以上になることが判明した。
As described above, in the present invention, the paint layer by silk printing and the solder resist are arranged in a structure different from the conventional one. In other words, by overlapping the solder resist and the paint layer by silk printing on the land of the wiring pattern and increasing the solder standoff height of the component, the structure is simple, and the long-term durability of the solder joint is achieved without increasing the process cost. It has improved reliability. As will be described later in detail, in a particularly harsh environment, the standoff height has a great influence on ensuring long-term durability and reliability, and according to an experiment by the present inventor, the standoff height is doubled. It became clear that the life would be more than four times longer.

【0008】[0008]

【実施例】以下、この発明を図面に基づいて説明する。
図1は、この発明の一実施例の断面図である。まず、構
成を説明すると、絶縁体である基体11上に、配線パタ
ーンのランド20が形成されている。なお、配線パター
ンのランドとは、配線パターンのうち、その上にはんだ
19を設けて搭載部品(表面実装部品)15を接続する
部分を意味する。このランド20は、従来例のそれより
も搭載部品のランドの長手方向に若干大きく形成されて
いる。どの位大きく形成するかは、その工程のもつ印刷
解像度などに依存するが0.3mm程度は必要である。
ただし、部品を載せる予定のない配線パターン12は通
常と全く同じでかまわない。なお、16は搭載部品15
の端子である。
DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to the drawings.
FIG. 1 is a sectional view of an embodiment of the present invention. First, the structure will be described. A land 20 having a wiring pattern is formed on a base 11 which is an insulator. The land of the wiring pattern means a portion of the wiring pattern on which the solder 19 is provided and the mounting component (surface mounting component) 15 is connected. The land 20 is formed slightly larger in the longitudinal direction of the land of the mounted component than that of the conventional example. How large the film is to be formed depends on the printing resolution of the process, but about 0.3 mm is necessary.
However, the wiring pattern 12 in which no parts are to be placed may be exactly the same as a normal one. In addition, 16 is a mounted component 15
Is the terminal.

【0009】上記の若干大きめに形成された配線パター
ンのランド20上の一部を覆うようにソルダレジスト1
8を形成する。この覆う大きさも工程の持つ印刷解像度
によって異なるが、やはり0.3mm程度は必要とな
る。また、一部を覆ったソルダレジスト18上にシルク
印刷による塗料層17を形成する。シルク印刷による塗
料層17はその厚みを目的として形成されるため、太さ
は特に規定する必要はないが、0.1〜0.2mm程度は
必要と思われる。そして実際の搭載部品15(チップ抵
抗器、チップコンデンサ、QFP等)が、基体11上に
ソルダレジスト18とシルク印刷による塗料層17とを
重ねた上に配置され、はんだ19によってランド20に
電気的機械的に接続される。
The solder resist 1 is formed so as to cover a part of the land 20 of the slightly larger wiring pattern.
8 is formed. The size of this cover also depends on the printing resolution of the process, but it is still necessary to have a size of about 0.3 mm. Further, the paint layer 17 is formed by silk printing on the solder resist 18 which covers a part. Since the paint layer 17 formed by silk printing is formed for the purpose of its thickness, it is not necessary to specify the thickness, but it is considered that about 0.1 to 0.2 mm is necessary. Then, the actual mounting component 15 (chip resistor, chip capacitor, QFP, etc.) is arranged on the base 11 on which the solder resist 18 and the paint layer 17 by silk printing are overlapped, and the land 19 is electrically connected to the land 20 by the solder 19. Mechanically connected.

【0010】次に作用を説明する。本実施例において
は、配線パターン20(通常、厚さ35μm)とソルダ
レジスト18(通常、厚さ20〜40μm)とシルク印
刷による塗料層17(通常、厚さ25μm前後)を重ね
合わせることにより、非常に簡単な構造で、大きなスタ
ンドオフ高さ(通常80〜100μm)を形成すること
が出来る。搭載部品のサイズやプリント配線板の線膨張
係数にもよるので決定的なことはいえないが、本発明者
の実験では、特に苛酷な環境では、このスタンドオフ高
さが数μm〜十数μm程度では信頼性の確保が困難であ
ることが判っている。また、本発明者の実験によれば、
スタンドオフ高さが2倍になると寿命は4倍以上になる
ことが判明した。
Next, the operation will be described. In this embodiment, the wiring pattern 20 (usually 35 μm in thickness), the solder resist 18 (usually 20 to 40 μm in thickness) and the paint layer 17 (usually around 25 μm in thickness) by silk printing are superposed on each other. With a very simple structure, a large standoff height (usually 80 to 100 μm) can be formed. It cannot be said to be definitive because it depends on the size of the mounted components and the linear expansion coefficient of the printed wiring board, but in experiments by the present inventor, this standoff height is several μm to several tens of μm in a particularly severe environment. It has been found that it is difficult to secure reliability to some extent. Moreover, according to the experiment of the present inventor,
It was found that when the standoff height is doubled, the life is more than four times longer.

【0011】従来、工程歩留まり・検査を目的とする改
善案(例えば、特開昭62−118478号公報に記
載)や、工程を大きく変更して追加の部材を使用してス
タンドオフ高さを稼ぐ方法(例えば、特開昭64−47
092号公報に記載)は存在したが、本実施例の構造で
は、上記の従来例よりも非常に単純な構成であり、か
つ、プリント配線板のマスク設計時に描画上の配慮(ラ
ンド20を多少大きくし、かつシルク印刷による塗料層
17の位置を設定)さえしてやればよいのであって、製
造工程の変更も必要としない。したがってコストアップ
は皆無に近い。更に上記の従来方法(特開昭64−47
092号)では、その構造上、部品の直下を通る配線パ
ターンに制限が必要になったり、中央部分をスタンドオ
フ高さを稼ぐために盛り上げるため、いわゆるマンハッ
タン現象(ツームストーン現象とも言う。はんだの表面
張力が大きいため、搭載部品の片側が浮き上がって、搭
載部品が立ち上がる現象)が頻発する恐れがあった。そ
の点、本実施例においては、本来から存在する配線パタ
ーンのランドの大きさを若干大きくしただけなので、部
品直下の配線パターンの制限に与える影響は極めて小さ
く、また部品の両端近傍を持ち上げる構造を有している
ため、マンハッタン現象を頻発するおそれもない。
Conventionally, an improvement plan for the purpose of process yield / inspection (for example, disclosed in Japanese Patent Laid-Open No. 62-118478) or a process is largely changed to use additional members to increase the standoff height. Method (for example, JP-A-64-47)
However, the structure of the present embodiment has a much simpler structure than the above-mentioned conventional example, and the drawing considerations (the land 20 may be slightly different) when designing a mask for a printed wiring board. All that has to be done is to increase the size and set the position of the paint layer 17 by silk printing, and no change in the manufacturing process is required. Therefore, there is almost no cost increase. Further, the above-mentioned conventional method (Japanese Patent Laid-Open No. 64-47)
No. 092), because of its structure, it is necessary to limit the wiring pattern that passes directly under the component, or to raise the central portion to increase the standoff height, so the so-called Manhattan phenomenon (also called tombstone phenomenon. Due to the large surface tension, one side of the mounted component floats up, and the mounted component may rise frequently). In this respect, in the present embodiment, since the size of the land of the wiring pattern which originally exists is only slightly increased, the influence on the limitation of the wiring pattern immediately below the component is extremely small, and a structure for lifting the vicinity of both ends of the component is adopted. Since it has, there is no fear that the Manhattan phenomenon frequently occurs.

【0012】次に、図2には、本発明の第2の実施例を
示す断面図である。まず、構成を説明する。絶縁体であ
る基体11上には部品を搭載しない配線パターン12が
形成されている。また、表面実装部品となるQFP31
の下部に位置する配線パターンのランド20は、通常形
成されるものよりも若干大きめに形成されている。具体
的に拡大する大きさは、QFP31のサイズ形状に大き
く依存するため一様には決定できないが、QFP31の
エポキシレジン外周よりも大きくなければ本実施例の効
果は期待できない。この実施例においては、ランドとソ
ルダレジストとシルク印刷による塗料層との重なる部分
が、表面実装部品のランド外周に沿ってランドを囲むよ
うに配置されている。なお、図1の実施例と同様に、表
面実装部品の直下にも設けられている。
Next, FIG. 2 is a sectional view showing a second embodiment of the present invention. First, the configuration will be described. A wiring pattern 12 on which no components are mounted is formed on a base 11 which is an insulator. In addition, QFP31 which is a surface mount component
The land 20 of the wiring pattern located in the lower part of is formed slightly larger than that normally formed. The size to be specifically expanded greatly depends on the size and shape of the QFP 31, and therefore cannot be uniformly determined, but the effect of the present embodiment cannot be expected unless it is larger than the outer circumference of the epoxy resin of the QFP 31. In this embodiment, an overlapping portion of the land, the solder resist, and the paint layer formed by silk printing is arranged so as to surround the land along the periphery of the land of the surface mount component. Note that, similarly to the embodiment of FIG. 1, it is also provided directly below the surface mount component.

【0013】上記の大きめに形成されたランド20上に
は、ソルダレジスト18が形成される。ソルダレジスト
18は少なくとも0.3mm程度はランド20と重なっ
ている必要がある。ソルダレジスト18とランド20の
重なり合っている上にはシルク印刷による塗料層17が
形成されている。シルク印刷による塗料層17の太さは
QFP31のピンピッチとの関係もあり一概にはいえな
いが、0.1mm程度は必要である。そしてランド20
上には、はんだ19によってQFP31の端子(リード
フレーム)32が電気的・機械的に接合されている。
A solder resist 18 is formed on the land 20 having a larger size. The solder resist 18 needs to overlap the land 20 at least about 0.3 mm. A paint layer 17 formed by silk printing is formed on the solder resist 18 and the land 20 which are overlapped with each other. The thickness of the paint layer 17 formed by silk printing cannot be unequivocally related to the pin pitch of the QFP 31, but about 0.1 mm is required. And land 20
A terminal (lead frame) 32 of the QFP 31 is electrically and mechanically joined to the top by the solder 19.

【0014】次に作用を説明する。作用は基本的には図
1で示した作用と同様であり、はんだ19のスタンドオ
フ高さを稼ぐことではんだ接合の寿命を改善することで
ある。なお、実装する部品がQFPの時には、場合によ
っては、はんだブリッジを防ぐ目的でリードフレーム3
2の先端方向に余分なはんだを流す手法も有効であるこ
とがある。そのような場合には、図2に示したリードフ
レーム32の先端方向に形成されているソルダレジスト
やシルク印刷による塗料層は必須ではない。
Next, the operation will be described. The operation is basically the same as the operation shown in FIG. 1, and the standoff height of the solder 19 is increased to improve the life of the solder joint. When the component to be mounted is QFP, the lead frame 3 may be used to prevent solder bridging in some cases.
A method of flowing excess solder in the tip direction of 2 may also be effective. In such a case, the solder resist formed on the tip end direction of the lead frame 32 shown in FIG. 2 and the paint layer by silk printing are not essential.

【0015】[0015]

【発明の効果】以上説明したごとく、本発明において
は、配線パターンのランド上にソルダレジストとシルク
印刷による塗料層を重ね合わせた構造とすることによ
り、簡単な構成で部品のはんだスタンドオフ高さを大き
くし、工程コストアップなしに、はんだ接合部の長期の
耐久信頼性を向上させることができる、という効果が得
られる。
As described above, according to the present invention, the solder standoff height of a component is simple with a structure in which a solder resist and a paint layer by silk printing are superposed on the land of the wiring pattern. And the long-term durability reliability of the solder joint can be improved without increasing the process cost.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の第1の実施例を示す断面図。FIG. 1 is a sectional view showing a first embodiment of the present invention.

【図2】本発明の第2の実施例を示す断面図。FIG. 2 is a sectional view showing a second embodiment of the present invention.

【図3】従来の一例の断面図。FIG. 3 is a cross-sectional view of a conventional example.

【符号の説明】[Explanation of symbols]

1…基体部分 13…シルク印刷に
よる塗料層 2…配線パターン 15…表面実装部品 3…シルク印刷による塗料層 16…表面実装部品
15の端子 4…はんだ 17…シルク印刷に
よる塗料層 5…表面実装部品 18…ソルダレジス
ト 6…表面実装部品5の端子 19…はんだ 7…ソルダレジスト 20…配線パターン
のランド 11…基体 31…QFP 12…配線パターン 32…QFP31
の端子
DESCRIPTION OF SYMBOLS 1 ... Base part 13 ... Paint layer 2 by silk printing ... Wiring pattern 15 ... Surface mount component 3 ... Paint layer by silk printing 16 ... Terminal 4 of surface mount component 15 ... Solder 17 ... Paint layer 5 by silk print ... Surface mount component 18 ... Solder resist 6 ... Surface mount component 5 terminals 19 ... Solder 7 ... Solder resist 20 ... Wiring pattern land 11 ... Base material 31 ... QFP 12 ... Wiring pattern 32 ... QFP31
Terminal

フロントページの続き (58)調査した分野(Int.Cl.7,DB名) H05K 3/28 H05K 1/18 H05K 3/34 Continuation of front page (58) Fields surveyed (Int.Cl. 7 , DB name) H05K 3/28 H05K 1/18 H05K 3/34

Claims (2)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】絶縁体上に導電体配線を形成し、該導電体
配線の上に表面実装部品をはんだ接合する、いわゆるプ
リント配線板の構造において、 上記表面実装部品の搭載予定部分の直下に位置する上記
導電体配線のランドの一部にソルダレジストを重ね、か
つ、上記ランドと上記ソルダレジストとの重なった部分
の上に、さらにシルク印刷による塗料層を設け、上記導電体配線のランドの一部と 上記ソルダレジストと
上記塗料層とを重ねた上に、上記塗料層と接触させて
記表面実装部品を配置したことを特徴とするプリント配
線板の構造。
1. In a structure of a so-called printed wiring board in which a conductor wiring is formed on an insulator and a surface mounting component is solder-bonded on the conductor wiring, directly below a portion where the surface mounting component is to be mounted. A solder resist is overlaid on a part of the land of the conductor wiring, and a paint layer by silk printing is further provided on a portion where the land and the solder resist are overlapped with each other. A structure of a printed wiring board, characterized in that a part, the solder resist, and the paint layer are superposed on each other, and the surface mount component is placed in contact with the paint layer .
【請求項2】上記のランドとソルダレジストとシルク印
刷による塗料層との重なる部分を、上記表面実装部品の
ランド外周に沿ってランドを囲むように配置したことを
特徴とする請求項1に記載のプリント配線板の構造。
2. The land, the overlapping portion of the solder resist, and the paint layer by silk printing are arranged so as to surround the land along the periphery of the land of the surface mount component. Printed wiring board structure.
JP31959594A 1994-12-22 1994-12-22 Structure of printed wiring board Expired - Fee Related JP3503232B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP31959594A JP3503232B2 (en) 1994-12-22 1994-12-22 Structure of printed wiring board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP31959594A JP3503232B2 (en) 1994-12-22 1994-12-22 Structure of printed wiring board

Publications (2)

Publication Number Publication Date
JPH08181419A JPH08181419A (en) 1996-07-12
JP3503232B2 true JP3503232B2 (en) 2004-03-02

Family

ID=18112028

Family Applications (1)

Application Number Title Priority Date Filing Date
JP31959594A Expired - Fee Related JP3503232B2 (en) 1994-12-22 1994-12-22 Structure of printed wiring board

Country Status (1)

Country Link
JP (1) JP3503232B2 (en)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2012124397A (en) * 2010-12-10 2012-06-28 Cmk Corp Multilayer printed wiring board with built-in component
JP6476871B2 (en) * 2014-05-22 2019-03-06 株式会社村田製作所 Circuit board, power storage device, battery pack and electronic device
WO2017203859A1 (en) * 2016-05-25 2017-11-30 日立オートモティブシステムズ株式会社 Electronic circuit device and method
JP2018046225A (en) * 2016-09-16 2018-03-22 株式会社豊田自動織機 Board device
WO2019146252A1 (en) * 2018-01-23 2019-08-01 株式会社村田製作所 Substrate bonding structure and substrate bonding method

Also Published As

Publication number Publication date
JPH08181419A (en) 1996-07-12

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