JPH0564552B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a high frequency pulse width modulation inverter modulation system that improves reliability.

When the output voltage waveform of an inverter is made to approximate a sine wave, it is common to use the following high frequency pulse width modulation method.

FIG. 1 shows an example of a three-phase inverter modulation system. The figure shows 3 where the number of pulses during the output half cycle is 3.
The case of pulse modulation is shown. In Figure 1, 1 is a triangular carrier wave that determines the number of pulses 3 and the pulse interval, 2 is a modulated wave that determines the magnitude of the fundamental wave of the output voltage, and 3 is a comparison of carrier wave 1 and modulated wave 2. The obtained composite gate signals 4 to 6 are U, V, and W phase gate signals obtained by dividing the composite gate signal 3 by 120° in the order of the phases of the U, V, and W phases. The phase gate signals 4 to 6 are distributed as gate signals for controlled rectifying elements such as thyristors in the U, V, and W phases of the inverter circuit shown in FIG.

In other words, the U-phase gate signal 4 is U-phase due to its high level.
Indicates the conduction state of the upper arm thyristor 14,
The low level indicates the conduction state of the U-phase lower arm thyristor 15. In addition, V phase, W phase gate signals 5, 6
Similarly, V and W phase upper and lower arm thyristors 16,1
7, 18, and 19 are electrically connected. Therefore, three-phase AC outputs 7 to 9 consisting of the pulse train shown in FIG. 1 are obtained between the output lines of the U, V, and W phases of the three-phase inverter in FIG. 2. In the above, by controlling the height of either modulated wave 2 or carrier wave 1, the output pulse width can be adjusted and the output voltage can be controlled.

In addition, in FIG. 2, 10 is a DC power supply, 11
12 is a filter reactor, and 13 is a filter capacitor.

FIG. 3 is an example of a block diagram of the modulation method shown in FIG. 1. In the figure, 20 is a modulated wave generation circuit, 21 is a carrier wave generation circuit, 22 is a comparator, 2
3 is a U-phase distribution circuit, 24 is a V-phase distribution circuit, 25 is a W-phase distribution circuit, and 26 is a phase angle generation circuit. The output of the comparator 22 is the composite gate signal 3 shown in FIG. 1, and the output of the U, V, W phase distribution circuits 23 to 25 is
UV and W phase gate signals 4 to 6.

Next, the minimum on-off period tmin shown in FIG. 1 will be explained. Controlled rectifying elements such as thyristors are
Switching frequency is limited. In addition, a commutation period, turn-off time, etc. are required to turn off the thyristor, and the gate amplification circuit also has a minimum value for the on/off repetition time, so the value of the minimum on-off period tmin must be set to U, V, W. Each phase gate signal 4~
The carrier wave 1 is modified to limit the minimum pulse width of 6.

However, although this method can ensure the minimum pulse width at the peak point of carrier wave 1, when modulated wave 2 changes rapidly, the minimum on-off period
The value of tmin may not be secured. FIG. 4 shows an example where the minimum on-off period tmin cannot be secured. If the modulated wave 2 suddenly decreases at point A, the V-phase gate signal 5 will no longer be able to secure the minimum on-off period tmin at points B and C. As described above, the conventional method has the disadvantage that the controlled rectifying element and the like are likely to cause commutation failure due to sudden changes in the modulated wave.

This invention has been made in view of the above, and by limiting the number of inversions of the comparison output with the modulated wave to one in each period of increase and decrease of the carrier wave, the minimum on-off period tmin Provides an inverter modulation method that ensures

The figures will be explained below. 4 in Figure 5
The same symbols as in the figure indicate the same signals. At point D in FIG. 5, even if the composite gate signal 3 is inverted, in the section where the carrier wave 1 continues to decrease, if the re-inversion of the composite gate signal 3 is restricted, the width of the output waveform 7 between UV and It is designed to ensure the minimum on-off period tmin without creating narrow slits.

An embodiment of a circuit for limiting re-inversion of the composite gate signal 3 is shown in FIG. In FIG. 6, the same signals as in FIG. 3 indicate the same functions. In Figure 6,
Reference numeral 27 denotes a section discrimination signal, which is a signal indicating an increasing section or a decreasing section of the carrier wave 1. A latch circuit 28 has the function of inputting the output 3 of the comparator 22 to D and outputting or fixing (latching) the signal of the input D to the output Q depending on the signal of the enable input E.
29 is an exclusive logic circuit, and the output Q of the latch circuit 28
The synthesized gate signal 3, which is the output signal of the synthesized gate signal 3, and the section discrimination signal 27 are compared, and if the synthesized gate signal 3 and the section discrimination signal 27 match, a signal for latching the output Q of the latch circuit 28 is generated. Note that the latch circuit 28 and exclusive logic circuit 29 constitute an inversion limiting circuit 30.

In the above embodiment, a method is used in which the signals indicating the increasing and decreasing sections of the carrier wave are compared with the composite gate signal, and the composite gate signal is fixed, thereby limiting the number of times the comparison output between the modulated wave and the carrier wave is inverted. However, for example, instead of a section discrimination signal, there is a method of separating increasing and decreasing sections using a signal obtained by differentiating the carrier wave, a method of latching the modulated wave instead of a method of latching a composite gate signal, and a method of latching the modulated wave from the point of inversion. The same effect as in the above embodiment can be expected by a method of fixing the value to the maximum value (when increasing) or the minimum value (when decreasing).

According to the present invention, the controlled rectification is performed by limiting the number of inversions of the comparison output between the carrier wave and the modulated wave to one in each of the increasing and decreasing sections of the carrier wave. Malfunction of the element is prevented. This improves reliability.

[Brief explanation of the drawing]

Figures 1 to 4 are diagrams explaining the conventional modulation method, where Figure 1 is a waveform diagram, Figure 2 is a main circuit configuration diagram, and Figure 3 is a diagram explaining the conventional modulation method.
4 is a waveform diagram explaining inversion, FIG. 5 is a waveform diagram of a modulation method according to the present invention, and FIG. 6 is a block diagram of a modulation circuit according to an embodiment of the present invention. . In the figure, 1 is a carrier wave, 2 is a modulated wave, 3 is a composite gate signal, 20 is a modulated wave generation circuit, 21 is a carrier wave generation circuit, 22 is a comparator, 26a is a phase angle generation circuit, 27 is a section discrimination signal, 30 is an inversion control circuit. Note that the same reference numerals in each figure indicate the same or equivalent parts.

Claims (1)

[Claims] 1. A modulated wave generation circuit that generates a modulated wave that determines the magnitude of the output voltage of the inverter, a carrier wave generation circuit that generates a carrier wave that determines the ratio and shape of the modulated pulse output from the inverter, and a comparator that outputs a composite gate signal when the carrier wave matches the carrier wave; a phase angle generation circuit that determines an increasing section and a decreasing section of the carrier wave and generates a section discrimination signal; an inverter modulation device comprising: an inversion limiting circuit that limits inversion of the composite gate signal to one time for each increasing section or decreasing section of the carrier wave when the discrimination signal matches the discrimination signal;