JPH0563969B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a phase synchronization control device used in communication equipment, audio equipment, and the like.

Conventional configurations and their problems Conventional phase synchronization control devices have various configurations, but are basically comprised of phase comparison means, phase difference signal integration means, and local oscillation means. The phase difference between the input signal and the signal from the local oscillation means is detected by the phase comparison means, and the phase difference signal is integrated by the phase difference signal integration means and converted to a DC level, and the local oscillation It is used as a direct current input. Further, the local oscillation means is configured to output a signal with a frequency proportional to the DC input, and the entire system is configured to be synchronized with the frequency of the input signal. However, in such a device, when the input signal to be cycled causes a sudden frequency shift, when the phase difference signal integrating means integrates the output of the phase comparing means, an overload state occurs due to the integration time constant. The frequency transition of the local oscillation means exhibited a time delay, and the system as a whole was also in an overload state. Note that in order to avoid such a state, it is possible to reduce the integral time constant, but this has the disadvantage that the stability of the entire system in a steady state decreases.

Therefore, if the above-mentioned phase synchronization device is used in communication equipment or information equipment that detects a part of an input signal as a synchronization signal, a practical problem arises due to its poor followability.

OBJECTS OF THE INVENTION It is an object of the present invention to provide a phase synchronization control device that solves the above-mentioned conventional problems, can follow sudden frequency transitions of an input signal, and has improved transient characteristics.

Structure of the Invention The present invention inputs a frequency change of an input signal into a signal sequence storage means, detects a frequency signal, and compares the frequency with a center frequency previously stored in an average frequency storage means using a comparing means. The numerical digital signal output from this comparison means is input to the DC bias storage means, and the DC bias storage means
Since a DC bias value that has a proportional linear relationship corresponding to this numerical digital signal is stored as a digital numerical value in advance, an output corresponding to the numerical digital signal input is performed and this is sent to the D/A.
This is configured so that the DC bias value is converted into a DC bias value by a converter, and DC summation is performed by the output of a simple phase synchronization system phase difference signal integration means and DC bias addition means, and the result is input to the local oscillation means. .

Description of Examples Examples of the present invention will be described below. 1st
The figure is a block diagram of a phase synchronization device in one embodiment of the present invention.

The input signal sequence frequency change detection section A includes a signal sequence storage means 1 (for example, consisting of a CCD, BBD, or digital register) that stores the input signal sequence for a certain length of time T in an analog or digital state, and an input signal of the signal sequence storage means 1. Comparing means 2 detects the frequency (input signal frequency within time T) and detects the difference between the frequency and the center frequency previously stored in the average frequency storage means 3; (quantity) to a DC bias value (digital quantity). It is composed of a DC bias storage means 4 (for example, composed of a ROM) and a D/A converter 5.

Note that 10 is an input terminal for a signal applied to this frequency change detection section A.

Further, the phase synchronization section B includes a local oscillation means 9, a phase comparison means 6 for detecting the phase difference of the input signal, and a phase difference for integrating the output of the phase comparison means 1 and outputting an average DC value (analog amount). signal integrating means 7;
The DC value of the difference from the center frequency of the input signal frequency detected by the frequency change detection section A and the average DC value that is the output of the phase difference signal integration means 7 are added by analog, and the DC value is input to the local oscillation means 9. It is composed of bias addition means 8. Note that this phase synchronization section B has a structure similar to that used in a conventionally known phase synchronization device.

Further, in FIG. 2, A indicates a change in the frequency of the input signal. FIG. 2B shows the time change in the DC output of the phase difference signal integrating means (7 in FIG. 1) of the phase synchronization section B when the above-mentioned signal frequency change occurs. FIG. 2C shows the change over time of the DC value output value of the input signal frequency detection section A. Note that in the figure, f _O is the center frequency stored in the average frequency storage means 3. FIG. 2D shows the frequency change of the local oscillation means 9 in response to the input signal frequency change.

FIG. 3 shows the correspondence relationship between the output of the comparison means 2 and the output of the DC bias storage means 4 of the frequency change detection section according to this embodiment.
and the center frequency f _O of the average frequency storage means 3
The horizontal axis is the difference between the two, and the vertical axis is the output of the DC bias storage means 4.

Next, the operation of the above embodiment will be explained.
The signal input from the input terminal 10 is sampled and sent to the phase synchronization unit B via the signal sequence storage means 1.
is input. In addition, the input signal sampled at each sampling period is stored in the signal sequence storage means 1 for a fixed time length T, and the frequency during this period T is calculated, and the center frequency f _O of the average frequency storage means 3 and the comparison means 2 compared by. The output of the comparison means 2 is converted into a DC value by the DC bias storage means 4 having the characteristics shown in FIG.
The converter 5 converts it into direct current. Note that this DC value is updated every sampling period of the input signal. In other words, as shown in Figure 2 A, the frequency of the input signal suddenly changes (approximately twice the frequency change).
In this case, the output change of the phase difference signal integrating means 7 of the phase synchronization section B will be overloaded as shown in Fig. 2B, and the transition time T _O determined by the time constant of the integrator will occur.
It comes to have. However, the DC output of the input signal frequency detection section A is output in proportion to the difference from the center frequency f _O in accordance with the characteristics shown in Fig. 3 for each sampling period, so the DC output is shown in Fig. 2 C. As a result, the transition time becomes T _N (T _N ≪T _O ).

The output of the frequency change detection section A is added to the output of the phase difference signal integration means 7 by the DC bias addition means 8, and is input to the local oscillation means 9. Therefore, the output of the local oscillation means 9 is shown in FIG. According to what is shown, the transient time is T _N and the system becomes stable.

In this embodiment, the free-running frequency when the output value of the DC bias value addition means 8 is O is previously stored in the average frequency storage section 3, and is stored in the signal sequence storage means 1 and the average frequency storage section 3 in advance. Means 3
By using the comparison value as input to the DC bias storage means 4, a phase synchronization system at any center frequency can be constructed. Here, in order to preserve linear characteristics in the frequency pull-in range, it is desirable that the DC bias value be selected in stages.

Effects of the Invention As is clear from the above embodiments, according to the present invention, the frequency change of the input signal is calculated in advance for a certain time length T for each sampling period, and is calculated as the difference from the center frequency f _O stored in advance. The comparison means inputs this frequency difference as a numerical digital signal to the DC bias storage means, and the DC bias storage means stores in advance a DC bias value having a proportional linear relationship in response to this numerical digital signal. Since it is stored in digital numbers,
Outputs corresponding to numerical digital signal input,
This is converted to a DC bias value by a D/A converter and added to the integrated output of the phase difference signal of a simple phase synchronization system, which shortens the transition time for sudden frequency fluctuations in the input signal. This improves the follow-up performance and allows the time constant of the integrator of the phase difference signal to be relatively large, thereby improving the stability of the system.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a phase synchronization device according to an embodiment of the present invention, FIG. 2A to D are signal waveform diagrams of the main parts thereof, and FIG. 3 is a characteristic diagram of an input signal frequency detection section. 1... Signal sequence storage means, 2... Comparison means, 3
... average frequency storage means, 4 ... DC bias storage means, 5 ... D/A converter, 6 ... phase comparison means, 7 ... phase difference signal integration means, 8 ... DC bias addition means, 9 ... ...Local oscillation means.

Claims (1)

[Claims] 1. Signal sequence storage means for storing input signal sequences;
A comparison means for comparing the frequency of the input signal series with a preset frequency, a numerical digital signal output from this comparison means is input, and a direct current having a proportional linear relationship corresponding to this numerical digital signal is input. DC bias storage means for storing bias values in digital values and outputting corresponding to inputs; a D/A converter for converting the digital values in the DC bias storage means into DC values; and phase error signal integration in a phase synchronization section. A DC bias addition means for adding an output of the D/A converter to a phase error integral value of the means, and configured such that the output of the DC bias addition means is input to the local oscillation means of the phase synchronization section. Phase synchronization controller.