JPH04200115A - Phase synchronization circuit - Google Patents

Abstract

PURPOSE:To attain oscillation control of a VCO in response to the synchronization state by providing a control means varying a control voltage outputted from a loop filter based on the result of discrimination of a discrimination means and revising a digital data fed to a D/A converter and adding/subtracting the data. CONSTITUTION:The circuit is provided with a double window comparator circuit 18 and with a discrimination result input port 19. Then the digital data fed to a level shift (LS) D/A converter 8 is added and subtracted depending on the output state of the said circuit 18 to revise the digital data from to a gain control (GC) D/A converter 7. Moreover, a nonvolatile memory 11 stores digital data in two kinds of converters 7 and read selectively in response to the output state of the said circuit 18 by a control circuit 12 and the result is fed to the converters 7. Thus, the state is immediately restored even when locking is released and locking is always implemented regardless of the quantity of jitter.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a phase-locked circuit (hereinafter referred to as 'PLL (P
hase I,ocked Loop) circuit"
It is related to.

Conventionally, such a PLL circuit is configured as shown in Fig. 4, where (1) is an input terminal to which an input signal of the reference frequency fItEF is applied, and (2) is an input terminal to which the input signal is supplied. The frequency f of the oscillation output signal is based on the control voltage. , C is a controlled voltage controlled oscillator (hereinafter referred to as "rvc○"), (3) is the oscillation output signal frequency f of v c O (2). Frequency divider that divides sc, (4) is V divided by frequency divider (3)
A phase comparator that compares the phases of the oscillation output signal of C O (2) and the input signal and outputs a difference signal voltage according to the phase difference (frequency shift of both signals), and the phase comparator (4) is a reference signal. If there is no phase difference between the falling edge of the input signal of the frequency f IIEF and the falling edge of the divided frequency f PLL oscillation output signal, and there is no phase difference between them, they enter a high impedance state and output a difference signal voltage. (i.e., at a constant voltage), the input signal has a phase difference (see Figure 5(a)).
If the phase is advanced with respect to the frequency-divided oscillation output signal (see Fig. 5(b)), the difference signal voltage of high level (see Fig. 5(c))
) is superimposed on a constant voltage and output, and conversely, in the case of a lagging phase, a low level difference signal voltage is superimposed on a constant voltage and output. (5) is V
The loop filter (5) is a low-pass filter (hereinafter referred to as rLP) that smooths the difference signal voltage of the phase comparator (4).
F. ) (6) and the output voltage of L P F (6) applied to its reference voltage terminal ■ Gain control that outputs the control voltage according to the supplied digital data and sets the lock range. A digital/analog converter (hereinafter referred to as "RCC-D/A converter") (7) converts the reference voltage applied to its reference voltage terminal into a control voltage corresponding to the supplied digital data and outputs it to control the oscillation center frequency. A level shift digital/analog converter (hereinafter referred to as rLS-D/A converter) (8) that performs settings, and a dual/A converter (7).
) Adding the control voltage output from (8), V C
0 (2) and an adder (9).

Here, both/A converters (7) and (8) are of a multiplication type that outputs the product of the voltage applied to its reference voltage terminal and a digital value. (10) is a frequency division ratio output port that supplies digital data for setting the frequency division ratio to the frequency divider (3), and (11) is a frequency division ratio output port (10) and GC, LS, D/ A non-volatile memory in which the digital data supplied to the converter (7) (8) is stored;
(l2) is a non-volatile memory (11) through the data hash
The digital data stored in the GC and LS-D/A converters (7) and (8) are read out and the digital data for setting the frequency division ratio is supplied to the frequency division ratio output port (10). , a control circuit (in this case, a microcomputer) that supplies digital data for setting the oscillation center frequency. Here, divide ratio output port (10)
The digital data supplied to the circuit is output from the frequency division ratio output port (10) so as to match the frequency divider (3).For example, the output from the control circuit (12) is divided by 8 bits. If the circuit (3) is 18 bits, three frequency division ratio output ports (10) are used to output 18 bits.

Therefore, in a PLL circuit having such a configuration, when the power is turned on, the control circuit (12) first loads the nonvolatile memory (
11), and supplies the digital data to the frequency division ratio output port (10);
Set the frequency division ratio of the frequency divider (3) (in this case, divide by N). Next, the digital data of the oscillation center frequency is read from the nonvolatile memory (ll) and the LS-D/A converter (
8) and the control voltage output from the LS/D/A converter (8), that is, the oscillation center frequency of V CO (2) is set.

Similarly, the lock range digital data is read from the nonvolatile memory (11) and the GC-D/A converter (7) is read out.
) and the gain of the control voltage output from the GC-D/A converter (7), that is, the lock range is set. In this state, the reference input signal applied to the input terminal (1) and the frequency divided by 1/N by the frequency divider (3) are used.
The phase is compared with the oscillation output signal of CO (2), and the difference signal voltage corresponding to the phase difference is converted to the GC-D/A converter (7).
After converting it to a control voltage with a gain set by digital data, the oscillation output signal is added to the control voltage from the LC-D/A converter (8) and supplied to the V CO (2), where feedback is applied. This operation is repeated until the phase difference disappears by controlling the input signal, and an N-multiplied oscillation output signal phase-synchronized with the input signal is obtained as a clock signal.

However, in PLL circuits with such conventional configurations, the digital data supplied from the control circuit to the LS and GC-D/A converters is constant, and the output from the LS-D/A converters is constant. Since the control voltage output from the GC/D/A converter and the conversion gain to the control voltage output from the GC/D/A converter are always constant, that is, the lock range and center frequency are constant, so there is no problem when the lock goes out. However, there was a drawback that it could not cope with cases where there was a lot of jitter.

The present invention has been made in view of the above points, and an object of the present invention is to provide a PLL circuit that can immediately recover from being unlocked and can be turned on and off even when there is a lot of jitter.

In order to achieve the above-mentioned object, the present invention compares the phases of the reference signal and the oscillation output signal from the VCO using a phase comparator, and then outputs signals from the phase comparator that respond to the phase difference. The difference signal voltage outputted from the loop filter is used as a control voltage by VC
In the PLL circuit, the oscillation output signal is supplied to O, and its oscillation output signal is phase-synchronized with the reference signal. Specifically, the loop filter includes a low-pass filter that smoothes the difference signal voltage of the phase comparator, and digital data supplied with the output voltage of the low-pass filter. A D/A converter outputs a control voltage according to the supplied digital data and sets the lock range, and a D/A converter outputs the reference voltage as a control voltage according to the supplied digital data and sets the oscillation center frequency. , by adding the control voltages from both/A converters to VC
The digital data supplied to both/A converters is changed, added and subtracted by the control means based on the determination result of the determination means.

Further, the control means includes a non-volatile memory capable of writing and reading digital data updated by addition and subtraction, and the discrimination means includes an output voltage of a low-pass filter for smoothing the difference signal voltage of the phase comparator and each A double window comparator circuit is used which compares the voltage with a reference voltage and sets an output state based on the comparison result.

In a PLL circuit with such a configuration, the synchronization state can be determined based on the output state of the double-wind comparator circuit, and the D/A converter sets the lock range and oscillation center frequency of the loop filter according to the result of the determination. By changing and adding/subtracting the supplied digital data to vary the control voltage, it is possible to control the oscillation of the VCO in response to the synchronous state.

Disaster” L base An embodiment of the present invention will be described below with reference to the drawings.

It should be noted that the same parts as those in the prior art will be given the same reference numerals and the explanation thereof will be omitted.

In this embodiment, a discriminating means for discriminating the synchronization state and a control means for controlling the control voltage output from the loop filter based on the discriminating result are provided. Specifically, as shown in FIG. The output voltage and resistance of the LPF (6) (
13) to (17), each reference voltage V, to V4 (V), which is set by dividing the power supply voltage VCC.

> V+ > V2 > V3 > V4) to determine the synchronization state by providing a double window comparator circuit (18), and the control circuit (12) reads the output state of this double window comparator circuit (18). A determination result input port (19) is provided for this purpose.

And the double window comparator circuit (18)
The digital data supplied to the LS-D/A converter (8) is added or subtracted depending on the output state of the GC-D/A converter (8), and
The digital data supplied to the A converter (7) is changed, and the updated digital data of the LS-D/A converter (8) is stored in a non-volatile memo +) (
11) as 1,5DATA-0, and the control circuit (12) is programmed to update the old LSDATA.0 stored in the memory (11). Furthermore, there are two types of GC-D in the nonvolatile memory (11).
The digital data of the /A converter (7), that is, C, CDATA-L for obtaining a wide lock range, and CCDATA-S for obtaining a narrow lock range, are stored, and the control circuit (12) controls the double-wind comparator circuit. (18) Selective readout GC according to the output state
- The signal is supplied to the D/A converter (7).

Here, the double window comparator circuit (1st) consists of first to fourth comparators (20) to (23),
1st. The inverting terminals of the second comparators (20) and (21) are connected to the first and second comparators, respectively. The second reference voltages V, , V2 are the third . The non-inverting terminals of the fourth comparators (22) and (23) each have a 3rd and a 4th reference voltage V3. Va are input respectively, and the first . The non-inverting terminals of the second comparators (20) and (21) and the third. The output voltage of the LPF (6) is input to the inverting terminals of the fourth comparators (22) and (23), respectively, and the second. Third reference voltage V2. V3 is set to the upper and lower limit voltages of the narrow long range. Fourth reference voltage ν1. v4 is set to the upper and lower limit voltages of the wide aperture range that allows a certain amount of jitter. Therefore, the input/output characteristics of the double window comparator circuit (18) are as shown in FIG.
Within the first window), it is assumed that the lock is almost completely locked, and the first to fourth comparators (20) to (
23) outputs L level (0), and V4<VLF
In the range of F≦v3 and V2<VLPF≦V (within the second window), there are many sick cases and the lock is in an unstable state. Third comparator (21) (22)
Output H level 1) from either of , V, < VLPF
If it falls within the range of ≦V ct or 0≦VLPF <Va, it is assumed that the lock is out or even if it is not out of lock, there is a considerable amount of jitter. 2nd or 3rd or 4th comparator (20) (21) , (22) (23)
The H level will be output from either one. and,
A control circuit (12) that reads the output state of this double window comparator circuit (18) from a determination result input port (19) controls the first to fourth comparators (2o) to (2).
3) When all the outputs are low, a small value of digital data (G'CDATA) is used to narrow the lock range.
-S) is read from the non-volatile memory (11) and QC
- Larger digital data (GCDATA -L) to be supplied to the D/A converter (7) and to provide a wide lock range when either output of the second or third comparator (21) (22) is high. is supplied to the GC/D/A converter (7). Furthermore, the first. Second
When the outputs of the comparators (20) and (21) are high, the digital data supplied to the LS-D/A converter (8) is subtracted by 1 in order to reduce the control voltage and shift the oscillation center frequency to the lower side. Third. Fourth comparator (2
2) When the output of (23) is high, the LS-
1 for the digital data supplied to the D/A converter (8)
(See the table below).

Next, the control operation of the PLL circuit by such a control circuit (12) will be explained with reference to the flowchart of FIG.

First, when the power is turned on, the process proceeds to step (Ill) where the GC-D/A converter (7), L S-D/A converter (8), and frequency dividing capo) are stored from the non-volatile memory (11). (10) (in this case, either digital data of the GC-D/A converter (7) is fine), and in the next step (#2) read each digital data of the LS-D/A converter (8). ) is not a variable, so it is called LSDA.
Create a variable called TA and assign it here before outputting it. After proceeding to step (113) and outputting each read digital data as processing 2 to the GC-D/A converter (7), LS-D/A converter (8), and frequency divider (10), Proceeding to the next step (#4), the output state of the double window comparator circuit (18) is read, and the frequency division ratio set by each digital data is determined.

In order to determine the lock range and synchronization state of the PLL circuit at the oscillation center frequency, first. Fourth comparator (20
) Determine whether the re-output in (23) is low. Here, if YES (low), it is assumed that it is locked and proceed to the next step (#5), and if NO (not low), the lock is off or even if it is not off, there is a lot of sintering. Step as the state is (#
6), and in step (#6), the first comparator (2
0) is low and the fourth comparator (23) is high. If NO, step (117) is performed and the output voltage V LPF is higher than the first reference voltage v1, and the LS-D/A converter (
8) Subtract 1 from the digital data LSDATA,
If YES, proceed to step (#8) and set the output voltage V.
Assuming that LFF is lower than the fourth reference voltage v4, LS・D
/A converter (8) digital data LSDA
After adding 1 to TA, proceed to step (#9). and,
LSDATA added and subtracted in step (#9) is L S
- After outputting to D/A Conharc (8), step again (
#4), and from then on #1. 4th comparator (20)
Until the re-output of (23) goes low, i.e. step (
The process is repeated until the determination result in #4) becomes YES. If the answer is YES, the current LSDATA and the initial digital data LSD are stored in step (#5).
Determine whether ATA・○ is the same or not, and return YE.
If S, proceed directly to the next step (#10),
If No, in step (#11) the LSDATA
is written into the non-volatile memory (11) as new initial digital data: I, 5DATA.0 to update it, and proceed to the next step (#10). And step (#10)
And then there's the second one. It is determined whether the re-output of the third comparator (21) (22) is low or not, and if No, there are many sick signals due to instability of the reference input signal frequency f REF. Assuming that the lock is in an unstable state, proceed to step (#12), and proceed to step (111).
2) GCDATA -L from non-volatile memory (11)
is read out and supplied to the GC-D/A converter (7). If YES, it is assumed that the state is completely locked with little sintering, and the process proceeds to step (113). In step (#13), CCDATA.S is read from the non-volatile memory (11) and the GC-D/A converter ( 7). Therefore, when the reference frequency is unstable and there is a lot of jitter, the lock range is widened to stabilize the lock, and the reference frequency is stable and there is no zinc.
When the amount of power is low, the lock range is narrowed to avoid receiving external shadows, and control is performed to maintain a complete lock state. Incidentally, the output state of the double window comparator circuit (18) is read periodically at certain regular intervals, and the control operations after step (#4) are performed at that time. The LSDATA ○ of the non-volatile memory (11), which is updated to the digital data of the LSD/D/A converter (8) which is always locked, ensures that the PLL circuit will be locked in a short time when the power is turned on next time. It will be used as the initial digital data for the future.

In this embodiment, the case where there is a single reference frequency has been described above, but even in the case of multi-scanning where there are a plurality of reference frequencies, the LS for each reference frequency is used.

This can be achieved by storing the digital data of the DS-D/A converter in a non-volatile memory.

Effects of the Invention As described above, according to the PLL circuit of the present invention, the synchronization state can be determined based on the output state of the double window comparator, and the lock range and oscillation center frequency of the loop filter can be set according to the result of the determination. The control voltage is varied by changing and adding/subtracting the digital data supplied to the /A converter, and the VC○ oscillation control is performed according to the synchronization state, so even if the lock is lost due to aging, etc., it can be restored immediately. In addition, it is possible to always lock the lock regardless of the degree of sickness. Further, since the data updated by addition and subtraction is written into the nonvolatile memory and used as initial digital data when the power is turned on next time, locking can be performed in a short time after the power is turned on.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing an example of a circuit configuration for realizing the present invention,
FIG. 2 is an input/output characteristic diagram of the double window comparator, FIG. 3 is a flowchart for explaining the control operation of the control circuit, and FIG. 4 is a diagram showing an example of a conventional circuit configuration.
FIG. 5 is a timing chart of the phase comparator. (2) -V CO, (4) - phase comparator. (5)-Loop filter, (6)--L P F
. (7) -G CD /A converter. (8) -LS-D/A converter. (9) - Adder; (11) - Non-volatile memory. (12)-m-control circuit. (1B)---Double window comparator circuit.

Claims (6)

[Claims] (1) After comparing the phases of the reference signal and the oscillation output signal from the voltage controlled oscillator using a phase comparator, the difference signal voltage output from the phase comparator according to the phase difference is used as the control voltage by the loop filter. In a phase locked circuit which is supplied to a voltage controlled oscillator so that its oscillation output signal is phase-synchronized with a reference signal, there is a determining means for determining the synchronization state, and the loop filter is configured based on the determination result of the determining means. 1. A phase synchronized circuit comprising: a control means for varying a control voltage output from the phase synchronization circuit. (2) The loop filter includes a low-pass filter that smoothes the difference signal voltage of the phase comparator, and sets the lock range by converting the output voltage of the low-pass filter into a control voltage according to the supplied digital data. The phase synchronized circuit according to claim 1, further comprising a digital/analog converter, and the supplied digital data is changed by the control means based on the determination result of the determination means. (3) The loop filter includes a digital/analog converter that outputs a reference voltage as a control voltage according to supplied digital data and sets an oscillation center frequency;
an adder that adds a control voltage from the difference signal voltage of the phase comparator to the control voltage and supplies the result to the voltage controlled oscillator, and the supplied digital data is determined based on the determination result of the determination means. 2. The phase locked circuit according to claim 1, wherein the addition and subtraction are performed by a control means. (4) The phase synchronized circuit according to claim 3, wherein the control means includes a storage means for storing digital data updated by addition and subtraction. (5) The phase synchronized circuit according to claim 4, wherein the storage means is a nonvolatile memory in which updated digital data can be written and read. (6) The discrimination means is a double-wind comparator circuit that compares the output voltage of a low-pass filter that smoothes the difference signal voltage of the phase comparator with each reference voltage and outputs an output state based on the comparison result. The first characterized by
A phase locked circuit according to the claims.