JP2867466B2 - PLL circuit - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention performs digital processing by quantizing a phase difference.
An object of the present invention is to provide a PLL circuit in which the jitter of the output signal is small even if the jitter of the input signal is large.

FIG. 13 shows a conventional PLL circuit. In FIG. 13, PD 28 is a phase comparator (hereinafter abbreviated as PD), filter 29 is a filter composed of a resistor and a capacitor, VCO 10 is a voltage controlled oscillator (hereinafter abbreviated as VCO), and frequency divider 11 is a signal This is a frequency divider that divides frequency by 1 / N. For example, if an exclusive OR (hereinafter, abbreviated as EXOR) is used for the PD 28, the characteristics will be as shown in FIG. 14, and its phase gain will be V / π when the power supply voltage is V. A lag-lead filter with characteristics as shown in FIG. 15 is adopted as the filter 29, the voltage-frequency gain of the VCO 10 is Kf, and the open-loop characteristics are obtained. The characteristics are as shown in FIG. No.
In FIG. 16, ω0 is called a gain crossing point and represents a characteristic in a high frequency region of the PLL circuit, and is also called a loop gain K (= ω0).

Similarly, FIG. 17 shows an example of a PLL circuit which is partially digitally processed.

In FIG. 17, PD 28 is a phase comparator, ADC 30 is an analog-to-digital converter (hereinafter abbreviated as ADC) for converting an analog value to a digital value, and multiplier 7 is a multiplier for multiplying the digital value by a constant (A). The digital filter 8 is a digital filter that filters digital values, and the digital filter 8 is a digital filter.
Is a digital-analog converter (hereinafter abbreviated as DAC) for converting a digital value to an analog value, VCO 10 is a voltage controlled oscillator having a voltage-frequency gain of Kf, and frequency divider 11 is a 1 / N frequency divider. For example, an EXOR is used for the PD 28, an analog-to-digital converter with 4-bit resolution is used for the ADC 30, the characteristics of the digital filter 8 are set to the characteristics shown in FIG. 15, and the DAC 9 is an 8-bit digital-to-analog converter. Is used.
At this time, the open loop characteristics Next, if A = 2 ^4, Which is similar to equation (1). The characteristics of the above PLL circuit are similar to those of the analog PLL circuit, but the ADC 30 and
When the resolution of the DAC 9 is low, the effect of the quantization error cannot be ignored, and the problem of the quantization error is added to the problem of the analog PLL circuit.

In the case of the above-described PLL circuit, the larger the loop gain K is, the better the tracking of the input signal is. Therefore, the PLL circuit follows the jitter of the input signal and causes jitter in the output signal.
However, since the characteristics of the PLL circuit itself, that is, the lock range, the pull-in range, and the like are proportional to the loop gain K,
There was a contradictory problem that it is desirable to have as large as possible.

Conventionally, in order to solve such a problem, there has been a method in FIG. 13 in which the characteristics of the filter 29 are switched between at the time of pull-in and at the time of stable operation. FIG. 18 shows a characteristic diagram when the characteristic of the filter 29 is switched. By changing the filter constants, the loop characteristics are changed, and as shown in Fig. 18, when the loop is pulled in, a high gain crossing point is set so that pulling in is easy. This is a method of reducing jitter and reducing jitter.

However, in the case of an analog PLL circuit, if an attempt is made to greatly change the gain intersection, noise is generated at the time of switching, and the PLL is desynchronized. VCO when switching
Although there is a method of holding the voltage of 10, the droop is inevitably generated, and the voltage of the VCO 10 cannot be completely held.

In addition, in the case of a PLL circuit in which a part is digitally processed, setting the gain intersection at a frequency that is too low so as to extremely reduce the jitter can reduce the digital filter 8.
Requires a longer operation word length, which is not practical.

As described above, there is also a problem in the method of switching the characteristics of the loop filter, and there is no optimum method.

Problems to be Solved by the Invention In the case of the conventional PLL circuit, the larger the loop gain K is, the better the tracking of the input signal is. Therefore, the PLL follows the jitter of the input signal, and the jitter occurs in the output signal.
However, since the characteristics of the PLL circuit itself, that is, the lock range, the pull-in range, and the like are proportional to the loop gain K,
There was a contradictory problem that it is desirable to have as large as possible.

An object of the present invention is to provide a PLL circuit which solves the above-mentioned problem and which can obtain a stable operation with very little jitter even in a PLL circuit partially digitally processed.

Means for Solving the Problems (1) PL at least partially performing digital processing
An L circuit, a first quantizing means for quantizing the phase difference, a first switching means for switching a sampling frequency at the time of quantization, and a phase difference quantized by the first quantizing means. There are provided first constant multiplying means for multiplying a constant, and second switching means for switching the sampling frequency by the first switching means and for switching the amount of the first constant multiplying means by a constant.

A first counter for counting the number of pulses of the input signal; a second counter for counting the output pulses of the control oscillator constituting the PLL; and a first counter. A first subtractor for obtaining a difference between the second counters; and a first holding unit for holding a subtraction result of the first subtractor.

A first quantizer, a first limiter for extracting only the lower M bits of the first and second counters, a first subtractor, a first holding means, and the first holding means; And a second subtractor for subtracting a predetermined first value from the output of the first limiter.

Further, a third switching means for switching the sampling frequency by the first switching means and simultaneously switching the characteristics of the loop filter of the PLL circuit is provided.

(2) first detection means for detecting that the value of the control input of the control oscillator constituting the PLL circuit is within a predetermined first range; and A second detecting that it is within the first range
Is provided.

(3) Second holding means for holding a control input of a control oscillator constituting the PLL circuit immediately before switching the sampling frequency by the first switching means, and a value held by the second holding means. A first adder that adds a control input value of a control oscillator constituting the PLL circuit;

(4) a fourth detecting means for detecting that an output of the first quantizing means is larger than a predetermined second value; an output of the second detector; and a fourth detecting means. A selector for selecting and outputting one of the outputs of the container.

(5) third holding means for holding the output of the first quantization means at a predetermined point in time, first switching means for switching the sampling frequency, and the output of the third holding means and the output of the third holding means. A third subtractor for subtracting the output of the first quantization unit from the output of the first quantization unit.

(6) a fourth holding means for holding an output of the first quantization means at a predetermined time, and an output of the first quantization means and an output of the fourth holding means. A third subtractor for subtracting, and a fourth subtractor for subtracting a predetermined constant amount from the fourth holding means at predetermined time intervals and updating the contents of the fourth holding means; Fifth detecting means for detecting that the output of the fourth holding means is within a predetermined range, and output of the fourth holding means is within a predetermined range by the fifth detecting means. A first clearing means for detecting the fact that the output of the fourth holding means is zero.

(7) A fourth detecting means for detecting that the output of the first quantizing means exceeds a predetermined range, and a first detecting means for switching a sampling frequency when the output is detected by the fourth detecting means. Switching means, a sixth detection means for detecting that the output of the first quantization means exceeds a predetermined range after switching by the first switching means, and a detection means for detecting the output by the sixth detection means. When done, the first
And second clearing means for setting the output of the quantizing means to zero.

Operation The operation of the present invention by the above means is as follows.

(1) PLL that performs digital processing at least partially
A first quantization means for quantizing the phase difference;
By providing a means for switching the sampling frequency when quantizing, the PLL is configured by increasing the sampling frequency at the time of pull-in to make the pull-in time shorter, and at the time of stable operation after the pull-down, lowering the sampling frequency. The change in the frequency of the controlled oscillator can be reduced and stabilized.

In particular, the first quantization means is a first counter that counts the number of pulses of an input signal, a second counter that counts output pulses of a control oscillator that constitutes a PLL circuit, When a first subtracter for obtaining a difference between the counter of the second counter and the second counter and a first holding unit for holding a subtraction result of the first subtractor are provided, the number of bits of the counter is set to an appropriate value. If the sampling frequency is switched to lower, the resolution will increase as a result.

Furthermore, a first limiter for extracting only the lower M bits of the first holding means and a second subtractor for subtracting a predetermined first value from the output of the first limiter are added. An accurate quantized phase difference can be obtained even if there is an offset between the first counter and the second counter.

At the same time, a first constant multiplying means for multiplying the phase difference quantized by the first quantizing means by a constant, and a sampling frequency switching by the first switching means, and a first constant multiplying means. More stable if it is provided with a second switching means for switching the amount by which the constant is multiplied by a constant, and a third switching means for switching the sampling frequency by the first switching means and simultaneously switching the characteristics of the loop filter of the PLL circuit. What
A PLL circuit can be obtained.

(2) first detection means for detecting that the value of the control input of the control oscillator constituting the PLL circuit is within a predetermined first range, and a first time for the predetermined first time And the second detecting means for detecting that the sampling frequency is within the range described above, it is possible to switch the sampling frequency at an appropriate timing.

(3) Second holding means for holding the control input of the control oscillator constituting the PLL circuit immediately before switching the sampling frequency by the first switching means, and the value held by the second holding means and the PLL circuit And the first adder that adds the control input value of the control oscillator that constitutes the above, can pull in the PLL immediately after switching the sampling frequency.

(4) fourth detecting means for detecting that the output of the first quantizing means is larger than a predetermined second value, and the output of the second detecting means and the fourth detecting means. By providing a first selector for selecting and outputting one of the outputs, it is possible to detect a sudden change in the phase difference when the sampling frequency is low, and to obtain a high sampling for the original pull-in. Appropriate timing for switching to a frequency and a means for selecting a signal for switching the sampling frequency can be obtained.

(5) third holding means for holding the output of the first quantizing means at a predetermined time, the first switching means for switching a sampling frequency, and the output of the third holding means. The provision of the third subtractor for subtracting the output of the first quantization means makes it possible to smoothly switch the sampling frequency when there is a large phase difference when switching the sampling frequency.

(6) Fourth holding means for holding the output of the first quantization means at a predetermined point in time, and subtracting the output of the first quantization means and the output of the fourth holding means. A third subtractor, a fourth subtractor for subtracting a predetermined constant amount from the fourth holding means at predetermined time intervals and updating the content of the fourth holding means, Fifth detecting means for detecting that the output of the fourth holding means is within a predetermined range, and detecting that the output of the fourth holding means is within a predetermined range by the fifth detecting means. By providing a first clear means for detecting and making the output of the fourth holding means zero, when the sampling frequency is switched, if there is a large phase difference, the switching is performed smoothly, and after the switching, Promptly the first quantization It is possible to secure the maximum value of the dynamic range of the means.

(7) Fourth detecting means for detecting that the output of the first quantizing means exceeds a predetermined range, and first switching for switching a sampling frequency when detected by the fourth detecting means. Means, and after the switching by the first switching means, sixth detecting means for detecting that the output of the first quantization means exceeds a predetermined range,
A second clearing means for making the output of the first quantizing means zero when detected by the sixth detecting means, whereby the phase difference changes abruptly, Even if the lock range is exceeded, re-pulling can be quickly performed.

Embodiments Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows an embodiment of the present invention. The counter 1 is a counter that counts the input signal, the counter 2 is a counter that counts a signal obtained by dividing the output of the VCO 10 by 1 / N, the subtractor 3 is a subtractor that subtracts the value of the counter 1 from the counter 2,
Latch 4 is a latch circuit for latching the result of subtractor 3, constant 5 is a constant having the same value as the initial offset value of counter 1 and counter 2, and subtractor 6 subtracts the value of constant 5 from the value of latch 4 , A multiplier 7 is a multiplier for multiplying the result of the subtractor 6 by a constant, a digital filter 8 is a digital filter for filtering the result of the multiplier 7, and a DAC 9 is a digital output value of the digital filter 8 to an analog value. A digital-to-analog converter for conversion, a VCO 10 is a voltage-controlled oscillator using the output of the digital-to-analog converter as a voltage control input, and a frequency divider 11 is a frequency divider for dividing the output of the voltage-controlled oscillator to 1 / N.

FIG. 2 shows the operation when there is no offset between the counter 1 and the counter 2. Here, it is simplified for ease of explanation. The counter 1 counts up in proportion to the input signal. The counter 2 counts a signal obtained by dividing the output of the VCO 10, and obtains the difference between the counter 1 and the counter 2 for each sampling period. According to the difference, set the oscillation frequency of VCO10 in the next sampling cycle,
As a result, as shown in FIG. 2, the operation of the counter 2 approaches the operation of the counter 1 and operates in synchronization with the counter 1.

The difference between the counter 1 and the counter 2 becomes a phase difference, and FIG. 3 shows a phase comparison characteristic. As shown in FIG. 3, when 2L is counted in the sampling period, the phase comparison gain has 2L / (2π).

 The open-loop transfer characteristics shown in FIG. 1 will be obtained.

A phase comparator is composed of a counter 1, a counter 2, a subtractor 3, a latch 4, a constant 5, and a subtractor 6, and the phase comparison gain is 2L /
(2π). Multiplier 7 is A times, digital filter 8
Is a characteristic represented by the following equation.

F (s) = (1 + s · T2) / (1 + s · T1) (4) where s is a differential operator, and T2 and T1 are filter time constants.

Although it depends on the configuration of the digital filter 8, if the bilinear transformation is used in the sZ transformation so that the equation (4) can be handled discretely, the equation (4) becomes the following equation.

Here, T represents a sampling period. (Sampling frequency
fs = 1 / T) DAC9 number of bits of the b bits, if the power supply voltage is V, the digital DAC 9 - analog conversion gain becomes V / 2 ^b.
The voltage-frequency conversion gain of the VCO 10 is Kv, and the frequency division ratio of the frequency divider 11 is 1 / N.

From the above, the open loop transfer characteristic is Becomes FIG. 4 shows this characteristic. G
(Z) is a function of the sampling period T.

Here, the behavior when the sampling frequency is switched will be described. When the sampling frequency is switched, the open loop transfer characteristic changes because G (Z) is a function of the sampling period T. If the ratio of T1 to T and the ratio of T2 to T are kept constant in equation (5), the shape of the characteristic will be as if it has just moved in parallel on the ω-gain characteristic diagram. That is, if the coefficients of the digital filter are normalized by the sampling frequency, the translation can be performed on the ω-gain characteristic without changing the coefficients of the digital filter by switching the sampling frequency. At this time, different characteristics may be realized before and after the switching by changing the coefficient of the digital filter. Since each of the input signal and the signal obtained by dividing the frequency of the VCO 10 does not change, in the case of FIG. 1, if the sampling frequency is multiplied by n1, the phase comparison gain becomes 1 / n1. Therefore, it is necessary to multiply the gain of the multiplier 7 which is a constant multiple by n1. To change the amount by which this constant is multiplied,
First, if a quantized phase difference is input to one of the inputs of the multiplier and a constant is input to the other input, a constant multiplication can be performed. By varying the constant input to the multiplier, the amount by which the constant is multiplied can be varied.

The feature of FIG. 1 is that the gain intersection can be lowered by switching the sampling frequency to lower. Also,
Since the counter is used, the jitter generated on average within the sampling period is canceled and does not appear in the phase comparison output. Further, when the sampling frequency is lowered and the sampling period is increased, the input of the DAC 9 is stabilized, so that a stable oscillation frequency of the VCO 10 can be obtained.

As described above, by switching the sampling frequency, the gain intersection can be lowered, and a stable signal with little jitter can be obtained.

Although the VCO 10 is a voltage-controlled oscillator here, it may be a digital-value-controlled oscillator that inputs a digital value and oscillates at a predetermined frequency.

Also, counter 1, counter 2, subtractor 3, latch 4, constant 5,
The subtractor 6, the multiplier 7, the digital filter 8, the DAC 9, the VCO 10, and the frequency divider 11 may be realized by a digital signal processor.

FIG. 5 shows an embodiment of the present invention. The counter 1 is a counter that counts the input signal, the counter 2 is a counter that counts a signal obtained by dividing the output of the VCO 10 by 1 / N, the subtractor 3 is a subtractor that subtracts the value of the counter 1 from the counter 2,
Latch 4 is a latch circuit for latching the result of subtractor 3, multiplier 7 is a multiplier for multiplying the result of subtractor 6 by a constant, digital filter 8 is a digital filter for filtering the result of multiplier 7, and DAC 9 is a digital filter. A digital-to-analog converter that converts the digital output value of the filter 8 to an analog value, a VCO 10 is a voltage-controlled oscillator that uses the output of the digital-to-analog converter as a voltage control input, and a frequency divider 11 is a 1 / N output of the voltage-controlled oscillator. Is a frequency divider. In addition, detector 12
Is a detector for detecting that the output value of the digital filter 8, that is, the input value of the DAC 9 is within a certain range,
Is a detector for detecting that the output value of the digital filter 8 in the detector 12 continues for a time set by the timer 14 within the set range.

FIG. 5 operates in the same manner as FIG. However, FIG. 5 stipulates the timing of switching the sampling frequency, and at least a part thereof is a PLL circuit which performs digital processing, and provides an appropriate switching timing of the sampling frequency. The detection of the timing of switching the sampling frequency is shown in FIG. 7 as an example of the temporal change of the output of the digital filter 8. In the PLL circuit of FIG. 5, the output of the digital filter 8 becomes a certain value with time. Converge. The detector 12 detects that the output of the digital filter 8 is within a predetermined detection range, and the detector 13 detects that the output continues for the time set by the timer 14. Detector
At the timing detected in step 13, the sampling frequency is switched. In FIG. 7, the continuation of one sampling period is detected, and the sampling frequency is switched. Detector 12
By appropriately setting the detection range and the time of the timer 14, an appropriate switching timing can be obtained.

Note that the detector 12 may be provided after the DAC 9, and may be an analog window comparator.

Further, the detector 12 may take the absolute value of the output value of the digital filter 8 and subtract it from a predetermined constant to detect that it is positive.

Further, the detector 12 outputs the output value of the digital filter 8 and
Compare with the upper limit and lower limit determined in advance,
You may detect that it is below an upper limit and below a lower limit.

Note that counter 1, counter 2, subtractor 3, latch 4, multiplier
7, Digital filter 8, Detector 12, Detector 13, Timer 14, D
The AC 9, VCO 10, and 1 / N frequency divider 11 may be realized by a digital signal processor.

FIG. 6 shows an embodiment of the present invention. The counter 1 is a counter that counts the input signal, the counter 2 is a counter that counts a signal obtained by dividing the output of the VCO 10 by 1 / N, the subtractor 3 is a subtractor that subtracts the value of the counter 1 from the counter 2,
Latch 4 is a latch circuit for latching the result of subtractor 3, multiplier 7 is a multiplier for multiplying the result of subtractor 6 by a constant, digital filter 8 is a digital filter for filtering the result of multiplier 7, and latch 15 is A latch for holding the output value of the digital filter 8 at the same time as switching the sampling frequency;
The adder 16 adds the output of the digital filter 8 and the output of the latch 15, and outputs the result. The DAC 9 is the digital filter 8
VCO10 is a voltage-controlled oscillator that uses the output of the digital-to-analog converter as a voltage control input, and frequency divider 11 divides the output of the voltage-controlled oscillator into 1 / N. It is a frequency divider that circulates. The detector 12 detects that the output value of the digital filter 8 is within a certain range, and the detector 13 is set by the timer 14 within the range where the output value of the digital filter 8 is set by the detector 12. Is a detector that detects that it lasts for a given time.

The operation in FIG. 6 operates in the same manner as in FIGS. 1 and 5.
However, the present invention provides a PLL circuit that can more smoothly switch the sampling frequency by the latch 15 and the adder 16. The operation of the latch 15 and the adder 16 will be described below.

FIG. 7 shows the temporal change of the output value of the digital filter 8. When the latch 15 and the adder 16 are not provided, when the sampling frequency is switched, the phase comparison output becomes the value before switching. Through the multiplier and digital filter 8 to DA
Input to C9. As described with reference to FIG. 1, when the sampling frequency is switched, in order to maintain the open-loop characteristic in a similar manner to the sampling period, the value of a constant multiple of the multiplier 7 is set to the sampling frequency. It is necessary to make the value proportional to the ratio.
Therefore, for example, when the sampling frequency is lowered, it is necessary to reduce the constant times of the multiplier 7 by that ratio. Immediately after the switching of the sampling frequency, the phase comparison output before the switching of the sampling frequency is input, so that the output of the digital filter 8 is reduced by the decrease of the constant times of the multiplier 7. As a result, the output voltage of the DAC 9 may be largely shifted, and as a result, the output frequency of the VCO 10 may be largely shifted and the PLL may be deviated.

On the other hand, if the latch 15 and the adder 16 are provided as shown in FIG. 6, the output value of the digital filter 8 immediately after the switching of the sampling frequency is held, so that immediately after the switching of the sampling frequency, the neighboring DACs 9 before the switching are switched. An input is obtained, and the output frequency of the VCO 10 does not greatly fluctuate as described above. Further, since the output value of the digital filter 8 immediately after the switching is always added by the adder, the required necessary phase comparison output may be small, and it is possible to shift to the stable state sooner.

Note that counter 1, counter 2, subtractor 3, latch 4, multiplier
7, digital filter 8, VCO10, frequency divider 11, detector 12, detector
13, the timer 14, the latch 15, and the adder 16 may be realized by a digital signal processor.

FIG. 8 shows an embodiment of the present invention. The counter 1 is a counter that counts the input signal, the counter 2 is a counter that counts a signal obtained by dividing the output of the VCO 10 by 1 / N, the subtractor 3 is a subtractor that subtracts the value of the counter 1 from the counter 2,
Latch 4 is a latch circuit for latching the result of subtractor 3, multiplier 7 is a multiplier for multiplying the result of subtractor 6 by a constant, digital filter 8 is a digital filter for filtering the result of multiplier 7, and latch 15 is A latch for switching the sampling frequency and holding the output value of the digital filter 8 at the same time, an adder 16 for adding the output of the digital filter 8 and the output of the latch 15 for output, and a DAC 9 for a digital output of the digital filter 8. A digital-to-analog converter that converts a value to an analog value, VCO 10 is a voltage-controlled oscillator that uses the output of the digital-to-analog converter as a voltage control input, and divider 11 is a divider that divides the output of the voltage-controlled oscillator by 1 / N. It is a circulator.
The detector 12 detects that the output value of the digital filter 8 is within a certain range, and the detector 13 is the detector 12.
Is a detector for detecting that the output value of the digital filter 8 continues within the set range for the time set by the timer 14. The detector 17 detects that the output of the latch 4 has exceeded a predetermined value. The selector 18 is a selector for selecting a signal from the detector 13 or a signal from the detector 17.

FIG. 8 operates similarly to FIGS. 1, 5 and 6. However, FIG. 8 shows that when the phase difference suddenly changes due to the detector 17 and the PLL circuit cannot operate,
The sampling frequency can be returned to the original frequency and re-pulling can be performed.

8 will be described focusing on the role of the detector 17. Ninth
The figure shows the time change of the phase comparison output. Ninth
It is assumed that the phase difference momentarily increases at the point a in the figure, and the phase comparison output momentarily increases. If the detector 17 is not provided, there is no way to cope with the case where the phase comparison output becomes too large and exceeds the dynamic range of the system, and the PLL remains off.

However, if the detector 17 is provided, it is detected that the phase comparison output exceeds a predetermined limit value, and the sampling frequency is switched so that the phase difference quickly falls within a predetermined range. be able to. For example, when the sampling frequency is low, the response of the system is slow, and when the beach phase comparison output is larger than the value detected by the detector 17, it takes a very long time to return the phase difference to within a predetermined range. Take it. But,
If the sampling frequency is switched to a higher sampling frequency at the time of pull-in, it is possible to pull in quickly. The selector 18 is a selector for selecting which of the output of the detector 13 and the output of the detector 17 is used for the switching signal of the sampling frequency. In the normal case, after switching the number of sampling arcs by the detector 13, the selector 18 selects the detector 17, and after the sampling frequency is switched by the detector 17, the detector 13 is selected. Good to keep.

Note that counter 1, counter 2, subtractor, latch 4, multiplier
7, digital filter 8, VCO10, frequency divider 11, detector 12, detector
13, Timer 14, Latch 15, Adder 16, Detector 17, Selector 18
May be realized by a digital signal processor.

Alternatively, the detector 17 may detect the positive value by taking the absolute value of the output value of the latch 4 and subtracting it from a predetermined constant.

Further, the detector 17 compares the output value of the latch 4 with a predetermined upper limit value and lower limit value, and
In addition, it may be detected that the value is equal to or less than the lower limit.

FIG. 10 shows an embodiment of the present invention. The counter 1 is a counter for counting the input signal, the counter 2 is a counter for counting a signal obtained by dividing the output of the VCO 10 by 1 / N, the subtractor 3 is a subtractor for subtracting the value of the counter 1, and the latch 4 is a subtractor. A latch circuit for latching the result of the multiplier 3, a multiplier 7 for multiplying the result of the subtracter 6 by a constant, a digital filter 8 for filtering the result of the multiplier 7,
The latch 15 switches the sampling frequency and simultaneously holds the output value of the digital filter 8, the adder 16 adds the output of the digital filter 8 and the output of the latch 15, and outputs the result. The DAC 9 is the digital filter 8 VCO10 is a voltage-controlled oscillator that uses the output of the digital-to-analog converter as a voltage control input, and frequency divider 11 divides the output of the voltage-controlled oscillator into 1 / N. It is a frequency divider that circulates. In addition, detector 12
Is a detector for detecting that the output value of the digital filter 8 is within a certain range, and a detector 13 is for a time set by the timer 14 within a range where the output value of the digital filter 8 is set by the detector 12. It is a detector that detects continuation.
The detector 17 detects that the output of the latch 4 has exceeded a predetermined value. Selector 18 is a detector
This is a selector for selecting between the signal of 13 and the signal of the detector 17.
The latch 19 is a latch for holding the value of the latch 4 when the sampling frequency is switched by the signal of the detector 17, and the subtractor 20 is for switching the sampling frequency by the signal of the detector 17 and then outputting the latch 4. This is a subtractor that subtracts the output of the latch 19 from the output and outputs the result.

FIG. 10 operates in the same manner as FIG. 1, FIG. 5, FIG. 6, and FIG. However, the detector 1 is provided by the latch 19 and the subtractor 20.
A stable phase comparison output can be obtained even after the sampling frequency is switched in step 7.

Considering a case where the sampling frequency is switched back to the original value by exceeding the limit of the phase comparison output by the detector 17 as a representative, when the sampling frequency is switched, the reverse phenomenon of FIG. In order to obtain consistency as a system, it is necessary to return the constant times of the multiplier 7 to the original value. When the latch 19 and the subtracter 20 are not provided, the phase comparison output has a large value even after the sampling frequency is switched, and the output of the latch 4 is multiplied as it is to be a very large value, and the PLL is deviated. I will.

However, if the latch 19 and the subtracter 20 are provided, the detector 17 holds the value of the latch 4 immediately after switching the sampling frequency,
After the sampling frequency is switched, the value of the latch 19 is subtracted from the value of the latch 4 of the phase comparison output to obtain an appropriate value as the dynamic range. This is equivalent to the case where the phase difference has an offset value, and the system operates so that the system is stabilized with an offset by the value held in the latch 19.

Note that counter 1, counter 2, subtractor 3, latch 4, multiplier
7, digital filter 8, VCO10, frequency divider 11, detector 12, detector
13, Timer 14, Latch 15, Adder 16, Detector 17, Selector 18,
The latch 19 and the subtractor 20 may be realized by a digital signal processor.

FIG. 11 shows an embodiment of the present invention. The counter 1 is a counter that counts the input signal, the counter 2 is a counter that counts a signal obtained by dividing the output of the VCO 10 by 1 / N, the subtractor 3 is a subtractor that subtracts the value of the counter 1 from the counter 2,
Latch 4 is a latch circuit for latching the result of subtractor 3, multiplier 7 is a multiplier for multiplying the result of subtractor 6 by a constant, digital filter 8 is digital filter 8 for filtering the result of multiplier 7, and latch 16 Is a latch that switches the sampling frequency and simultaneously holds the output value of the digital filter 8, an adder 16 adds the output of the digital filter 8 and the output of the latch 15, and outputs the result. A digital-to-analog converter that converts an output value to an analog value, a VCO 10 is a voltage-controlled oscillator that uses the output of the digital-to-analog converter as a voltage control input, and a frequency divider 11 divides the output of the voltage-controlled oscillator by 1 / N. It is a frequency divider.
The detector 12 detects that the output value of the digital filter 8 is within a certain range, and the detector 13 is the detector 12.
Is a detector for detecting that the output value of the digital filter 8 continues within the set range for the time set by the timer 14. The detector 17 detects that the output of the latch 4 has exceeded a predetermined value. The selector 18 is a selector for selecting a signal from the detector 13 or a signal from the detector 17. The latch 19 is a latch for holding the value of the latch 4 when the sampling frequency is switched by the signal of the detector 17, and the subtractor 20 is for switching the sampling frequency by the signal of the detector 17 and then outputting the latch 4. This is a subtractor that subtracts the output of the latch 19 from the output and outputs it. The constant 21 is a predetermined constant, the subtractor 22 is a subtractor that subtracts the value of the constant 21 from the latch 24, the selector 23 is a selector that selects the output of the latch 19 or the output of the subtractor 22, and the latch 24 is A latch for holding the output of the selector 23, a timer 25 is a timer for generating the timing for holding the latch 24, and a detector 26 detects that the output of the latch 24 has become substantially zero and outputs a signal for clearing the latch 24. It is a detector that occurs.

11 operates in the same manner as in FIGS. 1, 5, 6, 8, and 10. FIG. However, constant 21, subtractor 22, selector 2
3, the latch 24, the timer 25, and the detector 26 quickly return the value corresponding to the offset component of the latch 19 to zero even after the sampling frequency is switched by the detector 17, so that the original system dynamic range can be obtained. It was done.

As described in FIG. 10, the latch 19 acts like an offset of the phase difference. However, if the re-pull-in is performed while the latch 19 is kept as it is, and the phase difference of the PLL is largely shifted, the value is added more and more, and eventually exceeds the dynamic range of the system.

Therefore, it is necessary to return the value of the latch 19 to zero immediately after the sampling frequency is switched by the detector 17. No.
In Fig. 11, the sampling frequency is switched by the detector 17 and latched.
19 holds the value of latch 4. At the same time, the selector 23
Through the latch 19, the value of the latch 19 is held in the latch 24. latch
Immediately after the value of 19 is held in the latch 24, the selector 23
Select 22 outputs, and every time determined by timer 25,
The subtracter 22 subtracts a predetermined constant 21 from the output of the latch 24, and the subtractor 22
Is held, and the contents of the latch 24 are updated every time of the timer 25. In this manner, the update of the content of the latch 24 is continued, and the detector 26 detects that the value has become substantially zero, and
Clear the contents of 24. At the same time, the selector 23 selects the latch 19. In this way, the input to be added to the adder 2 decreases every time set by the timer 25, and finally becomes zero. At the time when the value becomes zero, preparation for switching the sampling frequency is made again. The above situation will be described with reference to FIG. T ₂ is a time determined by the timer 25. Phase comparison output at a point beyond the limit value Yuki decreased contents of latch 24 every T ₂ hours, gradually asymptotic to the original value. At point b, the value of the latch 24 becomes substantially zero, returning to the original loop and switching the sampling frequency.

In this way, the dynamic range of the system can be maintained even if the PLL frequently shifts.

Note that counter 1, counter 2, subtractor 3, latch 4, multiplier
7, digital filter 8, VCO10, frequency divider 11, detector 12, detector
13, Timer 14, Latch 15, Adder 16, Detector 17, Selector 18,
Latch 19, subtractor 20, constant 21, subtractor 22, selector 23, latch 2
4. The timer 25 and the detector 26 may be realized by a digital signal processor.

FIG. 12 shows an embodiment of the present invention. The counter 1 is a counter that counts the input signal, the counter 2 is a counter that counts a signal obtained by dividing the output of the VCO 10 by 1 / N, the subtractor 3 is a subtractor that subtracts the value of the counter 1 from the counter 2,
Latch 4 is a latch circuit for latching the result of subtractor 3, multiplier 7 is a multiplier for multiplying the result of subtractor 6 by a constant, digital filter 8 is a digital filter for filtering the result of multiplier 7, and latch 15 is A latch for switching the sampling frequency and holding the output value of the digital filter 8 at the same time, an adder 16 for adding the output of the digital filter 8 and the output of the latch 15 for output, and a DAC 9 for a digital output of the digital filter 8. A digital-to-analog converter that converts a value to an analog value, VCO 10 is a voltage-controlled oscillator that uses the output of the digital-to-analog converter as a voltage control input, a frequency divider 11
Is a frequency divider for dividing the output of the voltage controlled oscillator to 1 / N. The detector 12 detects that the output value of the digital filter 8 is within a certain range, and the detector 13 is set by the timer 14 within the range where the output value of the digital filter 8 is set by the detector 12. Is a detector that detects that it lasts for a given time. The detector 17 detects that the output of the latch 4 has exceeded a predetermined value. The selector 18 is a selector for selecting a signal from the detector 13 or a signal from the detector 17. The latch 19 is a latch for holding the value of the latch 4 when the sampling frequency is switched by the signal of the detector 17, and the subtractor 20 is for switching the sampling frequency by the signal of the detector 17 and then outputting the latch 4. This is a subtractor that subtracts the output of the latch 19 from the output and outputs the result. The constant 21 is a predetermined constant, the subtractor 22 is a subtractor that subtracts the value of the constant 21 from the latch 24, the selector 23 is a selector that selects the output of the latch 19 or the output of the subtractor 22, and the latch 24 is A latch for holding the output of the selector 23, a timer 25 is a timer for generating the timing for holding the latch 24, and a detector 26 detects that the output of the latch 24 has become substantially zero and outputs a signal for clearing the latch 24. It is a detector that occurs. Detector 27 detects that the output of latch 4 has exceeded a predetermined limit,
This is a detector that generates a signal for clearing the counter 1 and the counter 2 to an initial value.

As described in FIG. 11, it is possible to follow the instantaneous large change in the phase difference, but it is not possible to cope with the case where the phase difference continuously shifts greatly beyond the dynamic range of the PLL system. . For example, a case where a frequency exceeding the frequency range in which the PLL system can be locked is input to the input. In such a case, it is necessary to take measures to immediately lock when a signal within the PLL lock range is input. For this purpose, the output of the latch 4 is monitored by the detector 27, and when the output exceeds the predetermined limit value, an abnormal situation is detected. At the same time as detecting an abnormal condition with the detector 27, the counter 1 and the counter 2 are cleared to the initial state, and when a signal within the lock range is always input, it is possible to take measures to lock. .

Note that counter 1, counter 2, subtractor 3, latch 4, multiplier
7, digital filter 8, VCO10, frequency divider 11, detector 12, detector
13, Timer 14, Latch 15, Adder 16, Detector 17, Selector 18,
Latch 19, subtractor 20, constant 21, subtractor 22, selector 23, latch 2
4. The timer 25, the detector 26, and the detector 27 may be realized by a digital signal processor.

As described above, according to the present invention, the larger the loop gain K is, the better the tracking of the input signal is, and the jitter of the input signal is tracked. Since its own characteristics, that is, the lock range, the pull-in range, and the like are proportional to the loop gain K,
Solving the contradictory problem that it is desirable to be as large as possible, with a PLL circuit that has a large range of pull-in and a part of which is digitally processed, the jitter of the output signal is extremely small even if the jitter of the input signal is large. It is intended to provide a PLL circuit capable of obtaining a stable operation.

Also, no matter what the phase difference is, it can always be pulled in if it is within the PLL lock range.
A PLL circuit can be provided.

[Brief description of the drawings]

FIGS. 1 to 12 relate to the present invention, and FIGS.
FIG. 6, FIG. 6, FIG. 8, FIG. 10, FIG. 11, and FIG. 12 are block diagrams of a PLL circuit according to one embodiment of the present invention, and FIG. FIG. 3, FIG. 3 is a phase comparison characteristic diagram, FIG. 4 is a diagram showing a change in open loop characteristic when the sampling frequency is switched, FIG. 7 is a diagram showing a change in the output of the digital filter, FIG. 9 is a diagram showing a time change of the phase comparison output when the phase difference changes suddenly. 13 to 18 show a conventional example, FIG. 13 is a block diagram showing a conventional PLL circuit, FIG. 14 is a diagram showing a phase comparison characteristic of a PD, and FIG. 15 is a diagram showing a filter characteristic. FIG. 16 is a diagram showing the open-loop characteristics of the conventional example, FIG. 17 is a block diagram of the conventional example in which a part is digitally processed, and FIG. 18 is an open diagram when the filter characteristics are switched. It is a loop characteristic diagram. 1 ... Counter, 2 ... Counter, 3 ... Subtractor, 7 ...
... Multiplier, 8 ... Digital filter, 9 ... DAC (Digital-to-Analog Converter), 10 ... VCO, 11 ... Divider, 2
8 PD (phase comparator), 29 filter, 30 ADC
(Analog-digital converter).

Continuation of the front page (58) Field surveyed (Int.Cl. ⁶ , DB name) H03L 7/06-7/14

Claims (10)

(57) [Claims] 1. A PLL circuit at least partially performing digital processing, comprising: first quantization means for quantizing a phase difference; and first switching means for switching a sampling frequency at the time of quantization. A first constant multiplying means for multiplying the phase difference quantized by the first quantizing means by a constant, and a sampling frequency being switched by the first switching means at the same time as a constant multiplication of the first constant multiplying means. And a second switching means for switching an amount to be performed. A first counter for counting the number of pulses of an input signal; a second counter for counting output pulses of a control oscillator constituting a PLL; To find the difference between the second counter and the second counter
2. The PLL circuit according to claim 1, further comprising: a subtractor for storing the subtraction result of the first subtractor. 3. A first quantizing means, comprising a first and a second counter, a first subtractor, a first holding means, and a first quantizing means.
And a second subtractor for subtracting a predetermined first value from the output of the first limiter. 3. The PLL circuit according to claim 2, wherein 4. The apparatus according to claim 1, further comprising third switching means for switching the sampling frequency by the first switching means and simultaneously switching the characteristics of the loop filter of the PLL circuit. PLL circuit. 5. A PLL circuit at least partially performing digital processing, wherein a first quantizing means for quantizing a phase difference and a control input value of a control oscillator constituting the PLL circuit are predetermined. A first detecting means for detecting that the vehicle is within the first range, and a first detecting means for detecting that the vehicle is within the first range for a predetermined first time. 2. A PLL circuit comprising: a second detection unit; and a first switching unit that switches a sampling frequency based on detection by the second detection unit. 6. A PLL circuit at least partially performing digital processing, wherein said first quantizing means quantizes a phase difference, said first switching means switches a sampling frequency, and said first switching means. Means for holding the value of the control input of the control oscillator constituting the PLL circuit immediately before switching the sampling frequency by the means; and the value of the control oscillator constituting the PLL circuit with the value held by the second holding means. A first adder for adding the control input value to the control signal.
L circuit. 7. A PLL circuit at least partially performing digital processing, wherein a first quantizing means for quantizing a phase difference and a control input value of a control oscillator constituting the PLL circuit are predetermined. A first detecting means for detecting that the vehicle is within the first range, and a first detecting means for detecting that the vehicle is within the first range for a predetermined first time. 2 detecting means, a third detecting means for detecting that the output of the first quantizing means is larger than a predetermined second value, and an output of the second detector and the third detecting means. A PLL comprising: first selection means for selecting and outputting one of the outputs of a detector; and first switching means for switching a sampling frequency by an output of the first selection means. circuit. 8. A PLL circuit which is at least partially digitally processed, and holds a first quantization means for quantizing a phase difference and an output of the first quantization means at a predetermined time. A third holding unit that performs switching, a first switching unit that switches a sampling frequency, a third subtractor that subtracts an output of the third holding unit and an output of the first switching unit, 8. The PLL circuit according to claim 7, wherein after the switching by the switching means, the output of the third subtractor is controlled as a phase difference output. 9. A PLL circuit which is at least partially digitally processed, and holds a first quantizing means for quantizing a phase difference and an output of the first quantizing means at a predetermined time. A fourth holding unit, a third subtractor for subtracting the output of the first quantization unit and the output of the fourth holding unit, and a third subtractor for every predetermined time from the fourth holding unit. A fourth subtractor for subtracting a predetermined amount and updating the contents of the fourth holding means; and a fourth subtractor for detecting that the output of the fourth holding means is within a predetermined range. A first clearing means for detecting that the output of the fourth holding means is within a predetermined range by means of the fourth detecting means and making the output of the fourth holding means zero. Characterized by having
PLL circuit. 10. A PLL circuit at least partially performing digital processing, wherein a first quantizing means for quantizing a phase difference and an output of the first quantizing means exceed a predetermined range. Third detecting means for detecting the fact, a first switching means for switching a sampling frequency when detected by the third detecting means, and a first quantizing means after switching by the first switching means. A fifth detecting means for detecting that the output of the first quantizing means exceeds a predetermined range, and a second clearing means for making the output of the first quantizing means zero when detected by the fifth detecting means. A PLL circuit comprising: