JPH04189029A - Pll circuit - Google Patents

Abstract

PURPOSE:To generate an output with fast tracking and excellent stability by selecting either of a 1st integration device and a 2nd integration device depending on a difference of output voltages of the 1st integration device with a small time constant and a 2nd integration device with a large time constant. CONSTITUTION:When fluctuation of an input signal fH1 is large, a pulse voltage is outputted from a phase comparator 1, and an output voltage VA changes fast in following to a pulse voltage since the time constant of a 1st integration device 2 is small. On the other hand, an output voltage VB is not fast changed because a 2nd integration device 3 has a small time constant. Thus, a voltage difference between both the output voltages VA,VB is produced to be a prescribed value or over, a sampling clock with fast tracking but with less stability than the case with the 2nd integration device is generated by selecting the 1st integration device 2. Furthermore, when fluctuation of the input signal fH1 is small, a sampling clock having an opposite characteristic to that above is obtained stably at all times.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention is used, for example, to create a sampling clock in video equipment that performs digital signal processing by A/D converting a video signal.1) L, 1. , concerning circuits.

[Prior art] Fig. 2 shows a conventional F') 1. i. This is a flow diagram showing the configuration of the circuit. In the same figure, (1) is a phase comparator, which detects the phase difference depending on the phase difference between the horizontal synchronizing signal [1■1 of the video signal and the signal fHo created by the self-loop. to generate and output pulse voltage. (8) is an integrator that balances the output of this phase comparator (1), (6) is a voltage controlled oscillator that oscillates based on the output voltage of this integrator (8), and (7) is this voltage controlled oscillator (6). ) is a frequency divider that divides the output of this frequency divider (7
) is fed back to the phase comparator (1) to produce an output signal synchronized with the input signal fHI.

Next, the operation of the above configuration will be described in the case of creating a sampling clock for A/D conversion of a video signal.

The horizontal synchronization signal fHl of the video signal and the signal fHO generated by the self-loop are input to a phase comparator (1), which outputs a pulse voltage according to the phase difference between these two signals fH1 and fllO. This output pulse voltage is input to an integrator (8), balanced, and becomes a constant voltage.

This constant voltage is then input to the voltage controlled oscillator (6), which outputs the oscillation frequency while changing it according to the input terminal. This output signal is input to a frequency divider (7), frequency-divided, and fed back to the phase comparator (1) as a signal fHO in E for manual input.

The loop as described above produces an output fosc=:sampling clock whose phase is synchronized with the input signal fHI.

In the P+-L circuit described in 1., by increasing the time constant of the integrator (8) and using an integrator (8) with high stability and slow follow-up, stability that is synchronized with the horizontal synchronous frequency fHI can be achieved. On the one hand, they created a sampling clock with slow follow-up performance. Here, when the input signal fH1 fluctuates greatly, the time constant of the integrator (8) is large, so the integrator (8) responds to the pulse voltage output from the 1-phase comparator (1).
) is slow in tracking the output voltage, and synchronized output may not be obtained.

[Problem to be solved by the invention] Since the conventional PLL circuit is configured as described above,
When the horizontal synchronization frequency of the video signal fluctuates greatly or when a signal is input in which the horizontal synchronization signal is disturbed around the vertical synchronization signal, the time constant of the integrator (8) may be changed to increase stability. Take it big.

Because the followability is slow, it is impossible to create a synchronized sampling clock, and it is also slow to return to the original synchronized sampling clock after being disrupted.

This invention was made to solve the above-mentioned problems, and its purpose is to provide a PLL circuit that can always create a stable sampling clock without synchronization disturbance even if the input frequency fluctuates greatly. shall be.

[Means for Solving the Problems] A PLL circuit according to the present invention includes a first integrator with a small time constant and a second integrator with a large time constant, and calculates the output voltage difference between the two integrators. The present invention is characterized in that the first and second integrators are configured to be switched in accordance with.

C Effect 1 According to the present invention, either the first or second integrator is switched depending on the output voltage difference between the first integrator with a small time constant and the second integrator with a large time constant. According to
It has fast followability and can produce output with good stability.

[Embodiment of the Invention] Hereinafter, an embodiment of the present invention will be described based on the drawings.

FIG. 1 is a block diagram showing the configuration of a PLL circuit according to an embodiment of the present invention.

(1), (B), and (?) are the same as those in the conventional example shown in FIG. 2, so the same reference numerals are given to the corresponding parts and detailed explanation thereof will be omitted.

In Fig. 1, (2) is a first integrator with a small time constant, (3) is a second integrator with a large time constant, and (4) is a voltage difference detector. Integrator (2), (3
) to detect the output voltage difference. (5) is a changeover switch,
The first and second integrators (2) use the output of the voltage difference detector (4) as a control signal.

Switch the output of (3).

Next, the operation of the above configuration will be explained.

The voltage difference detector (4) detects the output voltage V of the first integrator (2).
The difference between the output voltage VB of A and the second integrator (3) is detected, and if the voltage difference is larger than a predetermined value, the first integrator (2) is selected, and if it is smaller, the second integrator (2) is selected. A switching control signal is output to the changeover switch (5) so as to select the integrator (3).

Here, when the fluctuation value of the input signal fH1 is small, the output from the phase comparator (1) is stable, so the output voltage VA of the first integrator (2) is also the same as that of the second integrator (3). ) are also at substantially the same potential, and the voltage difference detector (4) outputs a control signal to select the second integrator (3). In this way, when the second integrator (3) is selected, this second integrator (3) balances the pulse voltage well due to its large time constant, and has a slow tracking performance but good stability. Create a sampling clock.

In addition, when the fluctuation value of the input signal fH1 is large, a pulse voltage is output from the phase comparator (1), and the first integrator (2) follows the pulse voltage quickly due to its small time constant. While changing the output voltage VA, the second integrator (3
) does not change the output voltage VB very quickly because it has a large time constant. Therefore, when a voltage difference occurs between both output voltages VA and VB and exceeds a predetermined value, the first integrator (2
) to create a sampling clock that is not stable but has fast followability.

By switching the first and second integrators (2) and (3) as described above, an optimal sampling clock is always created regardless of fluctuations in the input frequency fH1.

In the above embodiment, the voltage difference detector (4) detects the first
The second integrator (2) and the second integrator (3) are selected, but both integrators (2) and (3) can be used in response to sudden and one-off input frequency fluctuations such as external noise. output voltage VA
,! Since the -VB voltage difference becomes very large, it is possible to take advantage of this and open the selector switch (5) to eliminate the effect on the output and create a more stable sampling clock. can.

[Effects of the Invention] As described above, according to the present invention, by switching two integrators with different time constants depending on the fluctuation value of the frequency of the input signal, it is possible to always create a stable sampling clock. be effective.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of a PLL circuit according to an embodiment of the present invention, and FIG. 2 is a block diagram showing the configuration of a conventional PLL circuit. (1)... Phase comparator, (2)... First integrator,
(3)...second integrator, (4)...voltage difference detector, (5)...changeover switch, (6)...voltage controlled oscillator, (7)...frequency division vessel. In addition, the same symbols in the figures indicate the same or equivalent parts.

Claims (1)

[Claims] (1) A phase comparator that generates a voltage based on the phase difference between the input signal and the self-loop, and a first integrator with a small time constant;
A second integrator with a large time constant, a changeover switch that switches between the first and second integrators, and a control signal of the changeover switch that is output according to the output voltage difference of the first and second integrators. a voltage difference detector, a voltage controlled oscillator whose control signal is the output voltage of an integrator switched by the output of the voltage difference detector, and a frequency divider which divides the output of the voltage controlled oscillator, A PLL circuit characterized in that it is configured to output a signal synchronized with an input frequency by feeding back the output of the frequency divider to the phase comparator.