KR20040015617A - Delay Locked Loop including phase interpolator having good linearity - Google Patents

Abstract

PURPOSE: A delay-locked loop circuit provided with a phase interpolator with a linear characteristics is provided to reduce the clock jitter by making the phase interpolator have a high linearity in such a way that the slope of the input signal of the phase interpolator is optimized. CONSTITUTION: A delay-locked loop circuit provided with a phase interpolator with a linear characteristics includes a delay(21), a phase interpolator(23), a level converter(25), a slope detector(29) and a slope controller. The delay(21) generates the delay clock by delaying the input clock to a predetermined time. The phase interpolator(23) interpolates the phase of the delay clock and outputs the interpolated clock. The level converter(25) converts the level of the interpolated clock outputted from the phase interpolator(23) as an output clock. The slope detector(29) generates a predetermined comparison signal by predicting the slope of the delay clock inputted to the phase interpolator(23). And, the slope controller controls the slope of the delay clock in response to the comparison signal.

Description

Delay Locked Loop including phase interpolator having good linearity

TECHNICAL FIELD The present invention relates to a semiconductor device, and more particularly, to a delay-locked loop (hereinafter referred to as a DLL) circuit having a phase interpolator in a semiconductor device and generating an output clock synchronized with an external clock.

1 is a block diagram schematically showing a DLL circuit 10 according to the prior art.

The DLL circuit 10 includes a retarder 11, a phase interpolator 13, and a level converter 15. The delay unit 11 outputs a delay clock DCLK by delaying a received input clock CLK / CLKB for a predetermined time so that coarse locking is performed between the output clock OCLK and the input clock CLK. It plays a role.

The phase interpolator 13 interpolates the phase of the delayed clock DCLK output from the delayer 11 so that fine locking is performed between the output clock OCLK and the input clock CLK. do.

The level converter 15 converts the level of the phase interpolated clock ICLK output from the phase interpolator 13 into a CMOS full-swing level and outputs the output clock to the output clock OCLK. It is a kind.

In order for the phase interpolator 13 to have the best linearity, the signal input to the phase interpolator 13 must have an optimal slope. If the phase interpolator 13 does not have linearity, the phase interval of the clock signal to be interpolated is not constant. For example, when the phase interpolator 13 interpolates two clock signals having a phase difference of '10' in 10 steps, the phase difference between the interpolated clocks should have a uniform phase difference as '1'. However, the phase difference between the interpolated clock signals is not uniform by the nonlinear phase interpolator. If the phase difference between the interpolated clock signals is not uniform, much jitter occurs in the output clock OCLK generated in the DLL circuit.

In the conventional DLL circuit 10, since the phase interpolator 13 receives the delay clock DCLK, which is the output signal of the delay unit 11, as it is, the delay clock input to the phase interpolator 13 according to the change of the process. The slope of (DCLK) also changes.

Therefore, in the DLL circuit 10 according to the related art, since the slope of the signal input to the phase interpolator 13 changes according to the process change, it is difficult to secure the linearity of the phase interpolator 13.

Accordingly, a technical problem of the present invention is to provide a DLL circuit that can reduce clock jitter by making the phase interpolator have high linearity by adjusting the input signal of the phase interpolator to be an optimal slope.

BRIEF DESCRIPTION OF THE DRAWINGS In order to better understand the drawings cited in the detailed description of the invention, a brief description of each drawing is provided.

1 is a block diagram schematically illustrating a delayed synchronization loop (DLL) circuit according to the prior art.

2 is a block diagram schematically illustrating a delayed synchronization loop (DLL) circuit according to an embodiment of the present invention.

3 is a circuit diagram illustrating an example embodiment of the slope detector shown in FIG. 2.

4 is a waveform diagram illustrating a phase interpolation result according to a slope of a delay clock input to the phase interpolator illustrated in FIG. 2.

5 is a diagram illustrating jitter of an output clock of a DLL circuit according to the prior art.

6 is a diagram illustrating jitter of an output clock of a DLL circuit according to an exemplary embodiment of the present invention.

According to an aspect of the present invention, a delay synchronization loop circuit includes: a delayer generating a delay clock (DCLK) by delaying a received input clock by a predetermined time; A phase interpolator for interpolating and outputting a phase of the delay clock; A level converter for converting a level of the phase interpolated clock output from the phase interpolator and outputting the converted level to an output clock (OCLK); A slope detector for predicting a slope of the delay clock DCLK input to the phase interpolator 23 and generating a predetermined comparison signal; And a slope adjuster configured to adjust a slope of the delayed clock in response to the comparison signal.

Preferably, the slope control unit includes a capacitor disposed between a path of the delay clock between the delay unit and the phase interpolator and a ground voltage; And a fuse selectively cut in response to the comparison signal to determine whether the capacitor is connected to the delay clock path.

Also preferably, the slope detector may include: a constant current source formed between a power supply voltage and a predetermined first node to flow a first current amount; One or more test transistors connected in series between the first node N1 and a ground voltage; And a comparator for generating the comparison signal by comparing the voltage of the first node with a predetermined reference voltage.

According to another aspect of the present invention, a delayed synchronization loop circuit including a phase interpolator for interpolating and outputting a phase of a clock signal, and detecting a slope of the clock signal to obtain a comparison signal. Generating a slope detector; And a slope adjuster configured to adjust a slope of the delay clock in response to the comparison signal.

In order to fully understand the present invention, the operational advantages of the present invention, and the objects achieved by the practice of the present invention, reference should be made to the accompanying drawings which illustrate preferred embodiments of the present invention and the contents described in the accompanying drawings.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. Like reference numerals in the drawings denote like elements.

2 is a block diagram illustrating a DLL circuit 20 according to an embodiment of the present invention. Referring to this, the DLL circuit 20 according to an embodiment of the present invention includes a retarder 21, a phase interpolator 23, a level converter 25, a slope detector 27, and a slope adjuster 29. do.

The delayer 21 outputs a delayed clock DCLK by delaying a received input clock CLK for a predetermined time. The delay unit 21 may be implemented in a form in which delay cells having a predetermined unit delay time are connected in series. In the case of a delay implemented with delay cells having a unit delay time, the resolution of the delay time is a unit delay time. As the clock signal input to the delay unit 21, not only the input clock CLK but also its inverted clock CLKB may be used together.

The phase interpolator 23 interpolates the phase of the delayed clock DCLK output from the delayer 21 so that fine locking is performed between the output clock OCLK and the input clock CLK. do. That is, the phase interpolator 23 subdivides the phases of the two delay clocks DCLK having the unit delay time difference so that the output clock OCLK output from the DLL can be finely phase-locked with the input clock CLK. do.

The level converter 25 converts the level of the phase-interpolated clock ICLK output from the phase interpolator 23 to a CMOS full-swing level and outputs it to the output clock OCLK.

The slope detector 27 serves to predict and detect the slope of the delay clock DCLK input to the phase interpolator 23. One embodiment of the slope detector 27 is shown in FIG. 3.

Referring to FIG. 3, the slope detector 27 includes a comparator 291, a constant current source 292, and first and second test transistors NM1 and NM2.

The constant current source 292 is formed between the power supply voltage VDD and the first node N1 to flow a constant current of 'I1'. The first and second test transistors NM1 and NM2 are connected in series between the first node N1 and the ground voltage, and are gated by the power supply voltage VDD to allow a current of 'I2' to flow.

The comparator 291 receives the first node voltage VC as the positive terminal and the reference voltage VREF as the negative terminal, and compares both the voltages VC and VREF to compare the signal CS. Outputs In this embodiment, the reference voltage VREF is at a level 1/2 (VDD / 2) of the power supply voltage.

The test transistors NM1 and NM2 are devices used to find out the process characteristics of the semiconductor device.

The slope detector 29 configured as described above outputs a comparison signal CS having different values according to the process characteristics of the test transistors NM1 and NM2.

If the characteristics of the test transistors NM1 and NM2 are F / F (Fast / Fast), I2 is larger than I1. On the other hand, if the characteristics of the test transistors NM1 and NM2 are S / S (Slow / Slow), there is less I2 than I1. When the characteristics of the test transistors NM1 and NM2 are T / T (Typical / Typical), I1 and I2 are similar.

When I2 is larger than I1, the first node voltage VC is lower than the reference voltage VREF. In this case, the comparator 291 outputs a comparison signal of '10'. When I2 is smaller than I1, the first node voltage VC becomes higher than the reference voltage VREF. In this case, the comparator 291 outputs a comparison signal of '01'. In addition, when I1 and I2 are similar, the first node voltage VC and the reference voltage VREF are substantially the same. In this case, the comparator 291 outputs a comparison signal of '00'.

As a result, the comparator 291 has a value of '10' if the characteristics of the test transistors NM1 and NM2 are F / F, '01' if the characteristics of the test transistors NM1 and NM2 are S / S, and the test transistors NM1 and NM2. If the characteristic of T / T is output the comparison signal of '00'.

If the characteristics of the test transistors NM1 and NM2 are F / F, the slope of the delay clock DCLK is steeper than the desired optimal slope. If the characteristics of the test transistors NM1 and NM2 are S / S, the slope of the delay clock DCLK is Is slower than the desired optimal slope. If the characteristics of the test transistors NM1 and NM2 are T / T, the slope of the delay clock DCLK is predicted to be close to the optimum.

The slope adjusting unit 29 is disposed between the slope retarder 21 and the phase interpolator 23 and adjusts the slope of the delay clock DCLK according to the comparison signal CS output from the slope detector. Do it.

The slope adjusting unit 29 includes first to second fuses FS1 and FS2 and first to second capacitors CP1 and CP2. The first to second capacitors CP1 and CP2 serve as loads to the delay clock DCLK to smooth the slope of the delay clock DCLK. The first to second fuses FS1 and FS2 are selectively cut according to the comparison signal CS, so that the first to second capacitors CP1 and CP2 are input terminals of the phase interpolator 23, that is, a delay clock ( DCLK) is connected to the input path. The first to second capacitors CP1 and CP2 are connected to the input terminal of the phase interpolator 23 to act as a load.

For example, when the first fuse FS1 is electrically disconnected, the first capacitor CP1 does not act as a load, and when the second fuse FS2 is electrically disconnected, the second capacitor CP2 is connected to the load. It doesn't work.

In the present exemplary embodiment, the first to second fuses FS1 and FS2 are not disconnected when the comparison signal CS is '10', and the first fuse FS1 when the comparison signal CS is '00'. ) Is cut and when the comparison signal CS is '01', all of the first to second fuses FS1 and FS2 are cut.

When the first fuse FS1 is blown, the first capacitor CP1 does not act as a load. In this case (this is called the first case), it is assumed that the delay clock DCLK has the most appropriate slope.

When both of the first to second fuses FS1 and FS2 are disconnected, since the first to second capacitors CP1 and CP2 do not act as loads, the slope of the delay clock DCLK becomes faster than in the first case. As described above, the comparison signal CS '01' indicates that the characteristics of the test transistors NM1 and NM2 are S / S, and when the characteristics of the test transistors NM1 and NM2 are S / S, the delay clock The slope of (DCLK) is slower than the desired characteristic. Accordingly, as described above, the first to second capacitors CP1 and CP2 are separated to adjust the slope of the delay clock DCLK to be closer to the optimum slope by making the slope of the delay clock DCLK faster than the original characteristic.

If the first to second fuses FS1 and FS2 are not cut, the slopes of the delay clock DCLK are slower than the first case since both of the first to second capacitors CP1 and CP2 serve as loads. A comparison signal CS of '10' indicates that the characteristics of the test transistors NM1 and NM2 are F / F as described above, and if the characteristics of the test transistors NM1 and NM2 are F / F, the delay clock The slope of (DCLK) is faster than the desired characteristic. Therefore, as described above, the first to second capacitors CP1 and CP2 are connected to adjust the slope of the delay clock DCLK to be closer to the optimum slope by making it slower than the original characteristic.

In the present embodiment, two fuses FS1 and FS2 and two capacitors CP1 and CP2 are used, but the number of fuses and capacitors may be changed. In addition, in the present embodiment, one delay clock path is displayed from the delayer 21 to the phase interpolator 23, but two delayed clocks having a phase difference from the delayer 21 are transferred to the phase interpolator 23. It may be entered. In this case, the slope adjuster 27 shown in Fig. 2 may be provided on each delay clock path between the delayer 21 and the phase interpolator 23, respectively.

4 is a waveform diagram illustrating a phase interpolation result according to a slope of a delay clock input to the phase interpolator illustrated in FIG. 2.

4A illustrates a case where the slope of the delay clock DCLK is very steep, and FIG. 4D illustrates a case where the slope of the delay clock DCLK is optimal. 4 (b) and 4 (c) show another example in which the slope of the delay clock DCLK is steeper than the optimal case. That is, the slope of the delay clock DCLK becomes closer to the optimum slope as the flow goes from FIG. 4 (a) to FIG. 4 (d), and conversely, the slope of the delay clock DCLK goes from FIG. 4 (d) to FIG. 4 (a). The slope has a steep slope.

First, referring to FIG. 4A, when the delay clock DCLK having the steep slope slope is input to the phase interpolator, it is understood that the increasing phase interval is not uniform each time the steps of the phase interpolator increase by one. have. In other words, the phase interpolator has a non-linear characteristic because the phase spacing of the first part and the end of the phase interpolator step is very dense and the center part is wide.

Referring to FIGS. 4B and 4C, as the slope of the delay clock DCLK approaches an optimal slope, the nonlinear characteristics of the phase interpolator decrease, but the phase interval is still not uniform.

Referring to FIG. 4 (d), when the delay clock DCLK having the optimal slope is input to the phase interpolator 23, the phase interval that increases every time the steps of the phase interpolator 23 increases by one is obtained. It can be seen that uniformity. That is, in this case, the phase interpolator 23 has a linear characteristic.

5 is a diagram illustrating jitter of an output clock OCLK of a DLL circuit according to the prior art, and FIG. 6 is a diagram illustrating jitter of an output clock OCLK of a DLL circuit according to an embodiment of the present invention.

Both the DLL circuit according to the prior art and the DLL circuit according to the present invention synchronize the output clock OCLK with the input clock through a coarse locking step and a fine locking step. As described above, coarse locking is performed by the retarders 11 and 21, and fine locking is performed by the phase interpolators 13 and 23. FIG.

In FIG. 5, '52' represents an output clock OCLK in the fine locking step, and '54' represents an output clock OCLK after synchronization is performed. Looking at '54', the jitter of the output clock (OCLK) after synchronization by the DLL circuit according to the prior art is about 70ps.

In FIG. 6, '62' represents an output clock OCLK in the fine locking step, and '64' represents an output clock OCLK after synchronization is performed. Looking at '64', the jitter of the output clock (OCLK) after the synchronization by the DLL circuit according to an embodiment of the present invention is about 45 ~ 50ps.

As is apparent from the enlarged views of '54' and '64', the jitter of the output clock OCLK of the DLL circuit according to an embodiment of the present invention is the jitter of the output clock OCLK of the DLL circuit according to the prior art. It is much smaller than that. The jitter of the output clock represents the phase difference between the output clock OCLK and the input clock CLK after the DLL circuit is synchronized.

Although the present invention has been described with reference to one embodiment shown in the drawings, this is merely exemplary, and those skilled in the art will understand that various modifications and equivalent other embodiments are possible therefrom. Therefore, the true technical protection scope of the present invention will be defined by the technical spirit of the appended claims.

According to the present invention, the phase interpolator has a high linearity by adjusting the clock signal input to the phase interpolator to be an optimal slope. Therefore, the jitter of the output clock of the DLL circuit is reduced.

Claims (8)

A delayer for delaying a received input clock by a predetermined time to generate a delayed clock; A phase interpolator for interpolating and outputting a phase of the delay clock; A level converter for converting a level of the phase interpolated clock output from the phase interpolator and outputting the converted output clock; A slope detector for predicting a slope of a delay clock input to a phase interpolator and generating a predetermined comparison signal; And And a slope adjustment unit for adjusting a slope of the delay clock in response to the comparison signal. The method of claim 1, wherein the slope adjustment unit A capacitor disposed between a path of the delay clock between the delay unit and the phase interpolator and a ground voltage; And And a fuse which is selectively cut in response to the comparison signal to determine whether the capacitor is connected to a path of the delay clock. The method of claim 1, wherein the slope detector A constant current source formed between a power supply voltage and a predetermined first node to flow a first current amount; One or more test transistors connected in series between the first node and a ground voltage; And And a comparator for generating the comparison signal by comparing the voltage of the first node with a predetermined reference voltage. The method of claim 3, wherein the reference voltage is And a half of the power supply voltage. The method of claim 1 wherein the retarder A delay synchronization loop circuit comprising delay cells having a predetermined unit delay time connected in series. A delayed synchronous loop circuit comprising a phase interpolator for interpolating and outputting a phase of a clock signal, A slope detector for detecting a slope of the clock signal to generate a comparison signal; And And a slope adjustment unit for adjusting a slope of the delay clock in response to the comparison signal. The method of claim 6, wherein the slope adjustment unit A capacitor disposed between an input terminal of the phase interpolator and a ground voltage; And And a fuse which is selectively cut in response to the comparison signal to determine whether the capacitor is connected to an input of the phase interpolator. The method of claim 6, wherein the slope detector A constant current source formed between a power supply voltage and a predetermined first node to flow a first current amount; One or more test transistors connected in series between the first node and a ground voltage; And And a comparator for generating the comparison signal by comparing the voltage of the first node with a predetermined reference voltage.