JPH0563461A - Differential amplifier circuit - Google Patents

Abstract

PURPOSE:To provide the differential amplifier circuit capable of preventing the malfunction due to diffusion layer leakage current. CONSTITUTION:In the case of connecting a P-channel MOS type electric field effect transistor(PchM0SFET)Q3 for cutting the power supply between an output terminal OUT and a power supply VDD, the diffusion layer leakage current flows from the first diffusion layer which makes the drain area to the output terminal OUT even when the PchM0SFETQ3 is turned off at the normal operation. Then, a PchMOSFETQ4 having the same characteristic as the PchM0 SFETQ3 is connected between a nodal point 1 and the power supply VDD. Thus, the diffusion layer leakage current flows from the second diffusion layer which makes the drain area of the PchMOSFETQ4 to the nodal point 1, the potential of the nodal point 1 and the potential of the output terminal OUT become equal. Therefore, the generation of the input offset can be prevented, resulting in preventing the malfunction due to the diffusion layer leakage current.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a differential amplifier circuit composed of MOS field effect transistors.

[0002]

2. Description of the Related Art FIG. 3 is a circuit diagram showing a conventional differential amplifier circuit. The load element 3 has one end connected to the power supply V _DD . The N-channel MOS field effect transistor (hereinafter referred to as NchMOSFET) Q ₁ has its drain connected to the other end of the load element 3, its gate connected to the first input terminal (potential V _A ), and its source connected to a node. Connected to 2. The load element 4 has a power source V _DD and an output terminal OUT.
Is connected between and. The NchMOSFET Q ₂ has its drain connected to the output terminal OUT, its gate connected to the second input terminal (potential V _B ), and its source connected to the node 2. P channel MOS type field effect transistor (hereinafter referred to as Pch MOSFET) Q _3
Has its source connected to the power supply V _DD , its gate connected to the standby signal input terminal STB, and its drain connected to the output terminal OUT. The constant current source 5 is connected between the node 2 and the ground GND. The load element 3 and the load element 4, the Nch MOSFET Q ₁ and the Nch
The MOSFET Q ₂ has equivalent characteristics.

In the differential amplifier circuit configured as described above, the potential V _A of the first input terminal and the potential V _A of the first input terminal during normal operation, that is, when the Pch MOSFET Q ₃ for current cutoff is off based on the standby signal. A predetermined output signal is output to the output terminal OUT based on the potential V _B of the second input terminal.

[0004]

However, in the above-described conventional differential amplifier circuit, the Pch during normal operation is used.
A diffusion layer leak current flows from the drain of the MOSFET Q ₃ to the output terminal OUT. On the other hand, Nch MOSFETQ
_The drain current flowing through ₂ does not change because it is determined by its gate voltage. Therefore, the current flowing through the load element 4 decreases. Therefore, in order to pass the same current as the load element 3 to the load element 4, the gate voltage of the Nch MOSFET Q ₂ must be lowered. In this case, there is a problem that an input offset occurs and the differential amplifier circuit malfunctions.

For example, in FIG. 3, PchMOSFE
Considering that the diffusion layer leak current I ₃ of 0.1 μA flows from the drain of TQ ₃ to the output terminal OUT, the current flowing to the constant current source 5 is set to 2 μA when the drivability of the constant current source 5 is low at high temperature, If the load of the load elements 3 and 4 is set to 1.5 MΩ, an input offset of about 10 mV occurs to bring the drain of the Nch MOSFET Q ₁ and the output terminal OUT to the same potential, which causes a malfunction of the differential amplifier circuit. ing.

The present invention has been made in view of the above problems, and an object of the present invention is to provide a differential amplifier circuit which can prevent malfunction due to a diffusion layer leak current.

[0007]

A differential amplifier circuit according to the present invention includes a first amplifier connected between a first power supply and a first node.
A load element, a first conductivity type first MOS field effect transistor having a drain connected to the first node, a gate connected to a first input terminal, and a source connected to a second node. A second load element connected between the first power supply and the output terminal; a drain connected to the output terminal, a gate connected to the second input terminal and a source connected to the second
A second MOS type field effect transistor of the first conductivity type connected to the node, a first diffusion layer connected to the output terminal, and a second diffusion layer connected to the first node. ,
A constant current source connected between the second node and a second power source.

[0008]

In the present invention, the first and second load elements,
A differential amplifier circuit is configured by the first and second MOSFETs and a constant current source, and a predetermined output signal is output to the output terminal based on the potential of the first input terminal and the potential of the second input terminal. It Here, MOSFET for current cut
Is connected to the output terminal, a diffusion layer leakage current flows from the first diffusion layer forming the drain region to the output terminal even when the current cutting MOSFET is in the off state during normal operation. Therefore, a second diffusion layer having a characteristic equivalent to that of the first diffusion layer is connected to the first node. As a result, a diffusion layer leak current flows from the second diffusion layer to the first node, so that the potential of the first node becomes equal to the potential of the output terminal. Therefore, it is possible to prevent the occurrence of the input offset and prevent the malfunction due to the diffusion layer leak current.

[0009]

Embodiments of the present invention will now be described with reference to the accompanying drawings.

FIG. 1 is a circuit diagram showing a differential amplifier circuit according to a first embodiment of the present invention. The load element 3 is connected between the power source V _DD and the node 1. Nch MOSFET Q ₁
Has its drain connected to node 1 and its gate
Is connected to the input terminal (potential V _A ) and the source thereof is connected to the node 2. The load element 4 is connected between the power source V _DD and the output terminal OUT. Nch MOSFETQ
The drain of ₂ is connected to the output terminal OUT, its gate is connected to the second input terminal (potential V _B ), and its source is connected to the node 2. Pch MOSFETQ
₃ , the source is connected to the power supply V _DD , the gate is connected to the standby signal input terminal STB, and the drain is connected to the output terminal OUT. PchMOSF
ETQ ₄ has its source connected to the power supply V _DD , its gate connected to the standby signal input terminal STB, and its drain connected to the node 1. NchMOSFE
The source of TQ ₅ is connected to the ground GND, the gate thereof is connected to the third input terminal (potential V _C ), and the drain thereof is connected to the node 2. NchMOSF
ETQ ₅ is a constant current source driven in the saturation region based on the potential V _C. In addition, load element 3 and load element 4, NchM
OSFET Q ₁ , Nch MOSFET Q ₂ and PchM
The OSFET Q ₃ and the Pch MOSFET Q ₄ have equivalent characteristics.

In the differential amplifier circuit configured as described above, the potential V _A of the first input terminal and the potential V _A of the first input terminal during the normal operation, that is, when the Pch MOSFET Q ₃ for cutting the current based on the standby signal is in the off state. A predetermined output signal is output to the output terminal OUT based on the potential V _B of the second input terminal.

In this embodiment, Pch MOSFET
Output terminal OU from the drain region of Q ₃ (first diffusion layer)
Assuming that the diffusion layer leak current flowing into T is I ₃ , Pch
By connecting PchMOSFET Q ₄ which has characteristics completely equivalent to MOSFET Q ₃ symmetrically,
Drain region of chMOSFET Q ₄ (second diffusion layer)
Diffusion layer leak current I ₄ flowing from node 1 to node 1 is equal to diffusion layer leak current I ₃ . Therefore, NchMOSF
If the gate potentials V _A and V _B of ETQ ₁ and Q ₂ are made equal, the respective drain currents I ₁ and I ₂ become equal. Moreover, since the load elements 3 and 4 have equivalent characteristics, the currents I ₃ −I ₂ and I ₄ −I ₁ flowing through the load elements 3 and ₄ are equal, and the potential of the node 1 and the output terminal OUT are equal. It becomes equal to the electric potential. As a result, the occurrence of input offset can be prevented, and malfunction due to the diffusion layer leakage current can be prevented.

FIG. 2 is a plan view showing a differential amplifier circuit according to the second embodiment of the present invention. In this embodiment, the Pch MOSFET Q ₄ in the first embodiment is replaced by the P-type semiconductor region 6 and laid out, so that the description will be given with reference to FIG. The resistor 7 as the load element 3 and the resistor 8 as the load element 4 are connected between the power source V _DD and the node 1 and the output terminal OUT, respectively. NchMOSF
N-type semiconductor region 10 forming ETQ ₁ and Q ₂ has a node 1
, And the output terminal OUT and the node 2 are commonly connected and provided on the N-type semiconductor region 10.
The potentials V _A and V _B are applied to the gates of the SFETs Q ₁ and Q ₂ , respectively. The P-type semiconductor region 9 forming the Pch MOSFET Q ₃ is connected between the power supply V _DD and the output terminal OUT, and the gate provided on the P-type semiconductor region 9 is connected to the input terminal STB. P-type semiconductor region 6
Are connected to node 1. The N-type semiconductor region 11 forming the NchMOSFET Q ₅ is connected between the node 2 and the ground GND, and the potential V _C is applied to the gate of the NchMOSFET Q ₅ provided on the N-type semiconductor region 11. .. In this case, the P-type semiconductor region 6 and the drain region of the P-type semiconductor region 9 have equivalent characteristics, and the two drain regions of the N-type semiconductor region 10 have equivalent characteristics.

According to this embodiment, as in the first embodiment, the diffusion layer leak current flowing from the P-type semiconductor region 6 to the node 1 and the diffusion flowing from the drain region of the P-type semiconductor region 9 to the output terminal OUT. By making the layer leak current equal, it is possible to prevent the occurrence of an input offset and prevent malfunction due to the diffusion layer leak current.

[0015]

As described above, according to the present invention, the second diffusion layer having characteristics equivalent to those of the first diffusion layer connected to the output terminal is connected to the first node, and the first diffusion layer is connected to the first node. Since the diffusion layer leak current flowing from the diffusion layer and the diffusion layer leak current flowing from the second diffusion layer are equalized, the occurrence of the input offset can be prevented, and the malfunction due to the diffusion layer leakage current can be prevented. it can.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a differential amplifier circuit according to a first embodiment of the present invention.

FIG. 2 is a plan view showing a differential amplifier circuit according to a second embodiment of the present invention.

FIG. 3 is a circuit diagram showing a conventional differential amplifier circuit.

[Explanation of symbols]

1, 2; Nodes 3, 4; Load element 5; Constant current source 6, 9; P-type semiconductor region 7, 8; Resistor 10, 11; N-type semiconductor region Q ₁ , Q ₂ , Q ₅ ; Nch MOSFET Q ₃ , Q ₄ ; Pch MOSFET OUT; Output terminal

Claims (1)

[Claims] 1. A first load element connected between a first power source and a first node; a drain connected to the first node; a gate connected to a first input terminal; and a source connected to the first input terminal. Second
A first conductivity type first MOS field effect transistor connected to the node, a second load element connected between the first power source and the output terminal, and a drain connected to the output terminal A second MOS of a first conductivity type having a gate connected to a second input terminal and a source connected to the second node
-Type field effect transistor, a first diffusion layer connected to the output terminal, a second diffusion layer connected to the first node, and between the second node and a second power supply A differential amplifier circuit having a connected constant current source.