JPH0563184A - Rectifying semiconductor device - Google Patents

Rectifying semiconductor device

Info

Publication number
JPH0563184A
JPH0563184A JP25053191A JP25053191A JPH0563184A JP H0563184 A JPH0563184 A JP H0563184A JP 25053191 A JP25053191 A JP 25053191A JP 25053191 A JP25053191 A JP 25053191A JP H0563184 A JPH0563184 A JP H0563184A
Authority
JP
Japan
Prior art keywords
conductivity type
type semiconductor
depletion layer
schottky contact
layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP25053191A
Other languages
Japanese (ja)
Other versions
JP3076638B2 (en
Inventor
Masaru Wakatabe
勝 若田部
Takashi Suga
孝 菅
Shinji Kuri
伸治 九里
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shindengen Electric Manufacturing Co Ltd
Original Assignee
Shindengen Electric Manufacturing Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
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Application filed by Shindengen Electric Manufacturing Co Ltd filed Critical Shindengen Electric Manufacturing Co Ltd
Priority to JP25053191A priority Critical patent/JP3076638B2/en
Publication of JPH0563184A publication Critical patent/JPH0563184A/en
Application granted granted Critical
Publication of JP3076638B2 publication Critical patent/JP3076638B2/en
Anticipated expiration legal-status Critical
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Links

Abstract

PURPOSE:To obtain a rectifying semiconductor device having a high efficiency and a high speed by holding an electron potential in the reverse characteristic high without increasing a channel series resistance of forward characteristics and eliminating voltage dependency of a reverse leakage current. CONSTITUTION:A Schottky contact surface (e) is formed on the upper surface of a protrusion on the surface of a one conductivity type semiconductor formed with trench grooves 8, an opposite conductivity type semiconductor 5 is formed in the bottom of the groove, and an insulator layer is formed on the sidewall of a protrusion. The semiconductor 5 and a Schottky contact metal layer are electrically connected to the same potential, and so constituted that at least two depleted layers 12, 13 at the time of zero voltage bias are not connected.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、整流用半導体装置の構
造に関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to the structure of a rectifying semiconductor device.

【0002】[0002]

【従来の技術】従来、高効率の整流用半導体装置とし
て、例えば、本発明者等による特願平3−115341
「ショットキバリア半導体装置」がある。それは図1の
断面構造図に示すものであり、1は低抵抗の一導電型半
導体(例えば、N+)、2は一導電型半導体(例えば、
N)、3は逆導電型半導体(例えば、P+)のガ−ドリ
ング領域、4は絶縁膜、5は逆導電型半導体(例えば、
P+)、6はショットキ接触をする金属層、7はオ−ミ
ック電極、8はトレンチ溝の凹部、9は一導電型半導体
内のチャネル、11は空乏層領域である。
2. Description of the Related Art Conventionally, as a highly efficient rectifying semiconductor device, for example, Japanese Patent Application No. 3-115341 filed by the present inventors.
There is a “Schottky barrier semiconductor device”. It is shown in the cross-sectional structure diagram of FIG. 1, where 1 is a low resistance one conductivity type semiconductor (eg N +), 2 is a one conductivity type semiconductor (eg
N), 3 is a guarding region of a reverse conductivity type semiconductor (for example, P +), 4 is an insulating film, and 5 is a reverse conductivity type semiconductor (for example, P +).
P +), 6 is a metal layer in Schottky contact, 7 is an ohmic electrode, 8 is a recess of a trench groove, 9 is a channel in a semiconductor of one conductivity type, and 11 is a depletion layer region.

【0003】図1の整流用半導体装置の順方向特性につ
いて説明する。Aをアノ−ド、Cをカソ−ドとして、零
電圧バイアスにすると、相対面する逆導電型半導体5の
距離WN、深さD、角度θ(零電圧バイアス時に延びる
空乏層の深さWbi(2)の位置における逆導電型半導体
5と一導電型半導体2の境界での接線が接触面eとの間
に形成する角度)を適切に選ぶことにより、チャネル9
内に電子エネルギ−ポテンシアルの丘を形成する。この
ポテンシアルの丘の最大高さが、金属層6によるショッ
トキ接触バリアの高さよりも低い内は順方向特性はその
バリア高さ(φB)で決定されるが、高くなると順方向
電圧降下はその金属ショットキバリア高さで決まるVF
値より大きなVF値となる。
The forward characteristic of the rectifying semiconductor device of FIG. 1 will be described. When A is an anode and C is a cathode and a zero voltage bias is applied, the distance WN, the depth D, and the angle .theta. Of the opposite conductivity type semiconductors 5 facing each other (the depth Wbi of the depletion layer extending at the zero voltage bias ( By appropriately selecting the angle formed by the tangent line at the boundary between the opposite conductivity type semiconductor 5 and the one conductivity type semiconductor 2 at the position 2) between the contact surface e),
To form electron energy-potential hills. As long as the maximum height of this potential hill is lower than the height of the Schottky contact barrier formed by the metal layer 6, the forward characteristic is determined by the barrier height (φB). VF determined by Schottky barrier height
The VF value is larger than the value.

【0004】一方、ショットキ接触バリアの逆漏れ電流
JRの公知の式は JR=JS・exp{(q/kT)(qE/4πE)1/2} で示され、電界強度E=0のときJR=JSとなり、最小
となる。又、逆方向電圧を大きくしてもJRはほぼ一定
の値となる。ただし、JSは飽和電流である。しかし
て、図2(a)は従来構造の電子ポテンシアル分布図で
あり、チャネル9の中央部におけるアノ−ドA、カソ−
ドC間の電子ポテンシアル分布を示している。即ち、シ
ョットキ接触バリア付近のポテンシアル勾配は大きく、
逆方向電圧の増加につれて少しづつポテンシアルを下げ
る。特に、逆導電型半導体5の深さDが浅く、チャネル
幅WNが広く、角度θが大であるとこの傾向は強まる。
On the other hand, a well-known formula for the reverse leakage current JR of the Schottky contact barrier is given by JR = JS · exp {(q / kT) (qE / 4πE) 1/2}, and when the electric field strength E = 0, JR = JS, which is the minimum. Further, even if the reverse voltage is increased, JR has a substantially constant value. However, JS is a saturation current. 2 (a) is an electron potential distribution map of the conventional structure, in which the anode A and cathode in the central part of the channel 9 are shown.
The electron potential distribution between C is shown. That is, the potential gradient near the Schottky contact barrier is large,
The potential gradually decreases as the reverse voltage increases. Particularly, when the depth D of the opposite conductivity type semiconductor 5 is shallow, the channel width WN is wide, and the angle θ is large, this tendency is intensified.

【0005】従って、図5のJR−VR(逆漏れ電流−逆
方向電圧)特性の「従来構造」の曲線で示すように、逆
漏れ電流は電圧に依存して少しづつ増加する。
Therefore, as shown by the curve of "conventional structure" of the JR-VR (reverse leakage current-reverse voltage) characteristic of FIG. 5, the reverse leakage current gradually increases depending on the voltage.

【0006】本発明者等は、逆方向に高い電圧印加があ
っても、高いポテンシアルを維持し、逆漏れ電流の電圧
依存性を最小とする構造として、平成3年7月18日、特
許出願「整流用半導体装置」を発明した。しかして、前
記せる特願平3−115341を含めて、従来提案した
構造では、零電圧バイアス時に形成する最高ポテンシア
ルを高電圧下でも保持しようとする深さDを極めて深く
する必要がある。又、順方向特性としては、チャネルシ
リ−ズ抵抗が増大する等、順方向電圧降下を大きくする
欠点がある。(3)
The inventors of the present invention filed a patent application on July 18, 1991 as a structure for maintaining a high potential even when a high voltage is applied in the reverse direction and minimizing the voltage dependence of the reverse leakage current. Invented "rectifying semiconductor device". Therefore, in the structure proposed hitherto, including the above-mentioned Japanese Patent Application No. 3-115341, it is necessary to make the depth D extremely deep so as to maintain the maximum potential formed at the time of zero voltage bias even under a high voltage. Further, as the forward characteristic, there is a defect that the forward voltage drop is increased such that the channel series resistance is increased. (3)

【0007】[0007]

【発明の目的】複数のトレンチ溝を設けた一導電型半導
体表面の凸部上面にショットキ接触をする金属層を形成
した整流用半導体装置において、順方向特性のチャネル
シリ−ズ抵抗を増加させることなく、かつ、逆方向特性
における電子ポテンシアルを高く保持し、逆漏れ電流の
電圧依存性をなくして、高効率、高速の整流用半導体装
置を得ることを目的とする。
An object of the present invention is to increase the channel series resistance of the forward characteristic in a rectifying semiconductor device in which a metal layer in Schottky contact is formed on the upper surface of a convex portion of the surface of one conductivity type semiconductor having a plurality of trench grooves. It is an object of the present invention to obtain a high-efficiency and high-speed rectifying semiconductor device that does not have a high electron potential in the reverse direction characteristic and eliminates the voltage dependence of the reverse leakage current.

【0008】[0008]

【実施例】図3は、本発明装置の1実施例の断面構造図
であって、同一符号は同一部分をあらわす。又、10は
絶縁物層、12は一導電型半導体2側にのびるショット
キ接触面eからの第1の空乏層、13は2側にのびる逆
導電型半導体領域5からの第2の空乏層である。なお、
12、13は、アノ−ドA、カソ−ドCを零電圧バイア
スとした時の空乏層である。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 3 is a sectional structural view of an embodiment of the device of the present invention, and the same reference numerals represent the same parts. Further, 10 is an insulator layer, 12 is a first depletion layer from the Schottky contact surface e extending to the one conductivity type semiconductor 2 side, and 13 is a second depletion layer from the opposite conductivity type semiconductor region 5 extending to the 2 side. is there. In addition,
Reference numerals 12 and 13 are depletion layers when the anode A and the cathode C are set to a zero voltage bias.

【0009】本発明の特徴とする構造は、トレンチ溝8
を設けた一導電型半導体2表面の凸部上面にショットキ
接触面eを形成し、凹部底部に逆導電型半導体5を形成
し、又、凸部側壁部に絶縁物層10を形成するように構
成し、5とショットキ接触面eを形成する金属層6を同
電位に電気接続し、更に、第1の空乏層12と第2の空
乏層13が少なくとも零電圧バイアス時にはつながらな
いように構成することである。
A feature of the present invention is that the trench groove 8
The Schottky contact surface e is formed on the upper surface of the convex portion of the surface of the one-conductivity-type semiconductor 2 provided with, the reverse conductivity type semiconductor 5 is formed on the bottom of the concave portion, and the insulator layer 10 is formed on the side wall of the convex portion. And 5 and the metal layer 6 forming the Schottky contact surface e are electrically connected to the same potential, and further, the first depletion layer 12 and the second depletion layer 13 are not connected at least at a zero voltage bias. Is.

【0010】次に、図3の本発明装置の具体的な製作例
を述べる。高抵抗N型シリコン2に3Ωcm 6μmエ
ピタキシアルウエハを使用し、トレンチ溝8、深さ3μ
m、幅1μmのほぼ垂直溝形状を形成した凸部の幅は
1.8μmとした。公知のイオン注入法にてボロン原子
を加速電圧40keV、ド−ズ 1×1015原子で垂直
に打込み、その後、950℃で活性化熱処理することに
より、約0.5〜0.8μm深さ、表面濃度 5〜10×
1018原子/cm3のP+領(4)域5をトレンチ溝8底
部に形成した。次に、凹部トレンチ溝8内面に、酸水素
炎によるパイロジェニックスチ−ム酸化膜SiO210
を約2000オングストロ−ム形成した。ホトレジスト
を塗布し、トレンチ溝8を埋めつくし、凸部上面にごく
薄い3000オングストロ−ム以下のレジストしか残ら
ないようにして、凹部酸化膜10を保護しておく。次
に、RF−REACTIVE ION ETCHERの
約2KW出力でCF4ガスと少量のO2ガスで60秒エッ
チングすると、凸部上面の薄いホトレジスト膜とSiO
2膜は除去される。同様に凹部底面の薄いSiO2膜も、
垂直イオンシャワ−によりエッチング除去し、P+層を露
出させる。次に、チタンショットキ−金属膜6をプラネタ
リ−型真空蒸着装置を用いて、約2000オングストロ
−ム厚さにトレンチ溝8の底面、側面にも形成し、凸部
上面高抵抗N型シリコン2とはショットキ接触面eを形
成する。
Next, a specific production example of the device of the present invention shown in FIG. 3 will be described. 3Ωcm 6μm epitaxial wafer is used for high resistance N type silicon 2, trench groove 8, depth 3μ
The width of the protrusion having a vertical groove shape of m and a width of 1 μm was 1.8 μm. Boron atoms are vertically implanted at a accelerating voltage of 40 keV and a dose of 1 × 10 15 atoms by a known ion implantation method, and then activation heat treatment is performed at 950 ° C. to obtain a surface depth of about 0.5 to 0.8 μm. Concentration 5-10x
A P + region (4) 5 of 10 18 atoms / cm 3 was formed at the bottom of the trench groove 8. Next, a pyrogenic steam oxide film SiO210 formed by an oxyhydrogen flame is formed on the inner surface of the concave trench groove 8.
Of about 2000 angstroms. A photoresist is applied to fill the trench groove 8 so that only a thin resist of 3000 angstroms or less remains on the upper surface of the convex portion to protect the concave oxide film 10. Then, an RF-REACTIVE ION ETCHER output of about 2 KW was used to etch for 60 seconds with CF4 gas and a small amount of O2 gas to form a thin photoresist film and SiO on the upper surface of the convex portion.
2 Membrane is removed. Similarly, the thin SiO2 film on the bottom of the recess is
The P + layer is exposed by etching away with a vertical ion shower. Next, a titanium Schottky metal film 6 is formed on the bottom surface and the side surface of the trench groove 8 to a thickness of about 2000 angstroms by using a planetary-type vacuum vapor deposition device, and the upper surface of the convex portion is formed of the high resistance N-type silicon 2. Forms a Schottky contact surface e.

【0011】以上により得られた本発明装置は電子ポテ
ンシアル分布図を図2(b)に示し、又、電気特性とし
てJR−VR(逆漏れ電流−逆方向電圧)特性図4及びJ
F−VF(順方向電流−順方向電圧)特性図5「本発明構
造」と図示するように改善されている。
The device of the present invention obtained as described above shows an electronic potential distribution chart in FIG. 2 (b), and also has JR-VR (reverse leakage current-reverse voltage) characteristic charts 4 and J as electric characteristics.
F-VF (Forward current-Forward voltage) characteristic This is improved as shown in FIG.

【0012】更に、図1の従来構造と図3の本発明構造
を空乏層領域の対比により説明する。図1の従来構造で
は零電圧バイアス時において、ショットキ接触面eとP
+層5接合から空乏層が伸びると、凸部上面と側面の角
の部分で、ショットキ接触接合の狭い空乏層とP+/N
接合の広い空乏層が接している。それにより、フェルミ
レベルを合わせるために、接合部の高抵抗N層2中の電
荷がはき出され、電荷中性条件を満たす距離まで空乏化
するが、この時、前記した狭い空乏層と広い空乏層がほ
とんど直交して連続性を保ち、ショットキ金属層6とP
+層5が同電位になっている条件下では、さらに各接合
がそれぞれの中性条件を満たすために空乏化した幅より
も、なおかつ、隣り合う空乏化領域間に電荷の再配置化
が起り、狭い空乏層はやや広い空乏層に、(5)又、広
い空乏層はやや狭い空乏層に変化する。特に、前記の角
の部分では、直交する電界ベクトルが重なり合うため、
合成ベクトルは大きくなり、空乏化の幅はさらに広くな
る。すなわち、P+/N接合の空乏層幅は、低いショッ
トキ接触接合の狭い空乏層に影響されて、狭くなってし
まう欠点がある。空乏層領域は電子ポテンシアルが高め
られている領域であるから、チャネル9中央部に高いポ
テンシアルを形成するには、チャネル幅WNを狭くする
ばかりでなく、P+/N接合から各々伸びる空乏層の広
さを広くすることも、高いポテンシアルの丘を高電圧化
でも保持するためには有効であるから、図1の従来構造
のように、ショットキ接触接合の空乏層とP+/N接合
の空乏層が空乏層領域11のごとく連結していること
は、P+/N接合ではさまれたチャネル9領域に高いポ
テンシアルを保持しようとする目的に対しては最適構造
ではない。
Further, the conventional structure of FIG. 1 and the structure of the present invention of FIG. 3 will be described by comparing the depletion layer regions. In the conventional structure of FIG. 1, when the zero voltage bias is applied, the Schottky contact surfaces e and P
When the depletion layer extends from the + layer 5 junction, P + / N and the narrow depletion layer of the Schottky contact junction are formed at the corners of the upper surface and the side surface of the convex portion.
A depletion layer with a wide junction is in contact. As a result, in order to match the Fermi level, the charges in the high resistance N layer 2 at the junction are ejected and depleted to a distance satisfying the charge neutrality condition. At this time, the narrow depletion layer and the wide depletion layer are Are almost orthogonal to each other and maintain continuity, and the Schottky metal layer 6 and P
Under the condition that the + layer 5 is at the same potential, charge rearrangement occurs more than the width depleted to satisfy the neutral condition of each junction and between the adjacent depleted regions. The narrow depletion layer changes to a slightly wide depletion layer, and (5) the wide depletion layer changes to a slightly narrow depletion layer. In particular, at the corners, because the electric field vectors that intersect at right angles overlap,
The composite vector becomes larger and the depletion becomes wider. That is, the width of the depletion layer of the P + / N junction is affected by the narrow depletion layer of the low Schottky contact junction and becomes narrow. Since the depletion layer region has a high electron potential, in order to form a high potential in the central portion of the channel 9, not only the channel width WN is narrowed but also the depletion layer extending from the P + / N junction is formed. Since increasing the width is also effective for maintaining high potential hills even at high voltage, the depletion layer of the Schottky contact junction and the depletion of the P + / N junction as in the conventional structure of FIG. The fact that the layers are connected like the depletion layer region 11 is not an optimum structure for the purpose of maintaining a high potential in the channel 9 region sandwiched by the P + / N junctions.

【0013】一方、図3の本発明構造では、ショットキ
接触接合からの空乏層12と、P+/N接合からの空乏層
13が少なくとも、零電圧バイアス時に互に接しないよ
うにしているから、それら接合が独自に有する条件を満
たす空乏層がそれぞれに発達し、P+/N接合からのび
る空乏層は従来構造のように狭くならずチャネル9の電
子ポテンシアルは、図2(b)のごとく、図2(a)に
比し高いポテンシアルとなり改善される。又、逆バイア
ス電圧がアノ−ドA、カソ−ドC間に印加されても、前
記現象は同じであるから、逆電圧バイアス時の高いポテ
ンシアルを保持する能力は高まる。
On the other hand, in the structure of the present invention shown in FIG. 3, the depletion layer 12 from the Schottky contact junction and the depletion layer 13 from the P + / N junction are arranged so as not to contact each other at the zero voltage bias. A depletion layer that satisfies the conditions unique to each of these junctions develops, and the depletion layer extending from the P + / N junction does not become narrow as in the conventional structure, and the electron potential of the channel 9 is as shown in FIG. 2 (b). The potential is higher than that in FIG. 2A, which is improved. Further, even if a reverse bias voltage is applied between the anode A and the cathode C, the above phenomenon is the same, so that the ability to hold a high potential at the time of reverse voltage bias is enhanced.

【0014】又、図3の本発明構造では、凸部側壁部に
絶縁物層10を形成しているので、絶縁物層10ではさ
まれたチャネル9には空乏層が発達しない。従って、順
電圧バイアス時のチャネル電流は、従来構造のように順
方向空乏層での電流路制限がなく、幅広い電流路を確保
できるため、順方向電圧に対するチャネルシリ−ズ抵抗
が小となり順方向特性においても大幅な改善を達成し
た。
In the structure of the present invention shown in FIG. 3, since the insulator layer 10 is formed on the side wall of the convex portion, the depletion layer does not develop in the channel 9 sandwiched by the insulator layer 10. Therefore, the channel current during forward voltage bias does not have the current path limitation in the forward depletion layer unlike the conventional structure, and a wide current path can be secured, so the channel series resistance against the forward voltage becomes small and the forward direction is reduced. Significant improvement was also achieved in the characteristics.

【0015】(6)前記せる本発明の実施例について
は、本発明の要旨の範囲で種々の変形、付加、変換等の
変更をなし得るものである。例えば、凸部の機械的破損
を防止するため、凹部を適当な固体材料層で充填するこ
とも可能である。
(6) The above-described embodiment of the present invention can be modified, modified, changed, etc. within the scope of the present invention. For example, the depressions can be filled with a suitable layer of solid material to prevent mechanical damage to the elevations.

【0016】[0016]

【発明の効果】以上説明したように本発明により、順方
向において、チャネルシリ−ズ抵抗を増加させることな
く、逆方向において電子ポテンシアルを高く保持し、か
つ、逆漏れ電流の電圧依存性をなくして、高効率、高速
の整流用半導体装置を得ることが可能となり、電源機器
をはじめ、広い範囲に利用でき、産業上の効果、極めて
大なるものである。
As described above, according to the present invention, the electron potential is kept high in the reverse direction without increasing the channel series resistance in the forward direction, and the voltage dependence of the reverse leakage current is eliminated. As a result, it is possible to obtain a high-efficiency and high-speed rectifying semiconductor device, which can be used in a wide range including power supply devices, and the industrial effect is extremely great.

【図面の簡単な説明】[Brief description of drawings]

【図1】従来の整流用半導体装置の断面構造図である。FIG. 1 is a sectional structural view of a conventional rectifying semiconductor device.

【図2】電子ポテンシアル分布図で、(a)は従来構造
のもの、(b)は本発明構造のものである。
2A and 2B are electron potential distribution charts, where FIG. 2A shows a conventional structure and FIG. 2B shows a structure of the present invention.

【図3】本発明の1実施例の断面構造図である。FIG. 3 is a sectional structural view of one embodiment of the present invention.

【図4】JR−VR(逆漏れ電流−逆方向電圧)特性図で
ある。
FIG. 4 is a JR-VR (reverse leakage current-reverse voltage) characteristic diagram.

【図5】JF−VF(順方向電流−順方向電圧)特性図で
ある。
FIG. 5 is a JF-VF (forward current-forward voltage) characteristic diagram.

【符号の説明】[Explanation of symbols]

1 低抵抗の一導電型半導体(例えばN+) 2 一導電型半導体(例えば、N) 3 ガ−ドリング領域 4 絶縁膜 5 逆導電型半導体(例えばP+) (7)6 金属層 7 オ−ミック電極 8 トレンチ溝の凹部 9 チャネル 10 絶縁物層 11 空乏層領域 12 第1の空乏層 13 第2の空乏層 A アノ−ド C カソ−ド e ショットキ接触面 θ 角度 D 深さ 1 low resistance one conductivity type semiconductor (eg N +) 2 one conductivity type semiconductor (eg N) 3 guarding region 4 insulating film 5 reverse conductivity type semiconductor (eg P +) (7) 6 metal layer 7 oh Mic electrode 8 Recess of trench groove 9 Channel 10 Insulator layer 11 Depletion layer region 12 First depletion layer 13 Second depletion layer A Anode C Cathode e Schottky contact surface θ angle D depth

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】 複数のトレンチ溝を設けた一導電型半導
体表面の凸部上面にショットキ接触をする金属層を形成
し、凹部底部に逆導電型半導体領域を形成した整流用半
導体装置において、凸部側壁部に絶縁物層を形成し、か
つ、逆導電型半導体領域と凸部上面の金属層を同電位に
電気接続し、該金属層をアノ−ド、前記一導電型半導体
をカソ−ドとした少なくとも零電圧バイアス時に、前記
一導電型半導体側にのびる前記逆導電型半導体領域から
の空乏層と前記凸部上面のショットキ接触からの空乏層
がつながらないように構成したことを特徴とする整流用
半導体装置。
1. A rectifying semiconductor device in which a metal layer in Schottky contact is formed on the upper surface of a projection of a surface of one conductivity type semiconductor having a plurality of trench grooves, and a reverse conductivity type semiconductor region is formed on the bottom of the recess. An insulating layer is formed on the side wall portion, and the opposite conductivity type semiconductor region and the metal layer on the upper surface of the convex portion are electrically connected to the same potential, the metal layer is an anode, and the one conductivity type semiconductor is a cathode. The rectification is characterized in that the depletion layer from the opposite conductivity type semiconductor region extending to the one conductivity type semiconductor side and the depletion layer from the Schottky contact on the upper surface of the convex portion are not connected at least at the time of zero voltage bias. Semiconductor device.
JP25053191A 1991-09-03 1991-09-03 Rectifier semiconductor device Expired - Fee Related JP3076638B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP25053191A JP3076638B2 (en) 1991-09-03 1991-09-03 Rectifier semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP25053191A JP3076638B2 (en) 1991-09-03 1991-09-03 Rectifier semiconductor device

Publications (2)

Publication Number Publication Date
JPH0563184A true JPH0563184A (en) 1993-03-12
JP3076638B2 JP3076638B2 (en) 2000-08-14

Family

ID=17209286

Family Applications (1)

Application Number Title Priority Date Filing Date
JP25053191A Expired - Fee Related JP3076638B2 (en) 1991-09-03 1991-09-03 Rectifier semiconductor device

Country Status (1)

Country Link
JP (1) JP3076638B2 (en)

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1022843A3 (en) * 1999-01-19 2001-01-31 Rockwell Science Center, LLC High power rectifier
JP2001077379A (en) * 1999-09-03 2001-03-23 Nippon Inter Electronics Corp Schottky barrier semiconductor device
JP2002083976A (en) * 2000-06-21 2002-03-22 Fuji Electric Co Ltd Semiconductor device
US6670650B2 (en) 2001-08-02 2003-12-30 Fuji Electric Co., Ltd. Power semiconductor rectifier with ring-shaped trenches
US6979874B2 (en) 1997-06-18 2005-12-27 Mitsubishi Denki Kabushiki Kaisha Semiconductor device and method of manufacturing thereof
JP2008519447A (en) * 2004-11-08 2008-06-05 ローベルト ボツシユ ゲゼルシヤフト ミツト ベシユレンクテル ハフツング Semiconductor device and use or manufacturing method thereof
JP2008523596A (en) * 2004-12-10 2008-07-03 ローベルト ボツシユ ゲゼルシヤフト ミツト ベシユレンクテル ハフツング Semiconductor device and manufacturing method of semiconductor device
CN103943666A (en) * 2013-01-17 2014-07-23 朱江 Grooved semiconductor device and manufacturing method thereof
CN112420851A (en) * 2019-08-20 2021-02-26 株式会社东芝 Semiconductor device with a plurality of semiconductor chips
CN113851525A (en) * 2021-09-18 2021-12-28 中山大学 GaN-based groove metal oxide Schottky barrier diode and preparation method thereof

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6979874B2 (en) 1997-06-18 2005-12-27 Mitsubishi Denki Kabushiki Kaisha Semiconductor device and method of manufacturing thereof
EP1022843A3 (en) * 1999-01-19 2001-01-31 Rockwell Science Center, LLC High power rectifier
JP2001077379A (en) * 1999-09-03 2001-03-23 Nippon Inter Electronics Corp Schottky barrier semiconductor device
JP2002083976A (en) * 2000-06-21 2002-03-22 Fuji Electric Co Ltd Semiconductor device
US6670650B2 (en) 2001-08-02 2003-12-30 Fuji Electric Co., Ltd. Power semiconductor rectifier with ring-shaped trenches
JP2008519447A (en) * 2004-11-08 2008-06-05 ローベルト ボツシユ ゲゼルシヤフト ミツト ベシユレンクテル ハフツング Semiconductor device and use or manufacturing method thereof
JP2008523596A (en) * 2004-12-10 2008-07-03 ローベルト ボツシユ ゲゼルシヤフト ミツト ベシユレンクテル ハフツング Semiconductor device and manufacturing method of semiconductor device
CN103943666A (en) * 2013-01-17 2014-07-23 朱江 Grooved semiconductor device and manufacturing method thereof
CN112420851A (en) * 2019-08-20 2021-02-26 株式会社东芝 Semiconductor device with a plurality of semiconductor chips
CN113851525A (en) * 2021-09-18 2021-12-28 中山大学 GaN-based groove metal oxide Schottky barrier diode and preparation method thereof

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