JP2007088342A - Semiconductor device and method for manufacturing the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device that can be manufactured at a low cost in an easy process, can suppress the shifting of a threshold voltage to a depression side even if a temperature rises, and can be compatible in both low consumption current and high-speed operation of a drive circuit. <P>SOLUTION: A free carrier concentration in a base region 61 has a temperature dependency that is increased as a temperature rises, because the region 61 is formed by using a dopant where impurity level is formed at a predetermined depth from the band gap end of a semiconductor used as a substrate. Namely, in an n-type MOS transistor, a p-type base region that is added to B is formed by using Be having a deep level. This allows the free carrier concentration Na in the p-type base region to be increased by a predetermined quantity due to a temperature rising, thereby preventing the threshold voltage Vth from being shifted to the depression direction. A threshold voltage control is a very effective method if the threshold voltage is approximated to zero voltage to raise an operating speed without increasing the consumption power of a circuit, particularly in a CMOS configuration. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a semiconductor integrated circuit device having a CMOS configuration, a field effect transistor operable at a high voltage, and a manufacturing method thereof.

  An example of a general n-type MOS transistor is shown in a sectional view in FIG.

As shown in FIG. 6, an N ⁺ -type drain region 20 and an N ⁺ -type source region 30 are formed on the surface layer of the P-type Si substrate 10. Further, a P-type base region 60 is formed on the surface layer of the Si substrate 10 so as to be connected to the drain region 20 and the source region 30. Usually, the base region 60 is formed by introducing, for example, B (boron) having a shallow impurity level into the surface layer of the Si substrate 10.

  A gate insulating film 40 is formed on the base region 60 so as to extend at least from the drain region 20 to the source region 30. A gate electrode 50 is disposed on the gate insulating film 40, and the gate electrode 50 is covered with an interlayer film 70. Further, a drain electrode 80 and a source electrode 90 are formed so as to be connected to the drain region 20 and the source region 30, respectively.

  As an operation of this n-type MOS transistor, a base formed by introducing a B (boron) impurity when a voltage equal to or higher than a threshold voltage Vth determined by the following (formula 1) is applied to the gate electrode 50. An n-type inversion layer is formed on the surface layer of the region 60, and a current flows from the drain electrode 80 to the source electrode 90. On the other hand, if the input voltage to the gate electrode 50 is made lower than Vth or no voltage is input, the drain electrode 80 and the source electrode 90 are electrically insulated.

Vth = φms + {2 · εs · q · Na · (2φB)} ^0.5 / Cox + 2φB (Formula 1)
here,
φms: work function difference between gate electrode 50 and Si εs: dielectric constant of Si q: elementary charge Na: free carrier concentration in base region 60 φB: energy difference Cox between Fermi level of base region 60 and Fermi level of intrinsic semiconductor : Capacitance of gate insulating film
Ref. Literature [S. M. Sze, Physics of Semiconductor Devices 2nd Edition (1981) p. 442])

However, the threshold voltage Vth shown in (Equation 1) shows temperature dependence, and when the normal temperature rises, Vth shifts in the depletion direction. This is because when the temperature rises, the Fermi level of the semiconductor decreases, and the difference between this Fermi level and the Fermi level in the intrinsic semiconductor becomes small. That is, in (Equation 1), φB has a negative dependence on temperature.
Next, regarding the temperature dependence of Vth, a calculated value is shown for an n-type MOS transistor having the following configuration.
Gate electrode 50: N ⁺ polysilicon base region 60: B (boron) impurity concentration 1E16 / cm ³
Gate insulating film 40: thickness 50 nm
B to form a base region 60 (boron) to form an impurity level from the valence band edge at the position of 0.045 (eV) (Ref. Reference [S.M.Sze, Physics of Semiconductor Devices 2 nd Edition ( 1981) p. 21]), assuming that 100% carriers are emitted at room temperature (0-30 ° C.), Na = 1E16 / cm ³ is constant, and the threshold voltage is changed by changing the temperature from (Equation 1). The result of calculating Vth is shown in FIG.

  As a result of calculating the threshold voltage Vth in this way, for example, Vth = 0.49V at 300K, and Vth shifts to the depletion side at 400K, and decreases to Vth = 0.27V.

  Next, the problem of Vth shifting to the depletion side will be described with reference to FIG. 8 showing a CMOS circuit configured using n-type MOS transistor 1. When Vth shifts to the depletion side in the n-type MOS transistor 1, the n-type MOS transistor 1 is not completely cut off when the input signal level is “L”, and a leakage current called a through current is generated from Vdd (power supply potential) to GND. It will flow to (ground potential). The through current increases as Vth shifts to the depletion side. Similarly, even if the temperature rises in the p-type MOS transistor 2 and Vth shifts in the depletion direction, a through current is generated when the input signal level is “H”. When the through current is generated, the power consumption of the CMOS circuit is greatly increased. Therefore, the absolute values of Vth of the n-type MOS transistor 1 and the p-type MOS transistor 2 are normally much larger than “0”. However, for high-speed operation, Vth should be close to 0 voltage, that is, there was a problem that high-speed operation was sacrificed to suppress the through current.

  Accordingly, an object of the present invention is to solve the problems of the prior art as described above, and the threshold voltage Vth is controlled with high accuracy to reduce the temperature coefficient, thereby reducing the current consumption of the drive circuit. And a method of manufacturing the semiconductor device capable of achieving both high-speed operation and high-speed operation.

  In order to solve the above-mentioned problem, a semiconductor device according to claim 1 of the present invention includes a drain region of a first conductivity type formed in a predetermined region of a semiconductor substrate surface layer, and the drain region in a predetermined region of the semiconductor substrate surface layer. A first conductivity type source region formed away from the semiconductor substrate, a second conductivity type base region formed on the semiconductor substrate surface layer in connection with the drain region and the source region, and the base region; A semiconductor device comprising at least a gate insulating film formed extending from the drain region to the source region and a gate electrode formed on the gate insulating film, wherein the semiconductor band used as the substrate By forming the base region using an impurity of a second conductivity type that forms an impurity level having a predetermined depth from the gap end, the free carrier concentration of the base region is reduced. It has temperature dependence that increases with increasing temperature.

  The semiconductor device according to claim 2 is the semiconductor device according to claim 1, wherein the base region includes another impurity of a second conductivity type that forms an impurity level shallower than a band gap end than the impurity. Have.

  The semiconductor device according to claim 3, wherein a drain region of a first conductivity type formed in a semiconductor substrate, a source region of a first conductivity type formed in a predetermined region of the semiconductor substrate surface layer, and a surface layer of the semiconductor substrate surface A second conductivity type gate region formed adjacent to the source region in a predetermined region; and a first conductivity type channel region formed in the semiconductor substrate connected to the gate region and the source region; The gate region is formed using an impurity of a second conductivity type that forms an impurity level having a predetermined depth from the band gap end of the semiconductor used as the base. The free carrier concentration in the region has a temperature dependency that increases as the temperature increases.

  A semiconductor device according to a fourth aspect is the semiconductor device according to the third aspect, wherein the gate region includes another impurity of a second conductivity type that forms an impurity level shallower than a band gap end than the impurity. Have.

  6. The method of manufacturing a semiconductor device according to claim 5, wherein a base region is formed on a semiconductor substrate surface layer, a gate insulating film is formed on the base region, and a gate electrode is formed on the gate insulating film. And forming a drain region and a source region connected to the base region in a predetermined region of the semiconductor substrate surface layer, wherein the step of forming the base region on the semiconductor substrate surface layer comprises: An impurity level of a predetermined depth is formed from a band gap end of a semiconductor having a predetermined conductivity type and used as the base so that the free carrier concentration of the base region increases by a predetermined amount as the temperature increases. The base region is formed using a first impurity.

  6. The method of manufacturing a semiconductor device according to claim 6, wherein the step of forming the base region on a surface of the semiconductor substrate includes the first impurity and the first impurity. And at least two impurities, which are the same conductivity type and a second impurity that forms an impurity level shallower than the first impurity at a band gap end.

  8. The method of manufacturing a semiconductor device according to claim 7, wherein a drain region is formed in a semiconductor substrate, a gate region is formed in a predetermined region of the semiconductor substrate surface layer, and the gate is formed in the predetermined region of the semiconductor substrate surface layer. Forming a source region adjacent to the region, and forming the source region, wherein the gate region and the channel connected to the source region are formed in the semiconductor substrate. The step of forming a gate region on the surface of the semiconductor substrate is a semiconductor having a predetermined conductivity type and used as the substrate so that a free carrier concentration in the gate region increases by a predetermined amount as the temperature increases. The gate region is formed using a first impurity that forms an impurity level having a predetermined depth from the end of the band gap.

  The method of manufacturing a semiconductor device according to claim 8, wherein the step of forming the gate region in the semiconductor substrate surface layer includes the first impurity and the first impurity. And at least two impurities, which are the same conductivity type and a second impurity that forms an impurity level shallower than the first impurity at a band gap end.

  According to the semiconductor device of the first aspect of the present invention, the base region is formed using the second conductivity type impurity that forms an impurity level having a predetermined depth from the band gap end of the semiconductor used as the base. Since the base region has a temperature dependency in which the free carrier concentration increases as the temperature rises, the trade-off between the low current consumption and the high-speed operation of the drive circuit, which has been a problem in the conventional semiconductor device, can be solved. That is, in this semiconductor device, even if the threshold voltage Vth is set to a value close to “0” for high-speed operation, the free carrier concentration increases by a predetermined amount due to the temperature rise. The shift is suppressed and no through current is generated. Therefore, according to the present invention, it is possible to realize a semiconductor device capable of controlling the threshold voltage Vth with high accuracy and achieving both low current consumption and high speed operation of the drive circuit.

  According to another aspect of the present invention, the base region has another impurity of the second conductivity type that forms an impurity level having a shallower depth from the band gap end than the impurity. It is possible to design the free carrier concentration of the base region and to design the free carrier concentration of the base region at a low temperature by using shallow level impurities. For this reason, suppression of threshold fluctuation can be realized with higher accuracy.

  According to the semiconductor device of the third aspect of the present invention, the gate region is formed using the second conductivity type impurity that forms an impurity level having a predetermined depth from the band gap end of the semiconductor used as the base. In addition, since the free carrier concentration in the gate region has a temperature dependency that increases as the temperature rises, even in the semiconductor device of the junction gate type field effect transistor, fluctuations in the threshold voltage due to the temperature rise can be suppressed. The same effect as item 1 is obtained.

  According to another aspect of the present invention, the gate region has another impurity of the second conductivity type that forms an impurity level having a depth shallower from the band gap end than the impurity, so that the deep impurity is used at a high temperature. It is possible to design the free carrier concentration of the gate region, and to design the free carrier concentration of the gate region at a low temperature using shallow level impurities. For this reason, suppression of threshold fluctuation can be realized with higher accuracy.

  According to the method of manufacturing a semiconductor device according to claim 5 of the present invention, the step of forming the base region on the surface of the semiconductor substrate is such that the free carrier concentration in the base region increases by a predetermined amount as the temperature increases. 2. The semiconductor device according to claim 1, wherein the base region is formed using a first impurity that forms an impurity level having a predetermined depth from a band gap end of a semiconductor having a predetermined conductivity type and used as a substrate. . In this case, since the base region can be formed using the first impurity, the semiconductor device in which the free carrier concentration increases by a predetermined amount due to the temperature rise and the threshold value does not shift in the depletion direction is generally manufactured. Can be realized by a process.

  According to a sixth aspect of the present invention, the step of forming the base region in the surface layer of the semiconductor substrate includes the first impurity and the impurity level having the same conductivity type as the first impurity and a depth shallower from the band gap end than the first impurity. Since at least two or more impurities are used together with the second impurity forming the substrate, the free impurity concentration of the base region at a high temperature is designed using the first impurity, and the low temperature is used using the second impurity. It is possible to design the free carrier concentration in the base region. Therefore, in the manufacturing method according to claim 5, the free carrier concentration at both the low temperature and the high temperature is determined depending on the depth of the impurity level formed by the first impurity. Carrier concentration and free carrier concentration at low temperature can be designed separately. For this reason, compared with the manufacturing method according to the fifth aspect, the threshold fluctuation can be suppressed with higher accuracy.

  According to the method for manufacturing a semiconductor device according to claim 7 of the present invention, the step of forming the gate region on the surface of the semiconductor substrate is such that the free carrier concentration in the gate region increases by a predetermined amount as the temperature increases. 4. The semiconductor device according to claim 3, wherein the gate region is formed by using a first impurity which forms an impurity level having a predetermined depth from a band gap end of a semiconductor having a predetermined conductivity type and used as a substrate. . In this case, since the gate region can be formed by using the first impurity, a semiconductor device in which the free carrier concentration increases by a predetermined amount due to the temperature rise and the threshold value does not shift in the depletion direction is generally manufactured. Can be realized by a process.

  According to another aspect of the present invention, the step of forming the gate region on the surface layer of the semiconductor substrate includes the first impurity and the impurity level having the same conductivity type as the first impurity and a depth shallower from the band gap end than the first impurity. Since at least two or more impurities are used together with the second impurity forming the gate electrode, the first carrier is used to design the free carrier concentration of the gate region at a high temperature, and the second impurity is used to lower the temperature. It is possible to design the free carrier concentration in the gate region. Therefore, in the manufacturing method according to claim 7, the free carrier concentration at both the low temperature and the high temperature is determined depending on the depth of the impurity level formed by the first impurity. Carrier concentration and free carrier concentration at low temperature can be designed separately. For this reason, compared with the manufacturing method according to the seventh aspect, the threshold fluctuation can be suppressed with higher accuracy.

(First embodiment)
A first embodiment of the present invention will be described below with reference to FIGS.

  FIG. 1 shows a cross-sectional view of an n-type MOS transistor as an example of a gate insulating field effect transistor according to the first embodiment of the present invention.

An N ⁺ type drain region 20 and an N ⁺ type source region 30 are formed on the surface layer of the P type Si substrate 10. Further, a P-type base region 61 is formed on the surface layer of the Si substrate 10 so as to be connected to the drain region 20 and the source region 30.

Here, the P-type base region 61 is formed using, for example, Be (beryllium), which forms a level deeper than B in a silicon semiconductor, in addition to B (boron) that is normally used as a p-type impurity. The free carrier concentration increases with increasing temperature. Be (Beryllium) is described in the literature [S. M. Sze, according to the ^{Physics of Semiconductor Devices 2 nd Edition (} 1981) p. 21], are known to form an impurity level from the valence band edge in the silicon semiconductor substrate at a position of about 0.17 (eV) .

  Note that the free carrier concentration of the P-type base region 61 increases with temperature due to the influence of Be forming a deep level. Designed to prevent shifting to

  A gate insulating film 40 is formed on the base region 61 so as to extend at least from the drain region 20 to the source region 30. A gate electrode 50 is disposed on the gate insulating film 40, and the gate electrode 50 is covered with an interlayer film 70. Further, a drain electrode 80 and a source electrode 90 are formed so as to be connected to the drain region 20 and the source region 30, respectively.

  Next, the manufacturing method of the n-type MOS transistor in this embodiment is demonstrated using sectional drawing of Fig.2 (a)-(e).

First, in the process of FIG. 2A, a P ⁻ type Si substrate 10 having an impurity concentration of 1E14 to 1E18 cm ⁻³ is manufactured.

In the process of FIG. 2B, for example, beryllium ions 170 are implanted as a first impurity at an acceleration voltage of 10 k to 3 M (eV) to form the P-type base region 61. The total dose is, for example, 1E12 to 1E16 / cm ² .

In the process of FIG. 2C, for example, boron ions 180 are implanted as the second impurity into the P-type base region 61 with an acceleration voltage of 10 k to 3 M (eV). The total dose is, for example, 1E12 to 1E15 / cm ² .

  The first impurity is preferably an impurity that forms a level deeper than the second impurity in the silicon semiconductor. In this embodiment, Be (beryllium) is used as the first impurity and B ( Boron) was used. In addition to Be (beryllium), In (indium), Tl (thallium), or the like can be used as the first impurity that forms a deep level in the silicon semiconductor.

In the step of FIG. 2D, oxidation is performed at about 1000 ° C. to form a gate insulating film 40 having a thickness of about 50 nm, and then polysilicon is patterned to form a gate electrode 50 on the gate insulating film 40. Next, for example, phosphorus ions 172 are implanted at an acceleration voltage of 10 k to 1 M (eV) using the gate electrode 50 as a mask to form the N ⁺ type drain region 20 and the N ⁺ type source region 30. The total dose is, for example, 1E14 to 1E16 / cm ² .

  The order of ion implantation for forming each region is not limited to this. For example, boron ions 180 that are second impurities may be implanted before beryllium ions 170 that are first impurities. .

  In the step of FIG. 2E, a heat treatment is performed at, for example, about 1000 ° C., and the ion-implanted impurities are replaced with lattice positions in the silicon semiconductor. To deposit.

Thereafter, although not particularly shown, contact holes are formed on the N ⁺ -type drain region 20 and the N ⁺ -type source region 30 to form the drain electrode 80 and the source electrode 90, respectively. An n-type MOS transistor is completed.

  The n-type MOS transistor of this embodiment is used by grounding the source electrode 90 and applying a positive voltage to the drain electrode 80. When a voltage equal to or higher than the threshold voltage Vth determined by (Equation 1) is applied to the gate electrode 50, an n-type inversion layer is formed in the base region 61 immediately below the gate insulating film 40, and the drain electrode 80 to the source A current flows to the electrode 90. On the other hand, if the input voltage to the gate electrode 50 is made lower than Vth or no voltage is input, the drain electrode 80 and the source electrode 90 are electrically insulated.

  Here, in the conventional MOS transistor, when the temperature increases, the Fermi level of the semiconductor decreases, and the difference between this Fermi level and the Fermi level in the intrinsic semiconductor decreases. That is, in (Expression 1), φB decreases as the temperature increases, and the threshold voltage Vth shifts to the depletion side.

  However, in this semiconductor device, as described above, the P-type base region 61 is formed using Be (beryllium) in addition to B (boron), and the free carrier concentration increases as the temperature rises. It has characteristics. For this reason, even if the temperature rises, Na increases in (Equation 1), and as a result, a decrease in φB can be suppressed, so that a depletion-side shift of the threshold voltage Vth can be prevented. The increase in free carrier concentration in the P-type base region 61 will be described in more detail later.

  As described above, in the n-type MOS transistor according to the embodiment of the present invention, the free carrier concentration Na of the P-type base region 61 can be increased by a predetermined amount as the temperature rises, so that the shift of the threshold voltage Vth in the depletion direction can be suppressed. It is. Therefore, the threshold voltage control according to the present invention is extremely effective in the case of increasing the operation speed by bringing the threshold voltage close to zero voltage without increasing the power consumption of the circuit, particularly in a semiconductor integrated circuit device having a CMOS configuration. It is an effective method.

  Here, the fact that the free carrier concentration of the P-type base region 61 in the present embodiment increases with temperature will be described in more detail.

  Now, assuming that the impurity concentration formed in the P-type base region 61 is NA, the free carrier concentration Na in the P-type base region 61 is obtained by the following (Equation 2).

Na = NA [1 + g · exp {q (EA−EFp) / kT}] ^{−1 (Formula 2)}

Here, EFp represents the Fermi level in the P-type base region 61, EA represents the impurity level, g is a degeneracy factor, and “= 4” in the P-type. k is the Boltzmann constant and T is the absolute temperature.

In the MOS transistor of this embodiment, in addition to B (boron), Be (beryllium) that forms an impurity level at about 0.17 (eV) from the valence band edge of the silicon semiconductor substrate is used to form a P-type base. Region 61 was formed. In such a P-type base region 61, the free carrier concentration Na at a temperature of 300 K is, for example, that when B impurity concentration is 3.6E15 / cm ³ and Be impurity concentration is 1.8E16 / cm ³ , B is room temperature ( (Equation 2)
Na = 3.6E15 (B free carrier concentration) + 6.4E15 (Be free carrier concentration) = 1.0E16 / cm ³ , 400K,
Na = 3.6E15 + 1.25E16 = 1.61E16 / cm ³
Thus, the free carrier concentration in the P-type base region 61 increases with temperature.

Next, regarding the temperature dependence of Vth of the n-type MOS transistor of this embodiment, a calculated value is shown in the case of the following configuration.
Gate electrode 50: N ⁺ polysilicon base region 60: B (boron) impurity concentration 3.6E15 / cm ³ , Be (beryllium) impurity concentration 1.8E16 / cm ³
Gate insulating film 40: thickness 50 nm
However, the free carrier concentration (1) of B was constant at 3.6E15 / cm ³ , and the threshold voltage Vth was calculated by changing the temperature from (Equation 1). The results are shown in FIG.

  As a result of calculating the threshold voltage Vth, for example, Vth = 0.49V at 300K and Vth = 0.47V at 400K, and the fluctuation of the threshold voltage is suppressed.

  Thus, when the base region 61 is formed using an impurity that forms a deep impurity level such as Be, the free carrier concentration increases as the temperature rises. In 1), Na increases, and as a result, the decrease in φB can be suppressed, so that the depletion-side shift of the threshold voltage Vth can be prevented.

  In the present embodiment, for example, a first impurity Be (beryllium) that forms an impurity level of 0.17 eV from the end of the band gap and a second impurity B (boron) that forms a shallow impurity level. A P-type base region 61 was formed using two impurities. In this way, by using at least two impurities, that is, an impurity that forms a deep level and an impurity that forms a shallow level, the free carrier concentration at room temperature and the free carrier concentration at high temperature can be designed separately. It is.

However, for example, it is of course possible to design the P-type base region 61 using only the first impurity Be (beryllium) so as to suppress the shift of the threshold voltage Vth in the depletion direction. Therefore, although not specifically mentioned as an embodiment, the present invention can also be applied to a MOS transistor in which the P-type base region 61 is formed using only the first impurity Be (beryllium).
(Second Embodiment)
A second embodiment of the present invention will be described with reference to FIGS.

  FIG. 4 shows a silicon carbide semiconductor device functioning as a junction gate type field effect transistor as a second embodiment according to the present invention.

An N ⁻ type epitaxial region 110 is stacked on an N ⁺ type SiC substrate 100 serving as a drain region. An N ⁺ type source region 31 and a P type gate region 120 are formed on the surface layer of the N ⁻ type epitaxial region 110. The gate region 120 is formed using Al (aluminum). According to the literature `` O. Takemura, T. Kimoto, H. Matsunami, T. Nakata, M. Watanabe and M. Inoue, Materials Science Forum Vols. 264-268 (1998) pp. 701-704 '' It has been found that an impurity level is formed at a position of about 0.2 eV from the valence band edge in the silicon carbide semiconductor substrate, and the free carrier concentration increases with increasing temperature in the gate region 120. is doing. Note that the free carrier concentration in the gate region 120 is specifically designed to prevent the shift to the depletion side so that the gate threshold voltage Vth does not fluctuate even when the temperature rises.

Further, an N-type channel region 200 is formed in the epitaxial region 110 so as to be connected to the gate region 120 and the source region 31. Source region 31 is connected to source electrode 150, and gate region 120 is connected to gate electrode 140. A drain electrode 160 is formed on the back surface of the N ⁺ type SiC substrate 100. Reference numeral 130 denotes an interlayer insulating film, which protects and stabilizes the surface and bonding surface.

  Next, the manufacturing method of the silicon carbide semiconductor device in this embodiment is demonstrated using sectional drawing of Fig.5 (a)-(d).

First, in the process of FIG. 5A, an N ⁻ type SiC epitaxial region 110 having, for example, an impurity concentration of 1E14 to 1E18 cm ⁻³ and a thickness of 1 to 100 μm is formed on an N ⁺ type SiC substrate 100 serving as a drain region. Has been.

In the process of FIG. 5B, using the mask material 190, for example, aluminum ions 171 are implanted at a high temperature of 100 to 1000 ° C. at an acceleration voltage of 10 K to 5 M (eV) to form the P-type gate region 120. To do. The total dose is, for example, 1E14 to 1E16 / cm ² .

In the step of FIG. 5C, using the mask material 191, phosphorus ions 182 are multi-stage implanted at an acceleration voltage of 10 k to 1 M (eV) at a high temperature of 100 to 1000 ° C., for example, and the N ⁺ type source region 31 is formed. Form. The total dose is, for example, 1E14 to 1E16 / cm ² .

  Here, the N-type channel region 200 is formed in the epitaxial region 110 in connection with the gate region 120 and the source region 31.

  In the step of FIG. 5D, for example, heat treatment is performed at 1000 to 1800 ° C. to replace the ion-implanted impurities with lattice positions in the silicon carbide semiconductor, and then a CVD oxide film is deposited as the interlayer film 130.

Thereafter, although not particularly shown, contact holes are formed on the N ⁺ -type source region 31 and the P-type gate region 120 to form the source electrode 150 and the gate electrode 140, respectively. Further, a metal film is deposited as the drain electrode 160 on the back surface of the N ⁺ substrate 100, and is heat-treated at, for example, 600 to 1400 ° C. to complete the silicon carbide semiconductor device of the second embodiment shown in FIG. 4 as an ohmic electrode.

The junction gate field effect transistor (JFET) of the present embodiment is used by grounding the source electrode 150 and applying a positive voltage to the drain electrode 160. When a voltage equal to or higher than the threshold voltage Vth ideally determined by (Equation 3) is applied to the gate electrode 140,
Vth = kT / q · {LN (Na / Ni) + LN (Nd / Ni)} (Formula 3)
q: Elementary charge Na: Free carrier concentration in gate region 120 Nd: Free carrier concentration in channel region 200 Ni: Intrinsic carrier concentration k is Boltzmann's constant, T is absolute temperature A storage layer is formed in channel region 200, and drain electrode A current flows from 160 to the source electrode 150. On the other hand, if the input voltage to the gate electrode 140 is lower than Vth or no voltage is input, the drain electrode 160 and the source electrode 150 are electrically insulated.
Here, when the temperature increases, the intrinsic carrier concentration Ni increases in (Equation 3), and the threshold voltage Vth shifts to the depletion side.

  However, in this semiconductor device, as described above, the P-type gate region 120 is formed using Al (aluminum), and the free carrier concentration increases with an increase in temperature. For this reason, even if the temperature rises, Na increases in equation (3), and the depletion-side shift of the threshold voltage Vth can be prevented.

  As described above, in the junction gate field effect transistor (JFET) according to the embodiment of the present invention, the free carrier concentration Na of the P-type gate region 120 can be increased by a predetermined amount as the temperature rises, so that the threshold voltage Vth is depleted. Can be suppressed.

  In the present embodiment, for example, the P-type gate region 120 is formed using only the first impurity Al (aluminum) that forms an impurity level of 0.2 eV from the end of the band gap. However, for example, it is possible to design the P-type gate region 120 using B (boron) or the like as the second impurity so as to suppress the shift of the threshold voltage Vth in the depletion direction. .

  In addition, the embodiment of the present invention has been described using the insulated gate field effect transistor in the first embodiment and the junction gate field effect transistor in the second embodiment. What is important in the present invention is to suppress the depletion direction shift of the threshold voltage by increasing the free carrier concentration with temperature, and is not applied only to the insulated gate field effect transistor. As described above, it can be used effectively in the junction gate type transistor as well.

  Although the embodiment of the present invention has been described using a silicon semiconductor (Embodiment 1) or a silicon carbide semiconductor (Embodiment 2) as a semiconductor substrate, the semiconductor substrate is not limited to silicon or silicon carbide. This is also true when an insulated gate type or junction gate type field effect transistor is made of all semiconductors such as GaAs, Ge, diamond, and GaN.

  Further, the present invention is not limited to the n-type field effect transistors shown in the first and second embodiments, and even in the case of a p-type field effect transistor, n having a predetermined amount of impurity levels. When the type impurity is introduced, the above-mentioned argument is established, and in this case, the effects of the first and second embodiments can be obtained.

  The semiconductor device and the manufacturing method thereof according to the present invention have an effect that a threshold voltage Vth can be controlled with high accuracy, and a semiconductor device that can achieve both low current consumption and high speed operation of the drive circuit can be realized. It is useful as a semiconductor integrated circuit device and a field effect transistor that can operate at a high voltage.

It is sectional drawing which shows the 1st Embodiment of this invention. It is sectional drawing which shows the manufacturing process of the 1st Embodiment of this invention. It is explanatory drawing which shows the temperature dependence calculation value of the threshold voltage in the n-type MOS transistor of the 1st Embodiment of this invention. It is sectional drawing which shows the 2nd Embodiment of this invention. It is sectional drawing which shows the manufacturing process of the 2nd Embodiment of this invention. It is sectional drawing of the n-type MOS transistor of a prior art example. It is explanatory drawing which shows the temperature dependence calculation value of the threshold voltage in the n-type MOS transistor of a prior art example. It is a schematic diagram explaining the problem of the threshold value Vth fluctuation | variation in a CMOS circuit.

Explanation of symbols

1 n-type MOS transistor 2 p-type MOS transistor 10 P ⁻ type Si substrate 20 N ⁺ type drain region 30 and 31 N ⁺ type source region 40 gate insulating film 50 gate electrodes 60 and 61 P type base region 70 interlayer insulating film 80 drain Electrode 90 Source electrode 100 N ⁺ type SiC substrate 110 N ⁻ type SiC epitaxial region 120 P type base region 130 Interlayer insulating film 140 Gate electrode 150 Source electrode 160 Drain electrodes 170 and 171 First impurity ions 180 Second impurity ions 172 , 182 Phosphorus ions 190, 191 Mask material 200 N-type channel region

Claims (8)

A first conductivity type drain region formed in a predetermined region of the semiconductor substrate surface layer; a first conductivity type source region formed in a predetermined region of the semiconductor substrate surface layer away from the drain region; and a semiconductor substrate surface layer A base region of a second conductivity type formed connected to the drain region and the source region, and a gate insulating film formed on the base region so as to extend at least from the drain region to the source region. A semiconductor device comprising a gate electrode formed on the gate insulating film,
By forming the base region using a second conductivity type impurity that forms an impurity level having a predetermined depth from the band gap edge of the semiconductor used as the substrate, the free carrier concentration of the base region is A semiconductor device characterized by having a temperature dependency that increases with an increase.   2. The semiconductor device according to claim 1, wherein the base region has another impurity of a second conductivity type that forms an impurity level shallower than a band gap end than the impurity. A drain region of a first conductivity type formed in a semiconductor substrate; a source region of a first conductivity type formed in a predetermined region of the semiconductor substrate surface layer; and a predetermined region of the semiconductor substrate surface layer adjacent to the source region. A second conductivity type gate region formed in a semiconductor device, and a first conductivity type channel region formed in the semiconductor substrate connected to the gate region and the source region,
By forming the gate region using an impurity of a second conductivity type that forms an impurity level having a predetermined depth from the band gap end of the semiconductor used as the base, the free carrier concentration of the gate region is A semiconductor device characterized by having a temperature dependency that increases with an increase.   4. The semiconductor device according to claim 3, wherein the gate region has another impurity of a second conductivity type that forms an impurity level shallower than a band gap end than the impurity. 5.   Forming a base region on a semiconductor substrate surface layer; forming a gate insulating film on the base region; forming a gate electrode on the gate insulating film; and forming the base in a predetermined region of the semiconductor substrate surface layer. A method of manufacturing a semiconductor device including a step of forming a drain region and a source region connected to a region, wherein the step of forming the base region on a surface layer of the semiconductor substrate has a free carrier concentration of the base region and a temperature of The base region is formed by using a first impurity that has a predetermined conductivity type and that has a predetermined depth from the band gap end of the semiconductor used as the substrate, and that increases by a predetermined amount as it increases. A method of manufacturing a semiconductor device.   The step of forming the base region on the surface of the semiconductor substrate includes the impurity level of the first impurity and the same conductivity type as the first impurity and a depth shallower than the band gap end than the first impurity. The method of manufacturing a semiconductor device according to claim 5, wherein at least two impurities are used together with a second impurity that forms the substrate.   Forming a drain region in the semiconductor substrate; forming a gate region in a predetermined region of the semiconductor substrate surface layer; forming a source region adjacent to the gate region in the predetermined region of the semiconductor substrate surface layer; And forming the source region, wherein the gate region and the channel connected to the source region are formed in the semiconductor substrate, wherein the gate region is formed on the surface of the semiconductor substrate. A step of performing impurity concentration at a predetermined depth from a band gap end of a semiconductor having a predetermined conductivity type and used as the substrate, such that a free carrier concentration in the gate region increases by a predetermined amount as the temperature increases. A method for manufacturing a semiconductor device, wherein the gate region is formed by using a first impurity for forming a semiconductor layer.   The step of forming the gate region in the surface layer of the semiconductor substrate includes an impurity level having the same conductivity type as the first impurity and a depth shallower than a band gap end than the first impurity. The method for manufacturing a semiconductor device according to claim 7, wherein at least two impurities are used together with a second impurity that forms the substrate.

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