JPH04321274A - Schottky barrier semiconductor device - Google Patents

Schottky barrier semiconductor device

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Publication number
JPH04321274A
JPH04321274A JP3115341A JP11534191A JPH04321274A JP H04321274 A JPH04321274 A JP H04321274A JP 3115341 A JP3115341 A JP 3115341A JP 11534191 A JP11534191 A JP 11534191A JP H04321274 A JPH04321274 A JP H04321274A
Authority
JP
Japan
Prior art keywords
conductivity type
schottky barrier
type semiconductor
semiconductor
depth
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP3115341A
Other languages
Japanese (ja)
Other versions
JP2879479B2 (en
Inventor
Masaru Wakatabe
勝 若田部
Mitsugi Tanaka
貢 田中
Shinji Kuri
伸治 九里
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shindengen Electric Manufacturing Co Ltd
Original Assignee
Shindengen Electric Manufacturing Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
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Application filed by Shindengen Electric Manufacturing Co Ltd filed Critical Shindengen Electric Manufacturing Co Ltd
Priority to JP3115341A priority Critical patent/JP2879479B2/en
Priority to US07/870,268 priority patent/US5262669A/en
Publication of JPH04321274A publication Critical patent/JPH04321274A/en
Application granted granted Critical
Publication of JP2879479B2 publication Critical patent/JP2879479B2/en
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Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/861Diodes
    • H01L29/872Schottky diodes
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/0619Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

PURPOSE:To rapidly minimize the loss in inverse leakage current by a method wherein the relations between the angle of the tangential line of the inverse conductivity type semiconductor regions with the depth of a space charge layer during the zero bias time, the nearest distance of multiple inverse conductivity type semiconductor regions and the width and the depth of the space charge layer during the insulation breakdown time are specified to reduce the current and the voltage decline in the normal direction. CONSTITUTION:Multiple inverse conductivity type semiconductor diode regions 2' are arrayed on the surface of one conductivity type semiconductor 1 furthermore, one electrode metal 4 is in Schottky barrier contact with the semiconductor 1 but in ohmic contact or Schottky barrier contact with said region 2'. At this time, the angle theta deg. of the tangential line of the regions 2' on the positions in the space charge layer depth of Wbi during the zero bias time extending from the contact surface (e) of the one electrode metal 4 and the one conductivity type semiconductor 1 making with the central side of the contact surface (e) is specified to be 0<theta deg.<=135 deg. while the relations between the nearest distance W of the regions 2', said depth Wbi and the space charge layer width WB during the insulation breakdown time are specified to be 3Wbi<=W<=2WB.

Description

【発明の詳細な説明】[Detailed description of the invention]

【0001】0001

【産業上の利用分野】本発明はショットキバリア半導体
装置の構造に関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to the structure of a Schottky barrier semiconductor device.

【0002】0002

【従来の技術】周知のように、半導体装置の特性改善、
特に、スイッチング速度、順方向及び逆方向特性につい
ての改善のため、開発が進められ、種々の構造が提案さ
れている。
[Prior Art] As is well known, improving the characteristics of semiconductor devices,
In particular, development is progressing and various structures have been proposed to improve switching speed and forward and reverse characteristics.

【0003】図1に従来のショットキバリア半導体装置
の断面構造図を示す。1は一導電型半導体、例えば、N
型半導体、1′は低抵抗の一導電型半導体、例えば、N
+型半導体、2は逆導電型半導体(例えば、P型半導体
)のガ−ドリング領域、3は絶縁被膜、例えば、SiO
2、4はショットキバリア接触をなす一電極金属、5は
オ−ミック電極金属、Aはアノ−ド電極、Cはカソ−ド
電極である。
FIG. 1 shows a cross-sectional structural diagram of a conventional Schottky barrier semiconductor device. 1 is a semiconductor of one conductivity type, for example, N
type semiconductor, 1' is a low resistance one conductivity type semiconductor, for example, N
+ type semiconductor, 2 is a guard ring region of an opposite conductivity type semiconductor (for example, P type semiconductor), 3 is an insulating film, for example, SiO
Reference numerals 2 and 4 are metal electrodes forming Schottky barrier contact, 5 is an ohmic electrode metal, A is an anode electrode, and C is a cathode electrode.

【0004】図1のショットキバリア半導体装置は耐圧
を改善する構造としてよく知られているが、その反面、
整流作用において、逆方向漏洩電流が大きいため逆方向
損失が大きく整流素子として効率が悪いという欠点があ
る。
The Schottky barrier semiconductor device shown in FIG. 1 is well known as a structure that improves breakdown voltage, but on the other hand,
In the rectifying action, there is a drawback that the leakage current in the reverse direction is large, so the loss in the reverse direction is large, and the efficiency as a rectifying element is poor.

【0005】[0005]

【発明の目的】本発明は前記せる従来装置の問題点を解
消し、逆漏れ電流、及び順方向電圧降下が小さく、高速
で、かつ、低損失のショットキバリア半導体装置の提供
を目的とする。
OBJECTS OF THE INVENTION It is an object of the present invention to solve the above-mentioned problems of the conventional device and to provide a Schottky barrier semiconductor device with low reverse leakage current and forward voltage drop, high speed, and low loss.

【0006】[0006]

【実施例】本発明の実施例を図3、図4及び図5の断面
構造図に示す。図3、図4及び図5はそれぞれ製法を変
えて得た実施例の構造である。又、図6は図5のY−Y
′平面構造図である。
Embodiment An embodiment of the present invention is shown in cross-sectional structural views in FIGS. 3, 4, and 5. FIGS. 3, 4, and 5 each show the structure of an example obtained by changing the manufacturing method. Also, FIG. 6 shows Y-Y in FIG.
'It is a plan view of the structure.

【0007】図1、図3、図4、図5及び図6の符号に
おいて、同一符号は同一部分を示す。又、2′は逆導電
型半導体領域、例えば、P型半導体、6は凹部、Wは逆
導電型半導体領域2′の一導電型半導体1における最近
接距離、Wbiは一電極金属4と一導電型半導体1の接
触面eから延びる零バイアス時の空間電荷層の深さ、θ
はWbiの位置での2′の接線が接触面eの中央側から
形成する角度、fはその接点、Dは接触面eからの2′
の深さである。なお、図示しないが、一導電型半導体1
の絶縁破壊時の空間電荷層幅をWBであらわす。
The same reference numerals in FIGS. 1, 3, 4, 5, and 6 indicate the same parts. Further, 2' is an opposite conductivity type semiconductor region, for example, a P-type semiconductor, 6 is a recess, W is the closest distance between the opposite conductivity type semiconductor region 2' and one conductivity type semiconductor 1, and Wbi is one electrode metal 4 and one conductivity. The depth of the space charge layer at zero bias extending from the contact surface e of the type semiconductor 1, θ
is the angle formed by the tangent of 2' at the position of Wbi from the center of the contact surface e, f is the contact point, and D is the angle 2' from the contact surface e.
depth. Although not shown, one conductivity type semiconductor 1
The width of the space charge layer at the time of dielectric breakdown is expressed by WB.

【0008】本発明の構造で最も重要な要件はθを0<
θ≦135°の範囲とし、かつ、3Wbi≦W≦2WB
の関係に形成することである。
The most important requirement for the structure of the present invention is that θ should be 0<0.
θ≦135° and 3Wbi≦W≦2WB
It is to form a relationship.

【0009】又、0<θ≦135°及び3Wbi≦W≦
2WBの要件に加えて、D≧0.5Wの関係に形成する
ことにより、更に改善した電気的特性を得ることができ
る。
[0009] Also, 0<θ≦135° and 3Wbi≦W≦
In addition to the requirement of 2WB, further improved electrical characteristics can be obtained by forming the relationship D≧0.5W.

【0010】又、一導電型半導体1の表面に凹部6を形
成し、6の内面の全部又は一部に沿って、逆導電型半導
体領域2′の堆積層、又は内部形成層を設けるようにす
ることにより、優れた電気的特性を得ることができる。
Furthermore, a recess 6 is formed on the surface of the semiconductor 1 of one conductivity type, and a deposited layer or an internal formation layer of the semiconductor region 2' of the opposite conductivity type is provided along all or part of the inner surface of the semiconductor 1. By doing so, excellent electrical characteristics can be obtained.

【0011】次に、図3による本発明の構造につき、実
施例を詳述する。N+型0.003Ω・cm、400μ
m厚のシリコン半導体基板上にN型5Ω・cm、14μ
m厚のエピタキシアルシリコン層を堆積した1.6×1
.6mmのチップを用いた。先づ、SiO2膜を形成し
た後、P型ガ−ドリング領域2(図示していない)を形
成した。次いで、ガ−ドリング領域2に囲まれた内側に
複数個の凹部6を形成するため、ステッパ−露光装置と
RIEエッチング装置を用いてSiO2膜に窓をあけ、
更に、SiO2膜をマスクとし、RIEエッチング装置
のエッチングガスを調整して、Siエッチング側面形状
をほぼ垂直に加工した。その後、逆導電型半導体領域2
′を形成するため、BNデポジション、及び拡散を行っ
た。従って、2′は凹部6の内面に内部形成層として設
けられる。次いで、凸部上のSiO2膜を除去して、所
要部にチタン金属を一電極金属4として蒸着し、又、N
iをオ−ミック電極金属5として形成した。
Next, an embodiment of the structure of the present invention shown in FIG. 3 will be described in detail. N+ type 0.003Ω・cm, 400μ
N type 5Ω・cm, 14μ on m-thick silicon semiconductor substrate
1.6×1 with m-thick epitaxial silicon layer deposited
.. A 6 mm tip was used. First, after forming a SiO2 film, a P-type guard ring region 2 (not shown) was formed. Next, in order to form a plurality of recesses 6 inside the guard ring region 2, windows are opened in the SiO2 film using a stepper exposure device and an RIE etching device.
Furthermore, using the SiO2 film as a mask and adjusting the etching gas of the RIE etching apparatus, the Si etching side surface shape was processed to be almost vertical. After that, the opposite conductivity type semiconductor region 2
To form ', BN deposition and diffusion were performed. Therefore, 2' is provided as an internal forming layer on the inner surface of the recess 6. Next, the SiO2 film on the convex portion is removed, titanium metal is vapor-deposited as one electrode metal 4 on the required portion, and N
i was formed as an ohmic electrode metal 5.

【0012】実験により得られた図3の構造における各
指定符号の寸法は、θは約110゜、Wは3.5μm、
Dは3.0μm、L(凹部6の開口幅)は2,0μm、
T(凹部6の深さ)は2.0μm、M(凸部の上部幅)
は6.0μm、B(逆 導電型半導体領域2′の幅)は4.4μm、XB(2′
の底部寸法)は1.0μm、XT(2′の上部寸法)は
1.2μm、各セルサイズCWは8.0μm×8.0μ
mとした。
The dimensions of each designation symbol in the structure of FIG. 3 obtained through experiments are as follows: θ is approximately 110°, W is 3.5 μm,
D is 3.0 μm, L (opening width of recess 6) is 2.0 μm,
T (depth of concave portion 6) is 2.0 μm, M (upper width of convex portion)
is 6.0 μm, B (width of opposite conductivity type semiconductor region 2') is 4.4 μm, XB (2'
(bottom dimension) is 1.0 μm, XT (top dimension of 2′) is 1.2 μm, each cell size CW is 8.0 μm x 8.0 μm.
It was set as m.

【0013】このようにして得た本発明のショットキバ
リア型整流ダイオ−ドの順逆方向特性は図2(a)のJ
F−VF(順電流−順電圧)特性図、及び図2(b)の
JR−VR(逆漏れ電流−逆電圧)特性図のそれぞれに
、ロの曲線により示す。
The forward and reverse characteristics of the Schottky barrier rectifier diode of the present invention thus obtained are shown in FIG. 2(a).
Each of the F-VF (forward current-forward voltage) characteristic diagram and the JR-VR (reverse leakage current-reverse voltage) characteristic diagram in FIG. 2(b) is shown by a curve B.

【0014】又、対比のため、従来構造のショットキバ
リア型整流ダイオ−ドの順逆方向特性を図2(a)、及
び図2(b)のそれぞれに、イの曲線により示す。従っ
て、本発明の半導体装置の逆漏れ電流についての改善の
著しいことが実験により立証できた。なお、一電極金属
4と逆導電型半導体領域2′間をオ−ミック接合とした
ものを曲線口に、又ショットキバリア接合としたものを
曲線ハに示した。
For comparison, the forward and reverse characteristics of a conventional Schottky barrier rectifier diode are shown by curves A in FIGS. 2(a) and 2(b), respectively. Therefore, it has been verified through experiments that the semiconductor device of the present invention has significantly improved reverse leakage current. It should be noted that the curved line C shows an ohmic junction between the one electrode metal 4 and the opposite conductivity type semiconductor region 2', and the curve C shows a Schottky barrier junction.

【0015】本願の構造は、逆バイアス時に一導電型半
導体1と一電極金属4が形成するショットキバリア接合
から延びる空間電荷層を逆導電型半導体領域2′が形成
するPN接合からの空間電荷層で両側からはさみ込むよ
うに配置させることにより、ある逆電圧以上で3方向の
空間電荷層が接触面eからdの深さまで併合することに
よって、ショットキバリア接合である接触面eにかかる
電圧Vに対する電界強度EJをEJ=V/dに弱めるこ
とができる。このことは、併合空間電荷領域の深さdが
深いほど電界強度EJは小さくなる現象の確認にもとづ
く結果である。
In the structure of the present application, a space charge layer extending from a Schottky barrier junction formed by one conductivity type semiconductor 1 and one electrode metal 4 during reverse bias is formed by a space charge layer extending from a PN junction formed by an opposite conductivity type semiconductor region 2'. By arranging them so as to sandwich them from both sides at The electric field strength EJ can be weakened to EJ=V/d. This is a result based on the confirmation of the phenomenon that the electric field strength EJ decreases as the depth d of the merged space charge region increases.

【0016】又、ショットキバリア半導体装置の逆漏れ
電流を改善するためにショットキバリア接合にかかる電
界強度EJを小さくすればよいことは公知の一般式から
導き出せる。
Further, it can be derived from a known general formula that in order to improve the reverse leakage current of a Schottky barrier semiconductor device, the electric field strength EJ applied to the Schottky barrier junction should be reduced.

【0017】前記せる角度θと、一導電型半導体1と一
電極金属4が形成するショットキバリア接合の電界強度
EJとの関係を図7のEJ−θ(電界強度−角度)特性
図に示し、又、角度θとショットキバリア接合の逆漏れ
電流JRとの関係を図8のJR−θ(逆漏れ電流−角度
)特性図に示す。それぞれ、W=2WBとW=3Wbi
における曲線を示し、実用的に好ましいWの範囲をあら
わしている。
The relationship between the above angle θ and the electric field strength EJ of the Schottky barrier junction formed by the one conductivity type semiconductor 1 and the one electrode metal 4 is shown in the EJ-θ (electric field strength-angle) characteristic diagram of FIG. Further, the relationship between the angle θ and the reverse leakage current JR of the Schottky barrier junction is shown in the JR-θ (reverse leakage current-angle) characteristic diagram of FIG. W=2WB and W=3Wbi, respectively.
The curve represents a practically preferable range of W.

【0018】図7から角度θが約90度において、最大
の電界緩和効果を示すことがわかる。即ち、電界強度E
Jは約90度で最小で、それより、小さくても大きくて
もEJが大きくなり、角度θが135度を超えると、従
来のショットキバリア半導体装置のEJの値に近似する
It can be seen from FIG. 7 that the electric field relaxation effect is maximum when the angle θ is about 90 degrees. That is, the electric field strength E
J is minimum at about 90 degrees, and EJ increases whether it is smaller or larger than that, and when the angle θ exceeds 135 degrees, the EJ value approximates that of a conventional Schottky barrier semiconductor device.

【0019】又、図8の逆漏れ電流JRは電界強度EJ
の強さに依存するから、図7にほぼ類似した傾向を示す
In addition, the reverse leakage current JR in FIG. 8 is determined by the electric field strength EJ
7, it shows a tendency almost similar to that shown in FIG.

【0020】次に、逆導電型半導体領域2′の一導電型
半導体1における最近接距離Wと逆漏れ電流JR、順電
圧VFのそれぞれの関係を図9のJR−W特性図、及び
図10のVF−W特性図に示す。
Next, the relationship between the closest distance W, the reverse leakage current JR, and the forward voltage VF in the one conductivity type semiconductor region 2' of the opposite conductivity type semiconductor region 2' is shown in the JR-W characteristic diagram in FIG. 9, and in FIG. This is shown in the VFW characteristic diagram.

【0021】図9は角度θが90度で、逆方向電圧10
Vを印加したときの接触面e(ショットキバリア接合面
)から逆導電型半導体領域2′の深さDとJRを示して
いる。従って、D≧0.5W及びW≦2WBの領域にお
いて、JRが小さくなる傾向を確認できた。
In FIG. 9, the angle θ is 90 degrees and the reverse voltage is 10
Depths D and JR of the opposite conductivity type semiconductor region 2' from the contact surface e (Schottky barrier junction surface) when V is applied are shown. Therefore, it was confirmed that the JR tends to become smaller in the regions of D≧0.5W and W≦2WB.

【0022】図10は順方向電流JF150Amp/c
m2における順電圧VFとWの関係であり、3Wbi≦
W≦2WBが、VFの低い、好ましい範囲といえる。な
お、一電極金属4と逆導電型半導体領域2′間をオ−ミ
ック接合としたものを曲線二に、又、ショットキバリア
接合としたものを曲線ホに示した。
FIG. 10 shows the forward current JF150Amp/c
The relationship between forward voltage VF and W at m2 is 3Wbi≦
W≦2WB can be said to be a preferable range with a low VF. Curve 2 shows an ohmic junction between the one electrode metal 4 and the opposite conductivity type semiconductor region 2', and curve E shows a Schottky barrier junction.

【0023】次いで、本発明の半導体装置によるスイッ
チング特性を示す、trr−W(逆回復時間−最近接距
離)特性図を図11にあげる。
Next, FIG. 11 shows a trr-W (reverse recovery time-nearest distance) characteristic diagram showing the switching characteristics of the semiconductor device of the present invention.

【0023】図11において、逆回復時間trrは前記
せる最近接距離Wが3Wbiより小さくなると著しく大
となり、図10のVF−W特性図と同様の傾向を示した
In FIG. 11, the reverse recovery time trr becomes significantly longer when the nearest distance W becomes smaller than 3Wbi, and shows the same tendency as the VFW characteristic diagram in FIG.

【0024】なお、逆導電型半導体領域2′と一電極金
属4の接合において、2′の表面濃度を約5×1018
Atoms/cm3以下の低濃度にすると、ショットキ
バリア接合を形成するようになる。このようにして、2
′−4間、及び1−4のそれぞれをショットキバリア接
合で形成した場合は、図11のSの線で示すごとく、2
′−4間をオ−ミック接触、及び1−4間をショットキ
バリア接合とした場合と異なり、W≦3Wbiの領域で
もtrrが増大しない。
Note that at the junction between the opposite conductivity type semiconductor region 2' and the one-electrode metal 4, the surface concentration of 2' is set to about 5×10 18
When the concentration is lower than Atoms/cm3, a Schottky barrier junction is formed. In this way, 2
'-4 and 1-4 using Schottky barrier junctions, as shown by the line S in FIG.
Unlike the case where ohmic contact is made between ' and 4 and Schottky barrier junction is made between 1 and 4, trr does not increase even in the region of W≦3Wbi.

【0025】ただし、図2(a)のJF−VF特性のハ
の曲線のごとく、シリ−ズ・オ−ミック性抵抗が少数キ
ャリアで変調を受けない高抵抗のままであるため、大電
流領域でVFが大となる欠点は生ずる。
However, as shown in curve C of the JF-VF characteristic in FIG. 2(a), the series ohmic resistance remains at a high resistance that is not modulated by minority carriers; The disadvantage is that the VF becomes large.

【0026】図3のような本発明装置の構造を得るため
の製法は前述したが、本発明装置の他の実施例である図
4、図5について簡単に述べる。
Although the manufacturing method for obtaining the structure of the device of the present invention as shown in FIG. 3 has been described above, other embodiments of the device of the present invention, shown in FIGS. 4 and 5, will be briefly described.

【0027】図4の構造を形成する製法は、一導電型半
導体1の表面から前記と同様にRIE法により、所望す
る深さD、角度θ、及び幅Wに適合する凹部6を形成し
ておき、しかる後、必要とする濃度の逆導電型不純物を
含んだ堆積層を設けて逆導電型半導体領域2′を形成す
る。その堆積層はエピタキシアル半導体層を形成するか
、多結晶半導体をCVD法により堆積することにより形
成する。このような製法による逆導電型半導体領域2′
の面積は通常の熱拡散法による製法のものに比して約1
/2以下にできる特徴をもっており、主接合のショット
キバリア接合面積を増すことができるから、小面積のチ
ップで大電流のショットキバリアダイオ−ドの実現を可
能とするものである。
The manufacturing method for forming the structure shown in FIG. 4 is to form a recess 6 having a desired depth D, angle θ, and width W from the surface of a semiconductor 1 of one conductivity type by RIE method in the same manner as described above. Thereafter, a deposited layer containing opposite conductivity type impurities at a required concentration is provided to form a reverse conductivity type semiconductor region 2'. The deposited layer is formed by forming an epitaxial semiconductor layer or by depositing a polycrystalline semiconductor by a CVD method. Opposite conductivity type semiconductor region 2' produced by such a manufacturing method
The area is about 1
/2 or less, and the Schottky barrier junction area of the main junction can be increased, making it possible to realize a large current Schottky barrier diode with a small chip area.

【0028】図5の構造は図3及び図4のごとく、凹部
の形成を行うことなく、逆導電型半導体領域2′を拡散
法により形成したものである。図5の構造では、角度θ
を前記せるごとき最も好ましい角度である約90度にす
ることは困難であるが、経済的な製法であり、安価な半
導体装置を得ることが容易となる。
In the structure shown in FIG. 5, as shown in FIGS. 3 and 4, the opposite conductivity type semiconductor region 2' is formed by a diffusion method without forming a recess. In the structure of Figure 5, the angle θ
Although it is difficult to achieve the most preferable angle of about 90 degrees as described above, it is an economical manufacturing method and it becomes easy to obtain an inexpensive semiconductor device.

【0029】一導電型半導体1の表面に凹部6を形成す
る図3、及び図4の構造において、RIE法のエッチン
グガスの組成、温度、圧力等の調整によって、所望の凹
部6の形状を任意に得ることができることを確認してい
る。
In the structure of FIGS. 3 and 4 in which the recess 6 is formed on the surface of the semiconductor 1 of one conductivity type, the desired shape of the recess 6 can be formed arbitrarily by adjusting the etching gas composition, temperature, pressure, etc. of the RIE method. I'm sure you can get it.

【0030】又、凹部6を形成後、ほぼ垂直方向からイ
オン注入法により、凹部6の底部のみ逆導電型不純物の
不純物原子を沈着せしめ、更に、高温拡散すると角度θ
を90度以下まで、容易に選択形成できる。
After forming the recess 6, impurity atoms of the opposite conductivity type are deposited only on the bottom of the recess 6 by ion implantation from a substantially vertical direction, and further, by high temperature diffusion, the angle θ
can be easily selectively formed up to 90 degrees or less.

【0031】本発明の平面構造は図6のY−Y′平面構
造図に限定されるものでなく、例えば、一導電型半導体
1の形状について、ストライプ状、円状、多角形等、種
々のパタ−ン形状の選択をなし得るものである。
The planar structure of the present invention is not limited to the Y-Y′ planar structure diagram in FIG. The pattern shape can be selected.

【0032】又、一電極金属4は図3、図4、及び図5
のごとく、上方からみて、全面をおおって設ける必要は
なく、1との接触面eと2′の少なくとも一部に及んで
設けてあればよい。又、図3、図4の凹部6は4の金属
材料で埋められていてもよい。
Further, one electrode metal 4 is shown in FIGS. 3, 4, and 5.
As seen from above, it is not necessary to provide it covering the entire surface, but it is sufficient to provide it covering at least part of the contact surfaces e and 2' with 1. Further, the recess 6 in FIGS. 3 and 4 may be filled with the metal material 4.

【0033】又、本発明のショットキバリア半導体装置
は整流ダイオ−ドに限定されるものではなく、他の半導
体デバイス、又はその部分構造として用いることが可能
である。
Furthermore, the Schottky barrier semiconductor device of the present invention is not limited to a rectifier diode, but can be used as another semiconductor device or a partial structure thereof.

【0034】その他、本発明の構成要件を満足するなら
ば、いづれの変形、付加、材料変換等の変更を行っても
本発明の範囲に包含される。
[0034] In addition, any modifications, additions, changes in materials, etc., are included within the scope of the present invention, as long as the constituent requirements of the present invention are satisfied.

【0035】[0035]

【発明の効果】以上、説明したごとく、本発明の実施に
より、逆方向特性、及びスイッチング特性に優れ、高速
で、かつ、低損失のショットキバリア半導体装置、特に
、パワ−用をはじめ、各種の産業機器に利用される整流
素子等に適用でき、その効果極めて大なるものである。
As explained above, by carrying out the present invention, a Schottky barrier semiconductor device with excellent reverse direction characteristics and switching characteristics, high speed, and low loss can be obtained, especially for various applications including power applications. It can be applied to rectifying elements used in industrial equipment, and its effects are extremely large.

【図面の簡単な説明】[Brief explanation of drawings]

【図1】従来のショットキバリアの断面構造図である。FIG. 1 is a cross-sectional structural diagram of a conventional Schottky barrier.

【図2】(a)はJF−VF(順電流−順電圧)特性図
、(b)はJR−VR(逆漏れ電流−逆電圧)特性図で
ある。
FIG. 2A is a JF-VF (forward current-forward voltage) characteristic diagram, and FIG. 2B is a JR-VR (reverse leakage current-reverse voltage) characteristic diagram.

【図3】本発明の実施例を示す断面構造図である。FIG. 3 is a cross-sectional structural diagram showing an embodiment of the present invention.

【図4】本発明の他の実施例を示す断面構造図である。FIG. 4 is a cross-sectional structural diagram showing another embodiment of the present invention.

【図5】本発明の他の実施例を示す断面構造図である。FIG. 5 is a cross-sectional structural diagram showing another embodiment of the present invention.

【図6】図5のY−Y′平面構造図である。FIG. 6 is a YY' plane structural diagram of FIG. 5;

【図7】EJ−θ(電界強度−角度)特性図である。FIG. 7 is an EJ-θ (electric field strength-angle) characteristic diagram.

【図8】JR−θ(逆漏れ電流−角度)特性図である。FIG. 8 is a JR-θ (reverse leakage current-angle) characteristic diagram.

【図9】JR−W(逆漏れ電流−最近接距離)特性図で
ある。
FIG. 9 is a JR-W (reverse leakage current-nearest distance) characteristic diagram.

【図10】VF−W(順電圧−最近接距離)特性図であ
る。
FIG. 10 is a VF-W (forward voltage-nearest distance) characteristic diagram.

【図11】trr−W(逆回復時間−最近接距離)特性
図である。
FIG. 11 is a trr-W (reverse recovery time-nearest distance) characteristic diagram.

【符号の説明】[Explanation of symbols]

1    一導電型半導体 1′  低抵抗の一導電型半導体 2    逆導電型半導体のガ−ドリング領域2′  
逆導電型半導体領域 3    絶縁被膜 4    一電極金属 5    オ−ミック電極金属 6    凹部 A    アノ−ド電極 B    2′の幅 C    カソ−ド電極 D    接触面eからの2′の深さ e    1と4との接触面 f    接点 L    6の開口幅 M    凸部の上部幅 T    6の深さ CW  セルサイズ XB   2′の底部寸法 XT   2′の上部寸法 W    2′の1における最近接距離Wbi  4と
1のeから延びる零バイアス時の空間電荷層の深さ WB   絶縁破壊時の空間電荷層幅 θ    Wbiの位置での2′の接線が接触面eの中
央側から形成する角度 JF   順電流 JR   逆漏れ電流 VF   順電圧 VR   逆電圧 trr  逆回復時間 EJ   電界強度
1 One conductivity type semiconductor 1' Low resistance one conductivity type semiconductor 2 Guard ring region of opposite conductivity type semiconductor 2'
Opposite conductivity type semiconductor region 3 Insulating film 4 One electrode metal 5 Ohmic electrode metal 6 Recess A Anode electrode B Width of 2' C Cathode electrode D Depth of 2' from contact surface e 1 and 4 Contact surface f Contact point L Opening width M of 6 Upper width of convex portion T Depth CW of 6 Cell size XB Bottom dimension of 2' XT Upper dimension of 2' W Closest distance Wbi of 2' at 1 4 and 1 Depth WB of the space charge layer at zero bias extending from e of space charge layer width θ at dielectric breakdown Angle JF formed by the tangent of 2' at the position Wbi from the center of the contact surface e Forward current JR Reverse leakage Current VF Forward voltage VR Reverse voltage trr Reverse recovery time EJ Electric field strength

Claims (3)

【特許請求の範囲】[Claims] 【請求項1】  一導電型半導体の表面に複数の逆導電
型半導体領域を配列し、さらに、一電極金属が一導電型
半導体とショットキバリア接触し、逆導電型半導体領域
とはオ−ミック接触、又はショットキバリア接触して成
るショットキバリア半導体装置において、一電極金属と
一導電型半導体の接触面から延びる零バイアス時の空間
電荷層深さWbiの位置での逆導電型半導体領域の接線
が前記接触面の中央側から形成する角度θを0<θ≦1
35°にし、かつ、複数の逆導電型半導体領域の最近接
距離W、Wbi、及び絶縁破壊時の空間電荷層幅WBの
関係を3Wbi≦W≦2WBに形成することを特徴とす
るショットキバリア半導体装置。
1. A plurality of semiconductor regions of opposite conductivity type are arranged on the surface of a semiconductor of one conductivity type, further, one electrode metal is in Schottky barrier contact with the semiconductor of one conductivity type, and the semiconductor regions of opposite conductivity type are in ohmic contact. , or in a Schottky barrier semiconductor device formed by Schottky barrier contact, the tangent to the opposite conductivity type semiconductor region at the position of the space charge layer depth Wbi at zero bias extending from the contact surface of one electrode metal and one conductivity type semiconductor is as described above. The angle θ formed from the center side of the contact surface is 0<θ≦1
35°, and the relationship between the closest distance W, Wbi of a plurality of opposite conductivity type semiconductor regions, and the space charge layer width WB at the time of dielectric breakdown is 3Wbi≦W≦2WB. Device.
【請求項2】  一電極金属と一導電型半導体の接触面
からの逆導電型半導体領域の深さDとWの関係をD≧0
.5Wにすることを特徴とする請求項1のショットキバ
リア半導体装置。
2. The relationship between the depth D and W of the opposite conductivity type semiconductor region from the contact surface of one electrode metal and one conductivity type semiconductor is D≧0.
.. 2. The Schottky barrier semiconductor device according to claim 1, wherein the Schottky barrier semiconductor device has a power of 5W.
【請求項3】  一導電型半導体の表面に凹部を形成し
、該凹部の全部又は一部に沿って、逆導電型半導体領域
の堆積層、又は内部形成層を設けたことを特徴とする請
求項1又は請求項2のショットキバリア半導体装置。
3. A claim characterized in that a recess is formed on the surface of a semiconductor of one conductivity type, and a deposited layer or an internal formation layer of a semiconductor region of an opposite conductivity type is provided along all or part of the recess. The Schottky barrier semiconductor device according to claim 1 or claim 2.
JP3115341A 1991-04-19 1991-04-19 Schottky barrier semiconductor device Expired - Fee Related JP2879479B2 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP3115341A JP2879479B2 (en) 1991-04-19 1991-04-19 Schottky barrier semiconductor device
US07/870,268 US5262669A (en) 1991-04-19 1992-04-17 Semiconductor rectifier having high breakdown voltage and high speed operation

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3115341A JP2879479B2 (en) 1991-04-19 1991-04-19 Schottky barrier semiconductor device

Publications (2)

Publication Number Publication Date
JPH04321274A true JPH04321274A (en) 1992-11-11
JP2879479B2 JP2879479B2 (en) 1999-04-05

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ID=14660146

Family Applications (1)

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Country Status (1)

Country Link
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