JP2879479B2 - Schottky barrier semiconductor device - Google Patents
Schottky barrier semiconductor deviceInfo
- Publication number
- JP2879479B2 JP2879479B2 JP3115341A JP11534191A JP2879479B2 JP 2879479 B2 JP2879479 B2 JP 2879479B2 JP 3115341 A JP3115341 A JP 3115341A JP 11534191 A JP11534191 A JP 11534191A JP 2879479 B2 JP2879479 B2 JP 2879479B2
- Authority
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- Japan
- Prior art keywords
- conductivity type
- type semiconductor
- schottky barrier
- semiconductor device
- contact
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 239000004065 semiconductor Substances 0.000 title claims description 71
- 230000004888 barrier function Effects 0.000 title claims description 31
- 229910052751 metal Inorganic materials 0.000 claims description 17
- 239000002184 metal Substances 0.000 claims description 17
- 230000015556 catabolic process Effects 0.000 claims description 4
- 230000008021 deposition Effects 0.000 claims description 4
- 230000015572 biosynthetic process Effects 0.000 claims description 3
- 239000000758 substrate Substances 0.000 claims description 2
- 238000010586 diagram Methods 0.000 description 17
- 230000005684 electric field Effects 0.000 description 10
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 8
- 238000005530 etching Methods 0.000 description 5
- 238000004519 manufacturing process Methods 0.000 description 5
- 229910052681 coesite Inorganic materials 0.000 description 4
- 229910052906 cristobalite Inorganic materials 0.000 description 4
- 238000000151 deposition Methods 0.000 description 4
- 238000011084 recovery Methods 0.000 description 4
- 239000000377 silicon dioxide Substances 0.000 description 4
- 235000012239 silicon dioxide Nutrition 0.000 description 4
- 229910052682 stishovite Inorganic materials 0.000 description 4
- 229910052905 tridymite Inorganic materials 0.000 description 4
- 238000009792 diffusion process Methods 0.000 description 3
- 238000000034 method Methods 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 230000007423 decrease Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000002474 experimental method Methods 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- 238000007792 addition Methods 0.000 description 1
- 238000013459 approach Methods 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 238000012790 confirmation Methods 0.000 description 1
- 239000000470 constituent Substances 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 230000018109 developmental process Effects 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 239000010936 titanium Substances 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- 238000009736 wetting Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/861—Diodes
- H01L29/872—Schottky diodes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Electrodes Of Semiconductors (AREA)
Description
【0001】[0001]
【産業上の利用分野】本発明はショットキバリア半導体
装置の構造に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a Schottky barrier semiconductor device.
【0002】[0002]
【従来の技術】周知のように、半導体装置の特性改善、
特に、スイッチング速度、順方向及び逆方向特性につい
ての改善のため、開発が進められ、種々の構造が提案さ
れている。2. Description of the Related Art As is well known, the characteristics of semiconductor devices have been improved.
In particular, developments have been made to improve the switching speed, forward and reverse characteristics, and various structures have been proposed.
【0003】図1に従来のショットキバリア半導体装置
の断面構造図を示す。1は一導電型半導体、例えば、N
型半導体、1′は低抵抗の一導電型半導体、例えば、N
+型半導体、2は逆導電型半導体(例えば、P型半導
体)のガ−ドリング領域、3は絶縁被膜、例えば、Si
O2、4はショットキバリア接触をなす一電極金属、5
はオ−ミック電極金属、Aはアノ−ド電極、Cはカソ−
ド電極である。FIG. 1 shows a cross-sectional structure diagram of a conventional Schottky barrier semiconductor device. 1 is a semiconductor of one conductivity type, for example, N
Semiconductor 1 ′ is a low-conductivity one-conductivity semiconductor such as N
+ Type semiconductor, 2 is a guarding region of a semiconductor of the opposite conductivity type (for example, P type semiconductor), 3 is an insulating film, for example, Si
O2 and 4 are one-electrode metals forming a Schottky barrier contact, 5
Is an ohmic electrode metal, A is an anode electrode, C is a cathode.
Electrode.
【0004】図1のショットキバリア半導体装置は耐圧
を改善する構造としてよく知られているが、その反面、
整流作用において、逆方向漏洩電流が大きいため逆方向
損失が大きく整流素子として効率が悪いという欠点があ
る。The Schottky barrier semiconductor device shown in FIG. 1 is well known as a structure for improving the breakdown voltage.
In the rectifying operation, there is a disadvantage that the reverse leakage current is large, the reverse loss is large, and the efficiency as a rectifying element is low.
【0005】[0005]
【発明の目的】本発明は前記せる従来装置の問題点を解
消し、逆漏れ電流、及び順方向電圧降下が小さく、高速
で、かつ、低損失のショットキバリア半導体装置の提供
を目的とする。SUMMARY OF THE INVENTION An object of the present invention is to solve the above-mentioned problems of the conventional device and to provide a high-speed, low-loss Schottky barrier semiconductor device having a small reverse leakage current and a forward voltage drop.
【0006】[0006]
【実施例】本発明の実施例を図3、図4及び図5の断面
構造図に示す。図3、図4及び図5はそれぞれ製法を変
えて得た実施例の構造である。又、図6は図5のY−
Y′平面構造図である。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention is shown in the sectional structural views of FIGS. 3, 4 and 5. FIG. FIGS. 3, 4 and 5 show the structure of the embodiment obtained by changing the manufacturing method, respectively. FIG. 6 is a cross-sectional view of FIG.
It is a Y 'plane structural view.
【0007】図1、図3、図4、図5及び図6の符号に
おいて、同一符号は同一部分を示す。又、2’は逆導電
型半導体領域、例えば、P型半導体、6は凹部、Wは逆
導電型半導体領域2’の一導電型半導体1における最近
接距離、Wbiは一電極金属4と一導電型半導体1の接
触面eから延びる零バイアス時の空間電荷層幅、θはW
biの位置での2’の接線が接触面eの中央側から形成
する角度、fはその接点、Dは接触面eから2’の深さ
である。なお、図示しないが、一導電型半導体1と逆導
電型半導体2’の接合の絶縁破壊時の空間電荷層幅の一
導電型半導体1側に延びる空間電荷層幅をWBであらわ
す。In FIGS. 1, 3, 4, 5 and 6, the same reference numerals indicate the same parts. Further, 2 ′ is a semiconductor region of the opposite conductivity type, for example, a P-type semiconductor, 6 is a concave portion, W is a closest distance in the semiconductor 1 of one conductivity type of the semiconductor region 2 ′ of the opposite conductivity type, and Wbi is one conductivity type with the one electrode metal 4. Is the space charge layer width at zero bias extending from the contact surface e of the type semiconductor 1, and θ is W
The angle formed by the 2 'tangent at the position bi from the center of the contact surface e, f is the contact point, and D is the depth 2' from the contact surface e. Although not shown, the width of the space charge layer extending toward the one conductivity type semiconductor 1 at the time of insulation breakdown at the junction between the one conductivity type semiconductor 1 and the opposite conductivity type semiconductor 2 ′ is represented by WB.
【0008】本発明の構造で最も重要な要件はθを0<
θ≦135°の範囲とし、かつ、3Wbi≦W≦2WBの
関係に形成することである。The most important requirement in the structure of the present invention is that θ is 0 <
θ ≦ 135 ° and 3Wbi ≦ W ≦ 2WB.
【0009】又、0<θ≦135°及び3Wbi≦W≦2
WBの要件に加えて、D≧0.5Wの関係に形成すること
により、更に改善した電気的特性を得ることができる。Also, 0 <θ ≦ 135 ° and 3Wbi ≦ W ≦ 2
By forming the relation of D ≧ 0.5 W in addition to the requirement of WB, further improved electric characteristics can be obtained.
【0010】又、一導電型半導体1の表面に凹部6を形
成し、6の内面の全部又は一部に沿って、逆導電型半導
体領域2′の堆積層、又は内部形成層を設けるようにす
ることにより、優れた電気的特性を得ることができる。A recess 6 is formed in the surface of the one-conductivity-type semiconductor 1, and a deposition layer of an opposite-conductivity-type semiconductor region 2 'or an internal formation layer is provided along the whole or a part of the inner surface of the semiconductor 6. By doing so, excellent electrical characteristics can be obtained.
【0011】次に、図3による本発明の構造につき、実
施例を詳述する。N+型0.003Ω・cm、400μm
厚のシリコン半導体基板上にN型5Ω・cm、14μm
厚のエピタキシアルシリコン層を堆積した1.6×1.6
mmのチップを用いた。先づ、SiO2膜を形成した
後、P型ガ−ドリング領域2(図示していない)を形成
した。次いで、ガ−ドリング領域2に囲まれた内側に複
数個の凹部6を形成するため、ステッパ−露光装置とR
IEエッチング装置を用いてSiO2膜に窓をあけ、更
に、SiO2膜をマスクとし、RIEエッチング装置の
エッチングガスを調整して、Siエッチング側面形状を
ほぼ垂直に加工した。その後、逆導電型半導体領域2′
を形成するため、BNデポジション、及び拡散を行っ
た。従って、2′は凹部6の内面に内部形成層として設
けられる。次いで、凸部上のSiO2膜を除去して、所
要部にチタン金属を一電極金属4として蒸着し、又、N
iをオ−ミック電極金属5として形成した。Next, an embodiment of the structure of the present invention shown in FIG. 3 will be described in detail. N + type 0.003Ω · cm, 400μm
N-type 5 Ω · cm, 14 μm on a thick silicon semiconductor substrate
1.6 × 1.6 deposited thick epitaxial silicon layer
mm chips were used. First, after forming a SiO2 film, a P-type guarding region 2 (not shown) was formed. Next, in order to form a plurality of recesses 6 inside the guard ring 2, a stepper exposure apparatus and R
A window was opened in the SiO2 film using an IE etching apparatus, and the etching gas of the RIE etching apparatus was adjusted using the SiO2 film as a mask to process the Si etching side surface substantially vertically. Thereafter, the reverse conductivity type semiconductor region 2 '
Was formed by BN deposition and diffusion. Therefore, 2 'is provided as an internal formation layer on the inner surface of the concave portion 6. Next, the SiO2 film on the convex portion is removed, and titanium metal is deposited as a one-electrode metal 4 on a required portion.
i was formed as the ohmic electrode metal 5.
【0012】実験により得られた図3の構造における各
指定符号の寸法は、θは約110゜、Wは3.5μm、
Dは3.0μm、L(凹部6の開口幅)は2,0μm、T
(凹部6の深さ)は2.0μm、M(凸部の上部幅)は
6.0μm、B(逆 導電型半導体領域2′の幅)は4.4μm、XB(2′の
底部寸法)は1.0μm、XT(2′の上部寸法)は1.
2μm、各セルサイズCWは8.0μm×8.0μmと
した。The dimensions of each designated code in the structure of FIG. 3 obtained by experiments are as follows: θ is about 110 °, W is 3.5 μm,
D is 3.0 μm, L (opening width of recess 6) is 2.0 μm, T
(The depth of the concave portion 6) is 2.0 μm, M (the upper width of the convex portion) is 6.0 μm, B (the width of the reverse conductivity type semiconductor region 2 ′) is 4.4 μm, and XB (the bottom dimension of the 2 ′). Is 1.0 μm and XT (upper dimension of 2 ′) is 1.0 μm.
2 μm, and each cell size CW was 8.0 μm × 8.0 μm.
【0013】このようにして得た本発明のショットキバ
リア型整流ダイオ−ドの順逆方向特性は図2(a)のJ
F−VF(順電流−順電圧)特性図、及び図2(b)のJR
−VR(逆漏れ電流−逆電圧)特性図のそれぞれに、ロの
曲線により示す。The forward / backward characteristics of the Schottky barrier rectifier diode of the present invention thus obtained are shown in FIG.
F-VF (forward current-forward voltage) characteristic diagram and JR in FIG. 2 (b)
Each of the -VR (reverse leakage current-reverse voltage) characteristic diagrams is shown by a curve b.
【0014】又、対比のため、従来構造のショットキバ
リア型整流ダイオ−ドの順逆方向特性を図2(a)、及
び図2(b)のそれぞれに、イの曲線により示す。従っ
て、本発明の半導体装置の逆漏れ電流についての改善の
著しいことが実験により立証できた。なお、一電極金属
4と逆導電型半導体領域2′間をオ−ミック接合とした
ものを曲線口に、又ショットキバリア接合としたものを
曲線ハに示した。For comparison, forward and reverse characteristics of a Schottky barrier type rectifier diode having a conventional structure are shown by curves a in FIGS. 2A and 2B, respectively. Therefore, experiments have proved that the semiconductor device of the present invention has a remarkable improvement in reverse leakage current. An ohmic junction between the one electrode metal 4 and the opposite conductivity type semiconductor region 2 'is shown in a curved line, and a Schottky barrier junction is shown in a curved line C.
【0015】本願の構造は、逆バイアス時に一導電型半
導体1と一電極金属4が形成するショットキバリア接合
から延びる空間電荷層を逆導電型半導体領域2′が形成
するPN接合からの空間電荷層で両側からはさみ込むよ
うに配置させることにより、ある逆電圧以上で3方向の
空間電荷層が接触面eからdの深さまで併合することに
よって、ショットキバリア接合である接触面eにかかる
電圧Vに対する電界強度EJをEJ=V/dに弱めること
ができる。このことは、併合空間電荷領域の深さdが深い
ほど電界強度EJは小さくなる現象の確認にもとづく結
果である。In the structure of the present invention, the space charge layer extending from the Schottky barrier junction formed by the one conductivity type semiconductor 1 and the one electrode metal 4 at the time of reverse bias is formed by the space charge layer formed by the PN junction formed by the reverse conductivity type semiconductor region 2 '. And the space charge layers in the three directions are merged from the contact surface e to the depth of d at a certain reverse voltage or more, so that the voltage V applied to the contact surface e, which is a Schottky barrier junction, is reduced. The electric field intensity EJ can be reduced to EJ = V / d. This is based on the confirmation that the electric field intensity EJ decreases as the depth d of the merged space charge region increases.
【0016】又、ショットキバリア半導体装置の逆漏れ
電流を改善するためにショットキバリア接合にかかる電
界強度EJを小さくすればよいことは公知の一般式から
導き出せる。It can be derived from a known general formula that the electric field strength EJ applied to the Schottky barrier junction should be reduced in order to improve the reverse leakage current of the Schottky barrier semiconductor device.
【0017】前記せる角度θと、一導電型半導体1と一
電極金属4が形成するショットキバリア接合の電界強度
EJとの関係を図7のEJ−θ(電界強度−角度)特性図
に示し、又、角度θとショットキバリア接合の逆漏れ電
流JRとの関係を図8のJR−θ(逆漏れ電流−角度)特
性図に示す。それぞれ、W=2WBとW=3Wbiにお
ける曲線を示し、実用的に好ましいWの範囲をあらわし
ている。The relationship between the angle θ and the electric field intensity EJ of the Schottky barrier junction formed by the one conductivity type semiconductor 1 and the one electrode metal 4 is shown in an EJ-θ (electric field intensity-angle) characteristic diagram of FIG. The relationship between the angle θ and the reverse leakage current JR of the Schottky barrier junction is shown in the JR-θ (reverse leakage current-angle) characteristic diagram of FIG. Curves at W = 2WB and W = 3Wbi are shown, respectively, and indicate the range of W which is practically preferable.
【0018】図7から角度θが約90度において、最大
の電界緩和効果を示すことがわかる。即ち、電界強度E
Jは約90度で最小で、それより、小さくても大きくて
もEJが大きくなり、角度θが135度を超えると、従
来のショットキバリア半導体装置のEJの値に近似す
る。FIG. 7 shows that the maximum electric field relaxation effect is exhibited when the angle θ is about 90 degrees. That is, the electric field intensity E
J is the minimum at about 90 degrees, and EJ increases when it is smaller or larger than it. When the angle θ exceeds 135 degrees, it approaches the value of EJ of the conventional Schottky barrier semiconductor device.
【0019】又、図8の逆漏れ電流JRは電界強度EJの
強さに依存するから、図7にほぼ類似した傾向を示す。Also, the reverse leakage current JR in FIG. 8 depends on the strength of the electric field intensity EJ, and thus shows a tendency substantially similar to FIG.
【0020】次に、逆導電型半導体領域2′の一導電型
半導体1における最近接距離Wと逆漏れ電流JR、順電
圧VFのそれぞれの関係を図9のJR−W特性図、及び図
10のVF−W特性図に示す。Next, the relationship between the closest distance W, the reverse leakage current JR, and the forward voltage VF in the one conductivity type semiconductor 1 in the reverse conductivity type semiconductor region 2 'will be described with reference to the JR-W characteristic diagram of FIG. Is shown in FIG.
【0021】図9は角度θが90度で、逆方向電圧10
Vを印加したときの接触面e(ショットキバリア接合
面)から逆導電型半導体領域2′の深さDとJRを示し
ている。従って、D≧0.5W及びW≦2WBの領域にお
いて、JRが小さくなる傾向を確認できた。FIG. 9 shows that the angle θ is 90 degrees and the reverse voltage 10
The depth D and JR of the opposite conductivity type semiconductor region 2 'from the contact surface e (Schottky barrier junction surface) when V is applied are shown. Therefore, it was confirmed that JR tended to decrease in the range of D ≧ 0.5 W and W ≦ 2 WB.
【0022】図10は順方向電流JF150Amp/cm
2における順電圧VFとWの関係であり、3Wbi≦W≦2
WBが、VFの低い、好ましい範囲といえる。なお、一電
極金属4と逆導電型半導体領域2′間をオ−ミック接合
としたものを曲線二に、又、ショットキバリア接合とし
たものを曲線ホに示した。FIG. 10 shows a forward current JF150 Amp / cm.
2 is a relationship between forward voltage VF and W, and 3Wbi ≦ W ≦ 2
WB is a preferable range of low VF. Curve 2 shows an ohmic junction between the one electrode metal 4 and the opposite conductivity type semiconductor region 2 ', and curve E shows a Schottky barrier junction.
【0023】次いで、本発明の半導体装置によるスイッ
チング特性を示す、trr−W(逆回復時間−最近接距
離)特性図を図11にあげる。FIG. 11 shows a trr-W (reverse recovery time-closest distance) characteristic diagram showing switching characteristics of the semiconductor device of the present invention.
【0023】図11において、逆回復時間trrは前記せ
る最近接距離Wが3Wbiより小さくなると著しく大とな
り、図10のVF−W特性図と同様の傾向を示した。In FIG. 11, the reverse recovery time trr becomes remarkably large when the closest distance W is smaller than 3 Wbi, and shows the same tendency as the VF-W characteristic diagram of FIG.
【0024】なお、逆導電型半導体領域2′と一電極金
属4の接合において、2′の表面濃度を約5×1018A
toms/cm3以下の低濃度にすると、ショットキバリ
ア接合を形成するようになる。このようにして、2′−
4間、及び1−4のそれぞれをショットキバリア接合で
形成した場合は、図11のSの線で示すごとく、2′−
4間をオ−ミック接触、及び1−4間をショットキバリ
ア接合とした場合と異なり、W≦3Wbiの領域でもtr
rが増大しない。In the junction of the opposite conductivity type semiconductor region 2 'and the one-electrode metal 4, the surface concentration of 2' is set to about 5 × 10 18 A
When the concentration is as low as toms / cm3 or less, a Schottky barrier junction is formed. Thus, 2'-
In the case where each of the regions 4 and 1-4 is formed by a Schottky barrier junction, as shown by the line S in FIG.
Unlike the case where ohmic contact is made between layers 4 and Schottky barrier junction is made between layers 1-4, even in the region of W ≦ 3Wbi, tr
r does not increase.
【0025】ただし、図2(a)のJF−VF特性のハの
曲線のごとく、シリ−ズ・オ−ミック性抵抗が少数キャ
リアで変調を受けない高抵抗のままであるため、大電流
領域でVFが大となる欠点は生ずる。However, as shown by the curve C of the JF-VF characteristic in FIG. However, the disadvantage that VF becomes large occurs.
【0026】図3のような本発明装置の構造を得るため
の製法は前述したが、本発明装置の他の実施例である図
4、図5について簡単に述べる。Although the manufacturing method for obtaining the structure of the apparatus of the present invention as shown in FIG. 3 has been described above, FIGS. 4 and 5, which are other embodiments of the apparatus of the present invention, will be briefly described.
【0027】図4の構造を形成する製法は、一導電型半
導体1の表面から前記と同様にRIE法により、所望す
る深さD、角度θ、及び幅Wに適合する凹部6を形成し
ておき、しかる後、必要とする濃度の逆導電型不純物を
含んだ堆積層を設けて逆導電型半導体領域2′を形成す
る。その堆積層はエピタキシアル半導体層を形成する
か、多結晶半導体をCVD法により堆積することにより
形成する。このような製法による逆導電型半導体領域
2′の面積は通常の熱拡散法による製法のものに比して
約1/2以下にできる特徴をもっており、主接 合のショットキバリア接合面積を増すことができるか
ら、小面積のチップで大電流のショットキバリアダイオ
−ドの実現を可能とするものである。The method of forming the structure shown in FIG. 4 is to form a recess 6 suitable for the desired depth D, angle θ, and width W by RIE from the surface of the one-conductivity type semiconductor 1 in the same manner as described above. After that, a deposition layer containing a necessary concentration of the impurity of the opposite conductivity type is provided to form the opposite conductivity type semiconductor region 2 '. The deposited layer is formed by forming an epitaxial semiconductor layer or by depositing a polycrystalline semiconductor by a CVD method. The area of the opposite conductivity type semiconductor region 2 'formed by such a manufacturing method is characterized in that it can be reduced to about 1/2 or less as compared with that of a manufacturing method formed by a normal thermal diffusion method. Therefore, a Schottky barrier diode with a large current can be realized with a small area chip.
【0028】図5の構造は図3及び図4のごとく、凹部
の形成を行うことなく、逆導電型半導体領域2′を拡散
法により形成したものである。図5の構造では、角度θ
を前記せるごとき最も好ましい角度である約90度にす
ることは困難であるが、経済的な製法であり、安価な半
導体装置を得ることが容易となる。In the structure of FIG. 5, as shown in FIGS. 3 and 4, a reverse conductivity type semiconductor region 2 'is formed by a diffusion method without forming a concave portion. In the structure of FIG.
Although it is difficult to set the angle to about 90 degrees, which is the most preferable angle as described above, it is an economical manufacturing method, and it is easy to obtain an inexpensive semiconductor device.
【0029】一導電型半導体1の表面に凹部6を形成す
る図3、及び図4の構造において、RIE法のエッチング
ガスの組成、温度、圧力等の調整によって、所望の凹部
6の形状を任意に得ることができることを確認してい
る。In the structure shown in FIGS. 3 and 4 in which the concave portion 6 is formed on the surface of the one-conductivity type semiconductor 1, the desired shape of the concave portion 6 can be arbitrarily adjusted by adjusting the composition, temperature, pressure, etc. of the etching gas of the RIE method. Make sure you can get it.
【0030】又、凹部6を形成後、ほぼ垂直方向からイ
オン注入法により、凹部6の底部のみ逆導電型不純物の
不純物原子を沈着せしめ、更に、高温拡散すると角度θ
を90度以下まで、容易に選択形成できる。After the recess 6 is formed, an impurity atom of the opposite conductivity type is deposited only at the bottom of the recess 6 by ion implantation from a substantially vertical direction.
Can be easily selected and formed up to 90 degrees or less.
【0031】本発明の平面構造は図6のY−Y′平面構
造図に限定されるものでなく、例えば、一導電型半導体
1の形状について、ストライプ状、円状、多角形等、種
々のパタ−ン形状の選択をなし得るものである。The plane structure of the present invention is not limited to the YY 'plane structure diagram of FIG. 6, and for example, various shapes such as a stripe shape, a circle shape, a polygon shape, etc. may be applied to the shape of the one conductivity type semiconductor 1. The pattern shape can be selected.
【0032】又、一電極金属4は図3、図4、及び図5
のごとく、上方からみて、全面をおおって設ける必要は
なく、1との接触面eと2′の少なくとも一部に及んで
設けてあればよい。又、図3、図4の凹部6は4の金属
材料で埋められていてもよい。The one-electrode metal 4 is shown in FIGS. 3, 4 and 5.
As seen from above, it is not necessary to cover the entire surface as viewed from above, but it is sufficient if the cover is provided over at least a part of the contact surfaces e and 2 'with 1. Further, the recess 6 in FIGS. 3 and 4 may be filled with the metal material 4.
【0033】又、本発明のショットキバリア半導体装置
は整流ダイオ−ドに限定されるものではなく、他の半導
体デバイス、又はその部分構造として用いることが可能
である。The Schottky barrier semiconductor device of the present invention is not limited to a rectifier diode, but can be used as another semiconductor device or a partial structure thereof.
【0034】その他、本発明の構成要件を満足するなら
ば、いづれの変形、付加、材料変換等の変更を行っても
本発明の範囲に包含される。In addition, any modifications, additions, changes in material conversion, and the like are included in the scope of the present invention as long as the constituent requirements of the present invention are satisfied.
【0035】[0035]
【発明の効果】以上、説明したごとく、本発明の実施に
より、逆方向特性、及びスイッチング特性に優れ、高速
で、かつ、低損失のショットキバリア半導体装置、特に、
パワ−用をはじめ、各種の産業機器に利用される整流素
子等に適用でき、その効果極めて大なるものである。As described above, according to the present invention, a high-speed, low-loss Schottky barrier semiconductor device having excellent reverse characteristics and switching characteristics, particularly,
The present invention can be applied to rectifiers and the like used for various industrial equipments including power use, and the effect is extremely large.
【図1】従来のショットキバリアの断面構造図である。FIG. 1 is a sectional structural view of a conventional Schottky barrier.
【図2】(a)はJF−VF(順電流−順電圧)特性
図、(b)はJR−VR(逆漏れ電流−逆電圧)特性図
である。2A is a JF-VF (forward current-forward voltage) characteristic diagram, and FIG. 2B is a JR-VR (reverse leakage current-reverse voltage) characteristic diagram.
【図3】本発明の実施例を示す断面積造図である。FIG. 3 is a sectional area diagram showing an embodiment of the present invention.
【図4】本発明の他の実施例を示す断面構造図である。FIG. 4 is a sectional structural view showing another embodiment of the present invention.
【図5】本発明の他の実施例を示す断面構造図である。FIG. 5 is a sectional structural view showing another embodiment of the present invention.
【図6】図5のY−Y’平面構造図である。FIG. 6 is a plan structural view taken along the line Y-Y ′ of FIG. 5;
【図7】EJ−θ(電界強度−角度)特性図である。FIG. 7 is an EJ-θ (electric field intensity-angle) characteristic diagram.
【図8】JR−θ(逆漏れ電流−角度)特性図である。FIG. 8 is a characteristic diagram of JR-θ (reverse leakage current-angle).
【図9】JR−W(逆濡れ電流−最近接距離)特性図で
ある。FIG. 9 is a characteristic diagram of JR-W (reverse wetting current—closest distance).
【図10】VF−W(順電圧−最近接距離)特性図であ
る。FIG. 10 is a VF-W (forward voltage-nearest distance) characteristic diagram.
【図11】trr−W(逆回復時間−最近接距離)特性
図である。FIG. 11 is a trr-W (reverse recovery time-closest distance) characteristic diagram.
1 一導電型半導体 1’ 低抵抗の一導電型半導体 2 逆導電型半導体のガードリング領域 2’ 逆導電型半導体領域 3 絶縁被膜 4 一電極金属 5 オーミック電極金属 6 凹部 A アノード電極 B 2’の幅 C カソード電極 D 接触面eからの2’の深さ e 1と4の接触面 f 接点 L 6の開口幅 M 凸部の上部幅 T 6の深さ CW セルサイズ XB 2’の底部寸法 XT 2’の上部寸法 W 2’の1における最近接距離 Wbi 4と1のeから延びる零バイアス時の空間電荷
層幅 WB 1と2’が形成する接合の絶縁破壊時の空間電荷
層幅の1側に拡がった空間電荷層幅。 θ Wbiの位置での2’の接線が接触面eの中央側
から形成する角度 JF 順電流 JR 逆漏れ電流 VF 順電圧 VR 逆電圧 trr 逆回復時間 EJ 電界強度DESCRIPTION OF SYMBOLS 1 One conductivity type semiconductor 1 'Low resistance one conductivity type semiconductor 2 Guard ring region of reverse conductivity type semiconductor 2' Reverse conductivity type semiconductor region 3 Insulating coating 4 One electrode metal 5 Ohmic electrode metal 6 Concave part A Anode electrode B 2 ' Width C Cathode electrode D Depth of 2 'from contact surface e e Contact surface of 1 and 4 f Opening width of contact L6 M Top width of convex portion T Depth of 6 CW Cell size XB 2' bottom dimension XT The top dimension of 2 ′ The closest distance at 1 of W 2 ′ Wbi 4 and the space charge layer width at zero bias extending from e of 1 WB 1 and 1 of the space charge layer width at breakdown of the junction formed by WB 1 and 2 ′ Space charge layer width spread to the side. The angle formed by the tangent line 2 ′ at the position of θ Wbi from the center of the contact surface e JF forward current JR reverse leakage current VF forward voltage VR reverse voltage trr reverse recovery time EJ electric field strength
フロントページの続き (58)調査した分野(Int.Cl.6,DB名) H01L 21/28 - 21/288 H01L 21/44 - 21/445 H01L 29/40 - 29/51 H01L 29/872 Continuation of the front page (58) Field surveyed (Int.Cl. 6 , DB name) H01L 21/28-21/288 H01L 21/44-21/445 H01L 29/40-29/51 H01L 29/872
Claims (3)
半導体領域を配列し、さらに、一電極金属が一導電型半
導体とショットキバリア接触し、逆導電型半導体領域と
はオーミック接触、又はショットキバリア接触して成る
ショットキバリア半導体装置において、一電極金属と一
導電型半導体の接触面から延びる零バイアス時の空間電
荷層幅Wbiの深さ位置での逆導電型半導体領域の接線
が前期接触面の中央側から形成する角度θを0<θ≦1
35゜にし、かつ、複数の逆導電型半導体領域の最近接
距離W、Wbi、及び絶縁破壊時の一導電型半導体側に
延びる空間電荷層幅WBの関係を3Wbi≦W≦2WB
に形成することを特徴とするショットキバリア半導体装
置。A plurality of opposite conductivity type semiconductor regions arranged on a surface of the one conductivity type semiconductor, further, one electrode metal makes Schottky barrier contact with the one conductivity type semiconductor, and ohmic contact with the opposite conductivity type semiconductor region; or In the Schottky barrier semiconductor device formed by Schottky barrier contact, the tangent of the opposite conductivity type semiconductor region at the depth position of the space charge layer width Wbi at zero bias extending from the contact surface between the one electrode metal and the one conductivity type semiconductor is in contact with the first contact. The angle θ formed from the center of the surface is 0 <θ ≦ 1
35 °, and the relationship between the closest distances W and Wbi of the plurality of opposite conductivity type semiconductor regions and the space charge layer width WB extending to the one conductivity type semiconductor at the time of dielectric breakdown is 3Wbi ≦ W ≦ 2WB.
A Schottky barrier semiconductor device characterized by being formed on a substrate.
らの逆導電型半導体領域の深さDとWの関係をD≧0.
5Wにすることを特徴とする請求項1のショットキバリ
ア半導体装置。2. The relationship between the depth D and the width W of the opposite conductivity type semiconductor region from the contact surface between the one electrode metal and the one conductivity type semiconductor is D ≧ 0.
2. The Schottky barrier semiconductor device according to claim 1, wherein the power is 5 W.
該凹部の全部又は一部に沿って、逆導電型半導体領域の
堆積層、又は内部形成層を設けたことを特徴とする請求
項1又は請求項2のショットキバリア半導体装置。3. A concave portion is formed on a surface of the one conductivity type semiconductor,
3. The Schottky barrier semiconductor device according to claim 1, wherein a deposition layer of an opposite conductivity type semiconductor region or an internal formation layer is provided along all or a part of the recess.
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP3115341A JP2879479B2 (en) | 1991-04-19 | 1991-04-19 | Schottky barrier semiconductor device |
US07/870,268 US5262669A (en) | 1991-04-19 | 1992-04-17 | Semiconductor rectifier having high breakdown voltage and high speed operation |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP3115341A JP2879479B2 (en) | 1991-04-19 | 1991-04-19 | Schottky barrier semiconductor device |
Publications (2)
Publication Number | Publication Date |
---|---|
JPH04321274A JPH04321274A (en) | 1992-11-11 |
JP2879479B2 true JP2879479B2 (en) | 1999-04-05 |
Family
ID=14660146
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---|---|---|---|
JP3115341A Expired - Fee Related JP2879479B2 (en) | 1991-04-19 | 1991-04-19 | Schottky barrier semiconductor device |
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JP (1) | JP2879479B2 (en) |
Families Citing this family (14)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2950232B2 (en) * | 1996-03-29 | 1999-09-20 | 日本電気株式会社 | Method for manufacturing semiconductor memory device |
JP3618517B2 (en) | 1997-06-18 | 2005-02-09 | 三菱電機株式会社 | Semiconductor device and manufacturing method thereof |
JP2002076371A (en) * | 2000-06-12 | 2002-03-15 | Fuji Electric Co Ltd | Semiconductor device |
DE102004056663A1 (en) * | 2004-11-24 | 2006-06-01 | Robert Bosch Gmbh | Semiconductor device and rectifier arrangement |
DE102010028203A1 (en) * | 2010-04-26 | 2011-10-27 | Robert Bosch Gmbh | Rectifier bridge circuit |
JP2012023199A (en) | 2010-07-14 | 2012-02-02 | Rohm Co Ltd | Schottky barrier diode |
JP5810522B2 (en) * | 2010-12-14 | 2015-11-11 | 日産自動車株式会社 | Dissimilar material junction diode and method of manufacturing the same |
JP2013030618A (en) * | 2011-07-28 | 2013-02-07 | Rohm Co Ltd | Semiconductor device |
JP5865016B2 (en) | 2011-10-31 | 2016-02-17 | 株式会社 日立パワーデバイス | Trench type Schottky junction type semiconductor device and manufacturing method thereof |
DE102011087591A1 (en) * | 2011-12-01 | 2013-06-06 | Robert Bosch Gmbh | High-voltage trench junction barrier Schottky |
JP5999678B2 (en) * | 2011-12-28 | 2016-09-28 | ローム株式会社 | Semiconductor device and manufacturing method of semiconductor device |
JP2016096351A (en) * | 2015-12-17 | 2016-05-26 | ローム株式会社 | Schottky barrier diode |
JP2017063237A (en) * | 2017-01-13 | 2017-03-30 | ローム株式会社 | Semiconductor device |
CN110707147A (en) * | 2019-08-30 | 2020-01-17 | 西安电子科技大学 | Variable-angle field limiting ring terminal structure and preparation method thereof |
-
1991
- 1991-04-19 JP JP3115341A patent/JP2879479B2/en not_active Expired - Fee Related
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