JPH0560304B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a solid-state imaging device using an interline charge-coupled device type solid-state imaging device (hereinafter abbreviated as IL-CCD).

Conventional configuration and its problems In recent years, solid-state imaging devices have been actively researched and developed as new imaging devices, and are rapidly reaching the stage of practical use.

A television camera using a solid-state image sensor has many characteristics compared to a conventional image pickup tube type television camera, such as a long life, high robustness, no burn-in, and easy handling.

Solid-state image sensors are CCD type, which transfer signal charges from photoelectric conversion elements arranged in an array.
There are many methods, such as a MOS type, in which a signal is read out by addressing the position of a photoelectric conversion element using a scanning pulse output from a shift register arranged in the vertical and horizontal directions. Among these, solid-state image sensors used in television cameras are interline CCD solid-state image sensors (IL
−CCD) is considered the most advantageous.

Below, the configuration and operation of IL-CCD are shown in Figures 1 to 4.
This will be explained using figures.

In FIG. 1, 1 is a photodiode as a photoelectric conversion element, 2 is a vertical transfer register, and this vertical transfer register includes vertical transfer gates 3, 4,
5 and 6. 7 is a signal readout gate, which is equivalent to vertical transfer gates 3 and 5.
It has become common. 8 is a vertical transfer pulse supply terminal. 9 is a horizontal transfer register, and this horizontal transfer register is composed of horizontal transfer gates 10 and 11. 12 is a horizontal transfer pulse supply terminal. Reference numeral 13 denotes a charge detection section, which converts the transferred signal charge into a signal voltage. The charge detection section 13 is usually composed of a floating diffusion amplifier. 14 is a signal output terminal. The operation of the IL-CCD configured as above will be explained next.

The photodiode 1 photoelectrically converts incident light from an object to obtain a signal charge. The signal charges obtained by photoelectric conversion are read into the vertical transfer gates constituting the vertical transfer register 2 via the signal readout gate 7, and then transferred in the vertical direction by the vertical transfer pulse supplied from the vertical transfer pulse supply terminal 8. That is, the data is sequentially transferred in the direction of the horizontal transfer register 9,
The data is read into the horizontal transfer register 9 for each horizontal line. The signal charge read into the horizontal transfer register is sequentially transferred to the charge detection section 13 by a horizontal transfer pulse supplied from the horizontal transfer pulse supply terminal 12, and is converted into a voltage by the charge detection section 13.
It is obtained from the signal output terminal 14 as a point sequential signal. A television signal is obtained by subjecting the dot sequential signal obtained by the method described above to signal processing by an electric circuit.

FIG. 2 shows a plan view of the light receiving section of the IL-CCD. In FIG. 2, parts having the same functions as those in FIG. 1 are given the same numbers. In FIG. 2, 1 is a photodiode, 2 is a vertical transfer register, and 3 to 6 are vertical transfer gates, and the vertical transfer register has a four-phase CCD configuration. 3 is φ _V3 , 4 is φ _V4 , 5 is φ _V1 , and 6 is φ _V2 . Reference numeral 7 denotes a signal readout gate, and the signal readout gate 7 is provided in part in common with the vertical transfer gates 6 and 4, that is, φ _V2 and φ _V4 , corresponding to the photodiode 1. Reference numeral 15 denotes a channel stopper for separating pixels in the horizontal direction (actually, it is also installed around the photodiode in areas other than the readout gate section).

Next, the vertical transfer register, photodiode,
The relationship between signal readout gates and the like will be explained using FIGS. 3a and 3b.

FIG. 3 is a sectional view taken along the line AA' shown in FIG. 2.

In FIG. 3a, parts having the same functions as those in FIGS. 1 and 2 are given the same numbers.

In FIG. 3a, the solid-state image sensor is an n-type substrate 1.
A p-layer 17 is epitaxially grown on top of the p-layer 17, and an n ⁺ layer 1 is provided on top of the p-layer 17 to form a photodiode with a PN junction. 6 is a vertical transfer gate, and the vertical transfer gate is arranged above the n ^- layer 18 and the p ⁺ layer 7. Reference numeral 7 denotes a signal readout gate, and a buried channel type CCD, that is, a vertical transfer register 2 is constructed at the junction between the n ^- layer 18 and the p layer 17. Reference numeral 19 denotes a light-shielding aluminum wiring for preventing the incident light from the object from being irradiated onto parts other than the photodiode section 1 and generating false signals such as smear. Here, a reverse bias voltage is applied between the substrate 16 and the epitaxial layer 17 by a power source 20. Also 1, 7, 8, 13
Each diffusion layer and the transfer electrode 6 are insulated with silicon oxide (SiO ₂ ) 21, and the surface of the element is protected by covering with phosphor glass (PSG) 22. FIG. 3b is a diagram showing an outline of the potential of each part in FIG. 3a. In FIG. 3b, the solid line potential diagram is a potential diagram during vertical transfer. The potential of the channel stopper region 15 is always constant. The potential of the photodiode section 1 takes a value between the potential V _A in the dark state and the potential V _B when the signal charge is full after receiving the incident light. The potential of the vertical transfer stage 18 is the potential V _C when no vertical transfer pulse is applied to the vertical transfer gate 6.
potential when vertical transfer pulse is applied
Takes a value between V and _D. Also, the signal readout gate 7
The potential takes a value between the potential V _E when the vertical transfer pulse is not applied to the vertical transfer gate 6 and the potential V _F when it is applied.
The signal charge in the vertical transfer stage 18 is a potential
Transferred between V _C and V _D.

Next, the potential when reading the signal charge of the photodiode 1 into the vertical transfer stage 18 will be explained.

To read signal charges into the vertical transfer stage 18, a signal read pulse is applied to the vertical transfer gate 6 during the vertical retrace period. If a signal read pulse that is sufficiently larger than the vertical transfer pulse is applied to the vertical transfer gate 6, the potential of the signal read gate 7 and the vertical transfer stage 18 becomes the potential shown by the broken line in FIG. 3b. That is, the potential of the signal readout gate is V _G , the potential of the vertical transfer stage 18 is V _H , and the signal charge accumulated in the photodiode 1 is read out to the vertical transfer stage 18 only during the period when the signal readout pulse is applied. . If the vertical transfer pulses φ _V1 to φ _VS shown in FIG. 4 are supplied to the IL-CCD configured as described above from the vertical transfer pulse supply terminal 8 shown in FIG. In the second field, the signal charge of the photodiode of the horizontal line where _V2 is common is read out, and the signal of the photodiode of the horizontal line where the signal read gate and _φV4 are common is read out. Therefore, by subjecting the signal voltage obtained from the signal output terminal 14 to signal processing using an electric circuit, it is possible to obtain a television signal subjected to 2: interlaced scanning. Here, among the vertical transfer pulses shown in FIG. 4, the pulses A shown at φ _V2 and the pulses B shown at φ _V4 are signal read pulses.

However, two problems arise when 2:1 interlaced scanning is performed with the above-described vertical transfer pulse relationship.

The first problem is the occurrence of afterimages. The cause of the afterimage is that, as is clear from FIG. 4, the signal charge accumulation time in the photodiode is two field periods, but the signal charge is read out every other horizontal line and every field. It is. Therefore, when the television camera is panned during imaging, an afterimage occurs in which the signal charge after one field is read out, and the edges of the image appear double.

The second problem is the occurrence of interlace flicker. In general image pickup tubes such as vidicon, the scanning beam is approximately circular, and the diameter of the scanning beam is equal to the original scanning line width (length of the effective screen of the image pickup tube/number of scanning lines in one frame). Since it is relatively large (spread out), the scanning beam 30 scans across both fields as shown in FIG. Note that the actual scanning beam is large and the electron density has a glass distribution with respect to the beam center.
Therefore, the boundaries between scanning lines are blurred. That is, the MTF in the vertical direction is less than or equal to the number of vertical lines.

However, in the case of a solid-state image pickup device, as shown in FIG. 2, the photodiodes 1 are arranged in a completely dispersed manner, so that the boundaries between scanning lines do not become blurred as in an image pickup tube. i.e. in the vertical direction
MTF hardly decreases even when the number of vertical scanning lines approaches. Therefore, an image of a subject with no vertical correlation, whose luminance signal changes greatly in the vertical direction, is captured and monitored.
When viewed on TV, the signal changes greatly from field to field in the subject areas where there is no vertical correlation, so
Vertical edges appear as flickering, resulting in unsettled image quality.

Therefore, as a method to solve the above-mentioned drawbacks, the accumulation period of the signal charge in the photodiode is set to one field period, and the signal readout is performed for each field, thereby eliminating the occurrence of afterimages. By mixing and reading out the signal charges of the photodiodes in the horizontal line and shifting one line for each field, the apparent aperture ratio of the photodiode is increased. A driving method for an IL-CCD that does not generate response frizz has been proposed.

Next, a conventional example of a solid-state imaging device using the above-mentioned IL-CCD driving method will be described with reference to FIGS. 6 and 7.

FIG. 6 shows vertical transfer pulses of an IL-CCD in a conventional example. φ _V1 and φ _V3 are the same as the vertical transfer pulses for frame readout shown in Figure 4, but
For φ _V2 and φ _V4 , signal read pulses are provided for both the first and second fields. When the vertical transfer pulse shown in FIG. 6 is applied to the φ _V1 to φ _V4 supply terminals of the vertical transfer pulse supply terminal 8 of the IL-CCD shown in _FIG .
An outline of the potential in φ _V4 26 is shown in FIG.

FIG. 7 shows the potential of the BB' cross section shown in FIG. 2, and each potential diagram is for each time from t ₁ to t ₂₀ shown in FIG. 6. here,
The mechanism of reading signals from the photodiode to the vertical transfer stage has been explained using FIG. 3, and will therefore be omitted. Also, the light-shielding aluminum wiring and surface protection film (PSG), etc., which are unnecessary for explaining the potential, are omitted.

In FIG. 7, 8 is a vertical transfer pulse supply terminal;
18 is an n ^- diffusion layer that constitutes a vertical transfer stage, 23 is a _φV1 electrode, 24 is a _φV2 electrode, 25 is a _φV3 electrode, 26 is a _φV4 electrode, and 21 is a diffusion layer that separates the _φV1 to _φV4 electrodes. It is an insulating layer (SiO ₂ ).

Next, the operation when the vertical transfer pulses φ _V1 to φ _V4 are applied to the vertical drive pulse supply terminal 8 will be explained based on FIG.

First, the potential at t ₁ during the vertical blanking period of the first field in Fig. 6 is the same as that in Fig. 7 a.
It takes the form shown in t ₁ , but there is no signal charge at this time. The barriers shown in the diagram showing the potential in Figure 7 are those that occur during the manufacturing process of solid-state imaging devices, such as misalignment of masks when forming vertical transfer electrodes, etc., and the diffusion process of the n ^-layer . In this conventional example, the φ _V1 electrode and the φ _V2 electrode
It is assumed that a barrier occurs at the joint of the electrodes. This potential barrier can be ignored due to fringe effects _etc. in the part where the voltage is applied to the φ _V electrode and _the potential is high. Cases are not shown.
The barrier mentioned above would not occur if solid-state imaging devices were manufactured in a completely ideal manner, but current semiconductor ICs
In process technology, there are limits to mask alignment accuracy, etc., and this almost always occurs. Next, the potential at time t ₂ takes the form shown at t ₂ in FIG. 7a. That is, by applying a signal read pulse to the electrode φ _V2 , the signal charges Q ₁ and Q ₃ (signal charges in this case are electrons) of PD1 and PD3 shown in Fig. 2 are read into the packet under the φ _V2 electrode. . (Here, the mechanism of reading from the photodiode into the packet under the _φV electrode is omitted as it was explained in Figure 3). then time t ₃
The potential at is in the form shown at t ₃ in Figure 7a. At this time, the charge under the φ _V2 electrode is diffused under the φ _V2 and φ _V3 electrodes, and the potential under the φ _V2 electrode changes greatly from the state at t ₂ to the state at t ₃ , so the direction of arrow A shown at t ₃ A vector of is given to the charge, and as a result, a part of the signal charge Q ₁ is pushed under the φ _V4 electrode. Next, at time t ₄ , voltage is applied to the φ _V3 and φ _V4 electrodes, so the potential takes the form shown at t ₄ in FIG. 7a. That is, since the potential state at t ₃ is transferred by one electrode in the charge transfer direction, the signal charge Q ₁ gathers in the packet under the φ _V3 and φ _V4 electrodes. The potential at time t ₅ is the seventh
The shape is shown in _t5 in Figure a, and PD2 shown in Figure 2,
Signal charges Q ₂ and Q ₄ of PD4 are read under the φ _V4 electrode. At this time, the signal charges Q ₁ and Q ₂ coexist, but for convenience of explanation, they are separated as shown in the figure. Next, the potential at time t ₆ becomes the form shown at t ₆ in Figure 7a, but the potential under the φ _V4 electrode changes from the state of t ₅ to t ₆
Because of the large _change to the state _{shown in FIG} .
At this time, since a barrier exists at the junction surface of the φ _V1 and φ _V2 electrodes, the signal charge does not move below the φ _V1 electrode. Next, at time t ₇ , voltage is applied to the φ _V2 and φ _V3 electrodes, so that from the state at time t ₆ , one electrode is transferred in the opposite direction to the charge transfer direction, as shown in Figure 7b. Therefore, the signal charges Q ₁ and Q ₂ are φ _V2 ,
φ It gathers under the _V3 electrode. From this state, the charge is transferred one electrode at a time in the direction of charge transfer, as shown from time _t8 to _t10 .

Next, the operation in the second field will be explained.

t ₁₁ during the vertical blanking period in the second field,
The potential at t ₁₂ is t ₁₁ and t ₁₂ in FIG. 7c. Since the operation is the same as in the first field, the explanation will be omitted. At time t ₁₃ , the potential under the φ _V4 electrode changes significantly from the state at t ₁₂ to the state at t ₁₃ , so a vector in the direction of arrow A shown at t ₁₃ is given to _the charge _. Since there is a barrier at the φV2 electrode, the signal charge does not move below the _φV2 electrode. At time _t14 , one electrode is transferred in the direction of movement from time _t13 . then time t ₁₅
The signal charges Q ₁ , Q ₃ to the packet under the φ _V2 electrode at
Load. Next, the potential at time t ₁₆ takes the form shown at t ₁₆ in Figure 7c, but since the potential under the φ _V2 electrode changes greatly from the state at t ₁₅ to the state at t ₁₈ , the vector in the direction of arrow B changes. is given to the signal charge, and as a result, a part of the signal charge is pushed under the φ _V4 electrode. Next, at time t ₁₇ , φ _V2
Since the potential under the electrode φ V4 decreases and the potential under the φ _V4 electrode increases, the vector shown in C is given to the signal charge, so the signal charge that was under the φ _V4 electrode at t ₁₆ is as shown in Figure 7 d at t ₁₇ . so φ _V3
Move below the electrode. Next, at time t ₁₈ , φ _V1 ,
A voltage is applied to the φ _V2 electrode, resulting in the potential shown at t _18. At this time, the signal charge that existed under the φ _V4 and φ _V1 electrodes at t ₁₇ is transferred to the φ _V1 and φ _V2 electrodes at t ₁₈ . The signal charge that was under the φ _V3 electrode at t ₁₇ remains unchanged at t ₁₈ as well. Next, at time _t19 , a voltage is applied to the _φV2 and _φV3 electrodes, so that at time _t18 , the charges existing under the _φV3 electrode and the charges existing under the _φV2 electrode are mixed.
Thereafter, starting from time _t20 , the charges are sequentially transferred in the signal charge transfer direction and read out as signal charges.

However, as is clear from t ₁₀ and t ₂₀ in FIG. 7, the signal charges are mixed into almost the same signal components in both the first and second fields.

Therefore, in this conventional example, the accumulation time of the signal charge in the photodiode is one field period, and the signal charge is read out every field, so no afterimage occurs.However, as mentioned above, the first , since substantially the same photodiode signals are mixed and read out in both the second fields, the number of pixels in the vertical direction is equivalently reduced to 1/2. Furthermore, since both the first and second fields have almost the same signal components, when an object whose luminance signal changes in the vertical direction is imaged and viewed on a monitor TV, the vertical edges where the luminance signal changes in the vertical direction , appearing as jitters and resulting in unstable image quality.

Therefore, the above-described driving of the IL-CCD has not achieved its initial purpose.

OBJECTS OF THE INVENTION The present invention solves the above conventional problems and provides a solid-state imaging device that has no afterimage, no interlace flicker, and almost no deterioration in resolution in the vertical direction.

Structure of the Invention In order to achieve the above object, the present invention includes a group of photoelectric conversion elements arranged in an array, a vertical transfer register consisting of a 4-phase CCD, and a horizontal transfer register consisting of a 2-phase CCD, and is compatible with the photoelectric conversion elements. The signal readout gates arranged as shown in FIG. , the vertical transfer transfer pulse is reset for each field, and even when the signal readout pulse is applied to read out the signal charge, the charge is always moved in the transfer direction, and the signal charge of the vertically adjacent photoelectric conversion element is After mixing, the signal is obtained in time series by charge transfer, and there is no afterimage or interlace flicker.
A solid-state imaging device with good vertical resolution can also be obtained.

DESCRIPTION OF EMBODIMENTS An embodiment of the solid-state imaging device according to the present invention will be described below with reference to FIGS. 8 and 9.

FIG. 8 shows the vertical transfer pulse of the IL-CCD according to the present invention. φ _V1 in the first field,
The pulses φ _V2 , φ _V3 , and φ _V4 are equal to φ _V3 , φ _V4 , φ _V1 , and φ _V2 in the second field, respectively. Further, signal readout pulses are provided at φ _V2 and φ _V4 in each of the first fields. The vertical transfer pulse shown in Figure 8 is
Vertical transfer pulse supply terminal 8 of IL-CCD shown in the figure
FIG. 9 shows an outline of the potential in the vertical transfer gates φ _V1 23 to _{φ V4} 26 forming the vertical transfer stage when the voltage is supplied to the φ _V1 to φ _V4 terminals of the vertical transfer stage. In FIG. 9, the presence of the potential barrier of each electrode, etc. is the same as that explained in FIG. 7 of the conventional example, so a description thereof will be omitted.

The outline of the potential at time to shown in FIG. ₈ is shown in correspondence with FIG. 9 _to .

First, at time _t1 , as shown in FIG. 9a, packets are generated under the φ _V2 and φ _V3 electrodes, but no signal charge exists. At time _t2 , the signal charges of photodiodes PD1 and PD3 are read under the _φV2 electrode. At time t ₃ , the signal charges Q ₁ and Q ₃ under the φ _V3 electrode are diffused under the electrodes φ _V2 and φ _V3 , and the potential under the φ _V2 electrode is further increased.
t ₃ to change significantly from the state of t ₂ to the state of t ₃
Since a vector in the direction of arrow A shown in is given to the charge, part of Q ₁ and Q ₃ is pushed under the φ _V4 electrode. At time _t4 , the packet spreads below the electrodes _φV2 to _φV4 , so that all of the signal charges _Q1 and _Q3 are accumulated in the packet again. Signal charges are transferred in the charge transfer direction from time _t5 to _t7 . At the time when the time changes from time _t5 to time _t7 , transfer for one transfer electrode is performed. PD2, PD4, PD at time t ₈
Four (not shown) signal charges Q ₀ , Q ₂ , Q ₄ are read under the φ _V4 electrode. Next, at time t ₉ , φ _V1 ,
A mixture of signal charges Q ₁ and Q ₂ , Q ₃ and Q ₄ exists under the φ _V4 electrode. Here, the potential under the φ _V4 electrode is
Since there is a large change from t ₈ to t ₉ , a vector in the direction shown at t ₉ is given, but since there is a barrier between φ _V1 and φ _V4 , the signal charge is not pushed under the φ _V2 electrode. During times t ₁₀ to t ₁₃ , charges for two transfer electrodes are transferred in the transfer direction. Thereafter, the signal is sequentially transferred vertically and horizontally using a transfer pulse to obtain a signal output.

Next, the operation in the second field will be explained.
The potential at times t ₁₄ and t ₁₅ is the same as the operation at times t ₁ and t ₂ . At time t ₁₆ , the potential under the φ _V4 electrode changes significantly from the state at t ₁₅ to the state at t ₁₆ , so a vector in the direction of arrow A shown at t ₁₆ is given to _the charge _. Since there is a barrier at , the signal charges Q ₀ and Q _{2 are}
It does not move below the electrode. Then time t ₁₆ ~ _{t 20}
, the signal charges Q ₀ , Q ₂ , and Q ₄ are transferred in the transfer direction by two transfer gates. Next, at t ₂₁ , the signal charges of photodiodes PD1 and PD3
Read Q ₁ and Q ₃ under the φ _V2 electrode, because the potential under the φ _V2 electrode changes greatly at t ₂₂ .
A vector in the direction of arrow B shown at _t22 is applied to the signal charge, and as a result, a portion of the signal charge is pushed under the _φV4 electrode.

Next, at _t23 , a voltage is applied to the φ _V4 electrode, so the signal charges Q ₀ Q ₁ and Q ₂ Q ₃ are again accumulated in the packet under the φ _V2 to φ _V4 electrodes. After being transferred from _t24 to _t25 , the signal is sequentially transferred vertically and horizontally using a transfer pulse and obtained as a signal output.

Here, as is clear from t ₁₃ and t ₂₆ in Figure 9,
In the first field, PD1, PD2, PD3
A signal obtained by mixing the signal charges Q ₁ and Q ₂ and Q ₃ and Q ₄ of PD4 is read out, and in the second field,
Only the signals of the signal charges Q ₀ and Q ₁ , Q 2 and Q 3 of PDO (not shown) and PDI, _PD2 and _PD3 are mixed and read out. In other words, when a vertical transfer register is composed of a 4-phase CCD, the transfer direction is not determined due to its structure, so only predetermined charges are mixed in the charge movement vector generated by the application of the drive voltage. You have to make it look like this.

In a solid-state imaging device, the mixed and read signals are processed by an electric circuit to obtain a television signal.

As explained above, by using the vertical transfer pulse according to the present invention, signal charges of two vertically adjacent horizontal lines can be completely mixed and then read out.

In the above specific example, a 4-phase CCD was used for the vertical register, but the same applies to a 3-phase CCD.

Effects of the Invention As described above, according to the present invention, the accumulation time of the signal charge in the photodiode is one field period, and the signal readout is also performed for each field, so that the afterimage described in the conventional example does not occur at all.

In addition, since the signal charges of the photodiodes in two horizontal lines adjacent to each other in the vertical direction are mixed and read out, the apparent aperture ratio of the photodiodes becomes wider. Therefore, there is no occurrence of interlace fritz.

Furthermore, when mixing the signal charges of the photodiode, the signal charges are mixed in an interlaced manner between the first field and the second field.
Vertical resolution is not a problem at all because vertical resolution equivalent to that of imaging can be obtained.

[Brief explanation of drawings]

Figure 1 is IL-CCD equivalent circuit, Figure 2 is IL-
A plan view of the CCD, Figure 3a is a cross-sectional view of the IL-CCD,
Fig. 4 shows the vertical drive pulses of a conventional IL-CCD, and Fig. 5 shows the relationship between the scanning line and the electron beam in the image pickup tube. , FIG. 6 is a diagram showing the vertical transfer pulse of the conventional example, FIG. 7 a, b, c, and d are diagrams showing the potential of the vertical transfer stage of the conventional example, and FIG. FIGS. 9A, 9B, 9D, and 9D are diagrams showing vertical transfer pulses in the embodiment, and are diagrams showing the potential of the vertical transfer stage in an embodiment of the solid-state imaging device of the present invention. 1...Photodiode (photoelectric conversion element), 2
... Vertical transfer register, 3, 4, 5, 6 ... Vertical transfer gate, 7 ... Signal readout gate, 8 ...
Vertical transfer pulse input terminal, 9...Horizontal transfer register, 10, 11...Horizontal transfer gate, 12...Horizontal transfer pulse input terminal, 13...Charge detection section, 2
3...φ _V1 electrode, 24...φ _V2 electrode, 25...φ _V3
Electrode, 26...φ _V4 electrode.

Claims (1)

[Claims] 1 A group of photoelectric conversion elements arranged in an array and a 4-phase
a signal readout gate comprising a vertical transfer register consisting of a CCD and a vertical transfer register consisting of a two-phase CCD and arranged corresponding to the photoelectric conversion element;
When a predetermined transfer gate among the transfer gates constituting the vertical transfer register is connected equivalently in common, and a signal charge is read from the photoelectric conversion element to the vertical transfer register, the vertical transfer is reset for each field. Pulses are applied in the order of arrangement of the four-phase vertical transfer registers, and signal charge readout pulses are also sequentially applied in different periods within one cycle of the vertical transfer pulses to read signals of vertically adjacent photoelectric conversion elements. A solid-state imaging device characterized by adding signals and then extracting signals in time series by charge transfer.