JPS604381A - Solid-state image pickup device - Google Patents

Abstract

PURPOSE:To obtain a solid-state image pickup device which does not give any persistence and flicker and is excellent in vertical resolution by transferring the signal electric charges of elements which are adjacent to each other in the vertical direction after mixing when a signal electric charge is read from a photoelectric transducer to a vertically transferring register. CONSTITUTION:At a time t1, packets are produced below the electrodes of phiV2 and phiV3, but no signal electric charge exists. At a time t2, the signal electric charge of a photodiode is read to below the electrode of the phiV2 and the read electric charge is diffused below the electrode of the phiV3. At a time t4, since the packets are extended to below the electrodes of phiV2-phiV4, all signal electric charges Q1 and Q3 are accumulated in the packets again and the accumulated signal electric charges Q1 and Q2 are transferred in the electric charge transferring direction at times t2-t7 (not shown in the figure). Signal electric charges are read to below the electrode of the phiV4 at a time t8 (not shown in the figure) and, at the next time t1 (not shown in the figure), signal electric charges Q1 and Q2 and the charges of Q3 and Q4 are mixed below the electrodes of the phiV1 and phiV4, respectively. At times t10-t13 (not shown in the figure), the electric charges of two pieces of transfer electrodes are transferred in the transferring direction.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a solid-state imaging device using an interline charge-coupled device type solid-state imaging device (hereinafter abbreviated as IL-COD).

Conventional configurations and their problems In recent years, research and development of solid-state imaging devices as new U71 imaging devices have been actively conducted, and they are rapidly reaching the stage of practical use.

A television camera using a solid-state image sensor has many characteristics compared to a conventional image pickup tube type television camera, such as a long life, high robustness, no burn-in, and easy handling.

The solid-state image sensor is a CCD type that obtains signal charges from photoelectric conversion elements arranged in an array by transferring them.

There are many methods, such as a MOS type, in which the position of a photoelectric conversion element is addressed and a signal is read out using a scanning pulse output from a shift register arranged in the vertical and horizontal directions. Among these, solid-state image sensors used in television cameras are interline CCD m
Solid-state imaging devices (IL-COD) are considered to be the most advantageous.

The configuration and operation of IL-COD will be described below with reference to FIGS. 1 to 4.

In FIG. 1, 1 is a photodiode as a photoelectric conversion element, 2 is a vertical transfer register, and this vertical transfer register is constituted by a vertical transfer gate (3,4°6.6). Reference numeral 7 denotes a signal readout gate, which is common to vertical transfer gates 3 and 5 due to equal constraints. 8 is a vertical transfer pulse supply terminal. 9 is a horizontal transfer register, and this horizontal transfer register is composed of horizontal transfer gates 10 and 11. 12 is a horizontal transfer pulse supply terminal. Reference numeral 13 denotes a charge detection section, which converts the transferred signal charge into a signal voltage. The charge detection unit 13 normally has a floating diffusion 7 block (Ftoating
Diffusion Amptifier). 14 is a signal output terminal.

The operation of the IL-COD configured as above will be explained next.

Photodiode 1id Photoelectrically converts incident light from an object to obtain a signal charge. The signal charge received by the photoelectric conversion is transferred to the vertical transfer register 2 via the signal readout gate 7.
After being read into the vertical transfer gates constituting the , the data is sequentially transferred in the vertical direction, that is, in the direction of the horizontal transfer register 9, by the vertical transfer pulse supplied from the vertical transfer pulse supply terminal 8, and the horizontal transfer register 9 is transferred one horizontal line at a time. is loaded into. The signal charge read into the horizontal transfer register is
The horizontal transfer pulses supplied from the horizontal transfer pulse supply terminal 12 are sequentially transferred to the charge detection section 13, converted into voltage by the charge detection section 13, and obtained as a point-sequential signal from the signal output terminal 14.

A television signal is obtained by signal processing the point 1 signal obtained by the method described above using an electric circuit.

FIG. 2 shows a plan view of the light receiving section of the IL-COD. In FIG. 2, parts having the same functions as those in FIG. 1 are given the same numbers. In FIG. 2, 1 is a photodiode, 2 is a vertical transfer register, and 3 to 6 are vertical transfer gates, and the vertical transfer register has a four-phase CCD configuration. 3 is ψV3, 4 is ψv4, 5 is ψv1, 6
is ψv2.

7 is a signal readout gate, and the signal readout gate 7 is connected to a vertical transfer gate 6 corresponding to the photodiode 1.
．． 4, that is, ψV2. It is provided in part in common with ψv4. Reference numeral 16 denotes a channel stopper for separating both systems in the horizontal direction (actually, it is also installed around the photodiode in areas other than the readout gate section).

Next, the relationship among the vertical transfer register, photodiode, signal readout gate, etc. will be explained using FIGS. 3a and 3b.

FIG. 3 is a sectional view taken along the line A-A' shown in FIG. 2.

In FIG. 3a, parts having the same functions as those in FIGS. 1 and 2 are given the same numbers.

In FIG. 3a, the solid-state image sensor is mounted on an n-type substrate 16 at
On top of the layer 17 epitaxially grown, an n4 layer 1 is provided to form a photodiode with a PN junction. 6 is a vertical transfer gate, and the vertical transfer gate is n
18. p+) is located above fJ7. 7 is a signal readout gate, and a buried channel type COD, that is, a vertical transfer register 2 is constructed at the junction between the n layer 18 and the p layer 17. Reference numeral 19 denotes a light-embedding aluminum wiring for preventing incident light from the object from being irradiated onto parts other than the photodiode section 1 and generating suspicious signals such as smear. Here, a reverse bias voltage is applied between the substrate 16 and the epitaxial layer 17 by a power source 20.

In addition, the diffusion layers 1, 7, 8, and 13 and the transfer electrode 6 are insulated with silicon oxide (SiO2) 21, and the surface of the element is covered with phosphorus glass (PSC;) 22 for protection. . FIG. 3 is a diagram showing an outline of the buttons/rings of each part in FIG. 3a. In Figure 3, the solid line potential diagram is a potential diagram during vertical transfer. The potential of the channel stopper region 16 is always constant. The potential of the photodiode section 1 takes a value between a potential vA in a dark state and a potential VB when signal charges are full after receiving incident light.

The potential of the vertical transfer stage 18 takes a value between the potential Vc when no vertical transfer pulse is applied to the vertical transfer gate 6 and the potential VD when the vertical transfer pulse is applied. The potential of the signal readout gate 7 is the potential E when the vertical transfer pulse is not applied to the vertical transfer gate 6, and the potential 7 when the vertical transfer pulse is applied.
The value is between 10 and 10.

Signal charges in the vertical transfer stage 18 are transferred between potentials vc and VD.

Next, the potential when reading the signal charge of the photodiode 1 into the vertical transfer stage 18 will be explained.

To read signal charges into the vertical transfer stage 18, a signal read pulse is applied to the vertical transfer gate 6 during the vertical retrace period. If a signal readout pulse that is sufficiently larger than the vertical transfer pulse is applied to the vertical transfer gate 6, the potential of the signal readout gate 7 and the vertical transfer stage 18 becomes the potential shown by the broken line in FIG. That is, the potential of the signal readout gate is VG, and the potential of the vertical transfer stage 18 is H, and 1. The signal charge accumulated in the photodiode 1 is read out to the vertical transfer stage 18 only during the period when the signal readout pulse is applied. I with the above configuration
L-CCDK Vertical transfer pulses ψv1 to ψV shown in Figure 4
4 is supplied from the vertical transfer pulse supply terminal 8 shown in FIG. , reads out the signal of the photodiode of the horizontal line whose signal readout gate and ψv4 are common. Therefore, by subjecting the signal direct voltage obtained from the signal output terminal 14 to signal processing using an electric circuit, it is possible to obtain a television signal subjected to 2: interlaced scanning. Here, among the vertical transfer pulses shown in FIG. 4, the A pulse shown at ψv2 and the B pulse shown at ψv4 are signal readout pulses.

However, two problems arise when 2:1 interlaced scanning is performed with the above-described vertical transfer pulse relationship.

The first problem is the occurrence of afterimages.
The reason for this is that, as is clear from Figure 4, the signal charge accumulation time in the photodiode is 2 fields Jυ], but the signal charge is read out every other horizontal line and every field. be.

Therefore, when the television camera is panned during imaging, an afterimage occurs in which the signal charge after one field is read out, and the edges of the image appear double.

The second problem is the occurrence of interlace flicker. In a general image pickup tube such as a vidicon, the scanning beam is approximately circular, and the diameter of the scanning beam is wider than the original scanning line width. scans across both fields. Note that the actual scanning beam is much larger and the electron density has a glass distribution with respect to the beam center.

Therefore, the boundaries between scanning lines remain blurred. That is,
The MTF in the vertical direction is less than or equal to the number of vertical lines.

However, in the case of a solid-state image pickup device, as shown in FIG. 2, the photodiodes 1 are arranged in a completely dispersed manner, so that the boundaries between scanning lines do not become blurred as in an image pickup tube. That is, MTFid in the vertical direction hardly decreases even when the number of vertical scanning lines approaches. Therefore, when you capture an image of an object with no vertical correlation in which the luminance signal changes greatly in the vertical direction and view it on a monitor TV, the signal changes greatly from field to field in the areas of the object where there is no vertical correlation. This appears as an upward flicker, resulting in unsettling image quality.

Therefore, as a method to solve the above-mentioned drawbacks, the accumulation period of the signal charge in the photodiode is set to one field period, and the signal readout is performed for each field to eliminate the occurrence of afterimages. The signal charges of the photodiodes are mixed and read out,
An IL-COD driving method that increases the apparent aperture ratio of the photodiode by shifting one line for each field, that is, does not generate interlace flicker, similar to the relationship between the scanning line of an image pickup tube and an electron beam. Proposed.

Next, a conventional example of a solid-state imaging device using the above-mentioned IL-CCD driving method will be explained with reference to FIGS. 6 and 7.

FIG. 6 shows a vertical transfer pulse of IL-COD in a conventional example. ψv11. ψv3 is the same as the vertical transfer pulse for frame readout shown in FIG. 4, but ψ■2. ψv
4 is the first. A signal readout pulse is provided for both the second field. The vertical transfer pulse shown in FIG. 6 is connected to the vertical transfer pulse supply terminal of the IL-COD shown in FIG.
FIG. 7 shows an outline of the potential at the vertical transfer gates ψV123 to ψv426 forming the vertical transfer stage when applied to the supply terminals 1 to ψ4.

Figure 7 shows the potential of the E-8' cross section shown in Figure 2, and each potential diagram is from t1 to t2 shown in Figure 6.
o at each time. Here, the mechanism of reading signals from the photodiode to the vertical transfer stage has been explained using FIG. 3, and will therefore be omitted. Light-shielding aluminum wiring and surface protection film (PS
G) etc. are omitted.

In FIG. 7, 8 is a vertical transfer pulse supply terminal, 18 is an n-diffusion layer constituting a vertical transfer stage, and 23 is a φv1 electrode 24.
is ψ■2 electrode, 26 is ψv3 electrode, 26 is ψv4 electrode,
21 is an insulating layer (
SiO2).

Next, the operation when the vertical transfer pulses ψv1 to ψ■4 are applied to the vertical drive pulse supply terminal 8 will be explained based on FIG.

First, the potential at tl during the vertical 4% line period of the first field in FIG. 6 has the form shown in 11 in FIG. 7a, but no signal charge exists at this time. The barriers shown in the diagram showing the potential in Figure 7 are those that occur during the manufacturing process of solid-state imaging devices, such as misalignment of masks when forming vertical and transfer electrodes, and during the n-layer diffusion process. In this conventional example, ψ
(2) It is assumed that a barrier occurs at the junction between the 1st electrode and the ψv2 electrode. This potential barrier can be ignored due to fringe effects etc. in the part where the ψ■ group electrode voltage is applied and the potential is high, so in the potential diagram in FIG. 7, ψv1. A case where a voltage is applied to both or one of the ψv2 electrodes is not shown. The barrier would not occur if the solid-state image pickup device was manufactured in a completely ideal manner, but in the current semiconductor IC process technology, there is a limit to mask alignment accuracy, etc., and most of the barrier does not occur. Next, the potential at time t2 takes the form shown at 12 in FIG. 7a.

That is, by applying a signal readout pulse to the electrode φ■2, the signal charge Q1 of PDl, Pf)3 shown in FIG.
．． Q3 (signal charge in this case is an electron) is read into the ψv2 electrode electrode valve socket. (Here, the mechanism of reading from the photodiode into the packet under the ψ■ electrode is the third one.
The potential at time t3 of the 0th order has the form shown at t3 in FIG. 7a. At this time ψ
(2) The charge under the 2nd electrode is diffused under the φV27ψv3 electrode, and furthermore, the ψV2 electrode water level goes from the state of t2 to the state of t3.

In order to change, a vector in the direction of arrow A shown at t3 is given to the charge, and as a result, a part of the signal charge Q1 becomes φv4
The electrode valve is inserted. Next, at time t4, ψV31
Since a voltage is applied to the φv4 electrode, the potential takes the form shown at t4 in FIG. 7a.

In other words, 1 in the charge transfer direction from the potential state of t
Since the signal charge Q1 is transferred by the number of electrodes, the signal charge Q1 is concentrated in the packet below the ψv3 +ψ■4 electrode.

The potential at time t5 takes the form shown at t6 in FIG. 7a, and the signal charges Q2, . Q4 is ψv4 electrode water is included.

At this time, signal charge Q1. Although Q2 is mixed, it is separated as shown in the figure for convenience of explanation. Next, the potential at time t6 takes the form shown at t6 in Figure 7a, but since the ψv4 electrode water tension changes greatly from the state at t6 to the state at 70, the vector in the direction of the arrow shown at t6 becomes the charge. As a result, the signal charge Q1. Part of Q3 is ψv2
The electrode valve is inserted. At this time, since there is a barrier at the junction surface of the φV11ψV2 electrodes, the signal charge does not move at the bottom of the ψv1 electrode. At time t7 in the 0th order, ψv
Since a voltage is applied to the 2°ψv3 electrode, the state at time t6 becomes a state in which the charge is transferred by one electrode in the opposite direction to the charge transfer direction, as shown in FIG. 7, and the signal charge Q1. Q2
ba ψ, v2. Gather under the ψv3 electrode. From this state, as shown from time t8 to t1°, the electrode 1 moves toward the charge transfer direction.
Transfer in individual pieces.

Next, the operation in the second field will be explained.

tll during the vertical retrace period in the second field.

The potential at t12 is tll in FIG. 7C.

The operation at t12 is the same as in the first field, so the explanation will be omitted. At time t13, the ψv4 electrode water tension changes greatly from the state of t12 to the state of t13, so the vector in the direction of arrow A shown at t13 is applied to the load, but since there is a barrier at the ψV1 + ψv2 junction, the signal charge At 0 time t14, where ψv2 does not move downward to the two main electrodes, one electrode is transferred in the traveling direction from time t13. Next, at time t15, ψ
v2 Signal charge Q1. Load Q3. Next, the potential at time t16 takes the form shown at t16 in FIG. As a result, a part of the signal charge is injected into the ψ■4 electrode water. Next, at time t1□, the ψV2 electrode water tension falls and the ψ■4 electrode water tension rises, giving the signal charge the vector shown in C. Therefore, the signal charge that was under the ψV4 electrode at '16 At t1□, Figure 7 d
Move below the ψV3 electrode as shown in .

Next, at time t18, ψv1. A voltage is applied to the ψv2 electrode, resulting in the potential shown at t18, but at this time, the signal charge existing under the ψV41ψ■1 electrode at t1□ becomes ψ■1. It is transferred under the ψv2 electrode, but t
The signal charges that have descended to the ψ■3 main three electrodes at 1□ do not move and remain there even at t18. Next time t19
When it becomes ψ■2. Since a voltage is applied to the ψv3 electrode, at time t18, the charge existing under the ψ■3 main 3 electrode and the charge existing under the ψv2 main 2 electrode are mixed. Thereafter, from time t2°, the charges are sequentially transferred in the signal charge transfer direction and read out as signal charges.

However, as is clear from the angle 110''2 in FIG. 7, the signal charges are mixed into almost the same signal components in both the first and second fields.

Therefore, in this conventional example, the accumulation time of the signal charge in the photodiode is one field period, and the signal charge is read out every field, so that no afterimage occurs.However, as mentioned above, the first . Since substantially the same photodiode signals are mixed and read out in both the second field, the number of pixels in the vertical direction is equal to i. Furthermore, since the signal components in the first and second fields are almost the same, when an object whose brightness signal changes in the vertical direction is imaged and viewed on a monitor TV, at the vertical edge portion where the brightness signal changes in the vertical direction, This appears as jitter, resulting in inconsistent image quality.

Therefore, the driving of the above-mentioned IL-CCD has not achieved its initial purpose.

OBJECTS OF THE INVENTION The present invention solves the above-mentioned conventional problems and provides a solid-state imaging device that has no afterimage, no interlace flicker, and almost no deterioration in resolution in the horizontal and vertical directions.

Structure of the Invention In order to achieve the above object, the present invention provides a structure in which a signal readout gate arranged corresponding to a photoelectric conversion element and a predetermined transfer gate among the transfer gates forming a vertical transfer register are equivalently common to each other. In the connected solid-state imaging device, a signal readout pulse is fielded so that a potential well (packet) is generated in the charge transfer direction of the vertical transfer register when signal charges are inserted from the photoelectric conversion element to the vertical transfer register. After applying the signals to the vertical transfer gates and mixing the signal charges of vertically adjacent photoelectric conversion elements, the signal charges are transferred vertically and horizontally and the signals are read out in time series to eliminate afterimages and interlace flicker. - It is possible to obtain a solid-state imaging device with good vertical resolution.

DESCRIPTION OF EMBODIMENTS An embodiment of the solid-state imaging device according to the present invention will be described below with reference to FIG.
This will be explained using FIG. 9.

FIG. 8 shows a vertically rotated X-pulse of the IL-COD according to the present invention. ψV1+ψV21 in the first field
Each pulse of ψV31ψv4 corresponds to ψV3'ψv4. in the second field. Each is equal to ψV1rψ■2. For each field, a signal readout pulse is provided at ψV2'ψv4. The vertical transfer pulse shown in FIG.
FIG. 9 shows an outline of the potential in the vertical transfer gates ψ123 to ψv426 forming the vertical transfer stage when the voltage is supplied to the terminals 1 to 4. In FIG. 9, the presence of potential barriers of each electrode, etc. are the same as those explained in FIG. 7 of the conventional example, so a description thereof will be omitted.

The outline of the potential at time tn shown in FIG. 8 is shown in correspondence with FIG. 9 tn.

First, at time t1, a packet is generated under the ψV2jψ■3 electrode as shown in FIG. 9a, but no signal charge exists. At time t2, the signal charge of the photodiode PD1°Pi)3 sinks under the two main electrodes ψV2.

At time t3, the signal charge Q1 under the ψ■3 electrode. Q3iJ,
Electrode ψ■2. Since the electric charge is diffused under the ψv3 electrode and the electrode water tension of the ψv2 electrode changes greatly from the state of 12 to the state of t3, a vector in the direction of arrow A shown in 13 is given to the charge, so a part of Ql and Q3 is ψv4 electrode electrode valve is inserted. At time t4, the packet is ψ■2~ψv
Signal charge Q1. All Q3s are stored in the packet again. Signal charges are transferred in the charge transfer direction from time t6 to t7. At the time when time t5 changes to time t7, transfer for one transfer electrode is performed.

At time t8, signal charges Q of PD'2, PO2, and PO2 (not shown). , Q2. Q4 is read under the ψ■4 electrode. Next, at time t9, signal charges Q1 and Q2 are placed under the ψV11ψv4 electrode. A mixture of Q3 and Q4 exists. Here, since the potential under the ψ■4 electrode changes greatly from t8 to t9, a vector in the direction of the mouth shown at t9 is given, but there is a barrier between ψ■1°ψ■4,
Therefore, the signal charge is not sent down to the ψV2 main two electrodes. During time t1° to t13, charges for two transfer electrodes are transferred in the transfer direction. From then on, due to the transfer,
It is sequentially transferred vertically and horizontally and obtained as a signal output.

Next, the operation in the second field will be explained.

Time t14. t1. The potential at is the same as the operation at time t1°t2. At time ti6, ψ■4
Since the potential under the electrode changes greatly from the state at t16 to the state at t16, a vector in the direction of arrow A shown at t16 is given to the charge, but ψ■1. At the ψ■2 junction, the signal charge Q0.Q2 becomes ψ
It does not move below the v2 electrode. Next time 116~t
At 2°, the signal charge Q0. Q2. Transfer Q4 to gate 2
Charges are transferred in the transfer direction. At the primary time t21, the photodiode PD1. Signal charge Q1 of PD3.
Read Q3 under the ψv2 electrode, at t22 ψ■
Since the potential under the two electrodes changes greatly, a vector in the direction of the arrow shown at t22 is given to the signal charge,
As a result, a part of the signal charge is pushed under the ψ■4 electrode.

Next, in '23, a voltage is applied to one and four electrodes, so the signal charge is Q. Ql, Q2Q3 is again ψv2 ~ ψ■4
Accumulated in packets under the electrodes. Thereafter, after being transferred from t24 to t25, the signal is sequentially transferred vertically and horizontally by a transfer pulse and obtained as a signal output.

Here, as is clear from 1131t26 in FIG. 9, in the first field, PDl and PO2°PO3 and PO
2 signal charges Q1 and Q2, Q3 and Q4 are read out, and H1PD○(
(not shown), PDl, Pv2 and PO3 signal charges Q. and Ql, Q2 and Q3 [Read only the words mixed.

In the solid-state imaging device, the mixed and read signals are processed by an electric circuit to obtain a television signal.

As explained above, by using the vertical transfer pulse according to the present invention, signal charges of two vertically adjacent horizontal lines can be completely mixed and then read out.

In the above specific example, a 4-phase CCD was used for the vertical register, but the same applies to a 3-phase CCD.

Effects of the Invention As described above, according to the present invention, the accumulation time of the signal charge in the photodiode is one field period, and the signal readout is also done for each field, so that the afterimage described in the conventional example does not occur at all.

In addition, since the signal charges of the photodiodes of two vertically adjacent horizontal lines are mixed and read out, the apparent aperture ratio of the photodiode becomes wider, that is,
The relationship between the scanning tube of the image pickup tube and the electron beam is similar, and there is no interlace flicker.

Furthermore, when mixing the signal charges of the photodiodes, the first
Since the signal charges are mixed in the field and the second field in an interlaced manner, a vertical resolution equivalent to that of a close-up image can be obtained isometrically, so that the vertical resolution is not a problem at all.

[Brief explanation of the drawing]

Figure 1 is the I L-COD equivalent circuit, Figure 2 is the I L-C
A plan view of the OD, FIG. 3a is a cross-sectional view of the IL-COD, b is a diagram showing an outline of the potential of each part in FIG. 3a, and FIG. 4 is a diagram showing the vertical transfer pulse of the conventional IL-COD. Fifth
The figure shows the relationship between the scanning line and the electron beam in the image pickup tube, Figure 6 shows the vertical transfer pulse of the conventional example, and Figure 7 &
,b. c and d are diagrams showing the potential of a conventional vertical transfer stage;
FIG. 8 is a diagram showing vertical transfer pulses in an embodiment of the solid-state imaging device of the present invention, and FIGS. 9a and 9b. c and d are diagrams showing the potential of the vertical transfer stage in an embodiment of the solid-state imaging device of the present invention.01...
Photodiode (photoelectric conversion element), 2... Vertical transfer register, 3, 4, 6.6... Vertical transfer gate, 7... Signal readout gate, 8...
...Vertical transfer pulse input terminal, 9...Horizontal transfer register, 10.11...Horizontal transfer gate,
12...Horizontal transfer pulse input terminal, 13...
...charge detection section, 23 ψV1 electrode, 24...
・ψ■2 electrodes, 25...ψ■3 electrodes, 26・
...ψv4 electrode. Figure 1 11 □-v- = Figure 2 Figure 7 ('a' Transfer direction Figure 7 (b) 5-notch direction Figure 7 (C) 16 Transfer direction Figure 7 (1) lt, q Coconut 9 Fig. 9 (illustration direction flower 9 Fig. 9 (b) Fig. 9 (C) Transfer direction Fig. 9 (d-)

Claims (1)

[Claims] comprising a group of photoelectric conversion elements arranged in an array, a vertical transfer register consisting of a plurality of transfer gates and a horizontal transfer register consisting of a plurality of transfer gates, a signal readout gate arranged corresponding to the photoelectric conversion element; Of the transfer gates constituting the vertical transfer register, predetermined transfer gates are equivalently connected in common, and when reading signal charges from the photoelectric conversion element to the vertical transfer register, the potential is changed in the charge transfer direction of the vertical transfer register. A signal readout pulse is applied to the vertical transfer gate for each field so as to generate a well, and signals are obtained in time series by charge transfer after mixing the signal charges of vertically adjacent photoelectric conversion elements. solid-state imaging device.