JPH0560130B2 - - Google Patents

Info

Publication number
JPH0560130B2
JPH0560130B2 JP58142415A JP14241583A JPH0560130B2 JP H0560130 B2 JPH0560130 B2 JP H0560130B2 JP 58142415 A JP58142415 A JP 58142415A JP 14241583 A JP14241583 A JP 14241583A JP H0560130 B2 JPH0560130 B2 JP H0560130B2
Authority
JP
Japan
Prior art keywords
program counter
instruction
machine language
contents
address
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP58142415A
Other languages
English (en)
Japanese (ja)
Other versions
JPS6033633A (ja
Inventor
Yoichi Kawabata
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Canon Inc
Original Assignee
Canon Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Canon Inc filed Critical Canon Inc
Priority to JP58142415A priority Critical patent/JPS6033633A/ja
Publication of JPS6033633A publication Critical patent/JPS6033633A/ja
Publication of JPH0560130B2 publication Critical patent/JPH0560130B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/32—Address formation of the next instruction, e.g. by incrementing the instruction counter
    • G06F9/322—Address formation of the next instruction, e.g. by incrementing the instruction counter for non-sequential address
    • G06F9/325—Address formation of the next instruction, e.g. by incrementing the instruction counter for non-sequential address for loops, e.g. loop detection or loop counter

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Executing Machine-Instructions (AREA)
JP58142415A 1983-08-05 1983-08-05 電子計算機 Granted JPS6033633A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58142415A JPS6033633A (ja) 1983-08-05 1983-08-05 電子計算機

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58142415A JPS6033633A (ja) 1983-08-05 1983-08-05 電子計算機

Publications (2)

Publication Number Publication Date
JPS6033633A JPS6033633A (ja) 1985-02-21
JPH0560130B2 true JPH0560130B2 (enrdf_load_stackoverflow) 1993-09-01

Family

ID=15314798

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58142415A Granted JPS6033633A (ja) 1983-08-05 1983-08-05 電子計算機

Country Status (1)

Country Link
JP (1) JPS6033633A (enrdf_load_stackoverflow)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61281339A (ja) * 1985-03-29 1986-12-11 Fujitsu Ltd 情報処理装置の命令分岐方式

Also Published As

Publication number Publication date
JPS6033633A (ja) 1985-02-21

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