JPH0559671B2 - - Google Patents

Info

Publication number
JPH0559671B2
JPH0559671B2 JP59150363A JP15036384A JPH0559671B2 JP H0559671 B2 JPH0559671 B2 JP H0559671B2 JP 59150363 A JP59150363 A JP 59150363A JP 15036384 A JP15036384 A JP 15036384A JP H0559671 B2 JPH0559671 B2 JP H0559671B2
Authority
JP
Japan
Prior art keywords
voltage
output
power
inverter
active power
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP59150363A
Other languages
Japanese (ja)
Other versions
JPS6130967A (en
Inventor
Yasushi Honma
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Meidensha Electric Manufacturing Co Ltd
Original Assignee
Meidensha Electric Manufacturing Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Meidensha Electric Manufacturing Co Ltd filed Critical Meidensha Electric Manufacturing Co Ltd
Priority to JP15036384A priority Critical patent/JPS6130967A/en
Publication of JPS6130967A publication Critical patent/JPS6130967A/en
Publication of JPH0559671B2 publication Critical patent/JPH0559671B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H02GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02MAPPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M7/00Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
    • H02M7/42Conversion of dc power input into ac power output without possibility of reversal
    • H02M7/44Conversion of dc power input into ac power output without possibility of reversal by static converters
    • H02M7/48Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Inverter Devices (AREA)

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は無停電電源装置などに用いるインバー
タの並列運転装置に関するものである。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a parallel operation device for inverters used in uninterruptible power supplies and the like.

〔従来の技術〕[Conventional technology]

一般に、無停電電源装置ではインバータによつ
て蓄電池電圧を交流電圧に変換して出力するよう
に構成しているが、負荷容量が大きい場合、この
ような無停電電源装置を並列運転することがあ
る。
Generally, uninterruptible power supplies are configured to use an inverter to convert storage battery voltage to AC voltage and output it, but if the load capacity is large, such uninterruptible power supplies may be operated in parallel. .

このようなインバータを有する無停電電源装置
の並列運転に際し、各装置間で制御信号の送受を
行なわず、それぞれの装置に割当てられた出力電
力の範囲内で自己の出力電力を制御して運転する
個別制御方式という並列運転方法がある。
When operating uninterruptible power supplies with such inverters in parallel, each device does not send or receive control signals, and operates by controlling its own output power within the range of output power assigned to each device. There is a parallel operation method called the individual control method.

この個別制御方式は、具体的には各無停電電源
装置毎に制御装置を設け、この制御装置によつて
有効電力と無効電力とを検出し、有効電力の検出
値によつて出力周波数を制御し、また無効電力の
検出値によつて出力電圧値を制御することによ
り、負荷に対する電力を分担し合うように構成さ
れる。
Specifically, in this individual control method, a control device is provided for each uninterruptible power supply, and this control device detects active power and reactive power, and controls the output frequency based on the detected value of active power. In addition, by controlling the output voltage value based on the detected value of reactive power, the power to the load is shared.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

ところが、この個別制御方式においては各装置
相互間における有効電力の設定値に誤差がある
と、特定の装置の有効電力の供給量が増加し、他
の装置においては有効電力が逆に流し込まれると
いう現象が生じ、これによつてインバータの直流
入力電圧が上昇し、正常な並列運転が不可能にな
るという問題点があつた。このような問題点は無
停電電源装置の並列運転時に限らず、インバータ
の並列運転時にも生じていた。
However, in this individual control method, if there is an error in the active power settings between each device, the amount of active power supplied to a specific device will increase, and the active power will be reversed to other devices. This phenomenon caused the DC input voltage of the inverter to rise, making normal parallel operation impossible. Such problems occur not only when uninterruptible power supplies are operated in parallel, but also when inverters are operated in parallel.

〔問題点を解決するための手段、作用〕[Means and actions for solving problems]

本発明は上記のような問題点を解決するために
なされたもので、インバータの入力電圧が所定値
より上昇したことを検出する検出手段を設け、こ
の検出手段の検出出力によつて出力周波数を上昇
側に制御することにより、有効電力の分担を平衡
に維持して正常な並列運転を継続し得るインバー
タの並列運転装置を提供するものである。
The present invention has been made to solve the above-mentioned problems, and includes a detection means for detecting that the input voltage of the inverter has risen above a predetermined value, and the output frequency is determined by the detection output of this detection means. An object of the present invention is to provide an inverter parallel operation device that can maintain normal parallel operation by maintaining the share of active power in a balanced manner by controlling the inverters to the rising side.

〔実施例〕〔Example〕

以下、実施例に基づき本発明を詳細に説明す
る。
Hereinafter, the present invention will be explained in detail based on Examples.

第1図は本発明を適用した無停電電源装置の一
実施例を示すブロツク図であり、ここでは2台の
無停電電源装置1,2を並列運転し、負荷3に電
力を供給する場合の例を示している。第1図にお
いて、無停電電源装置1,2は装置1を代表して
示しているように、交流入力電圧Eを整流回路1
1によつて整流し、その整流後の直流電圧をコン
デンサ12で平滑化し、さらに平滑化した直流電
圧をインバータ13によつて所定の電圧、周波数
の交流電圧に変換して出力するように構成されて
いる。そして、各装置1,2からの出力電圧は開
閉器4,5を介して負荷3に供給されている。
FIG. 1 is a block diagram showing an embodiment of an uninterruptible power supply to which the present invention is applied. Here, two uninterruptible power supplies 1 and 2 are operated in parallel to supply power to a load 3. An example is shown. In FIG. 1, uninterruptible power supplies 1 and 2 convert AC input voltage E into rectifier circuit 1, as shown in FIG.
1, the rectified DC voltage is smoothed by a capacitor 12, and the smoothed DC voltage is further converted into an AC voltage of a predetermined voltage and frequency by an inverter 13 and output. ing. The output voltage from each device 1, 2 is supplied to a load 3 via switches 4, 5.

一方、各装置1,2の出力有効電力Pおよび出
力無効電力Qをそれぞれの分担量に応じて制御す
る制御装置6,7は、制御装置6を代表して示し
ているように、有効−無効電力検出部60(以下
PQ検出部と略称する)、周波数制御部61、電圧
制御部62、ゲートロジツク部63とから構成さ
れ、変圧器8を介して検出した負荷3への供給電
圧EOと変流器9,10によつて検出した負荷電
流IOとによつて各電源装置1,2の有効電力Pと
無効電力QをPQ検出部60で検出し、この有効
電力Pの検出値に基づいてゲートロジツク部63
からインバータ13に与えるゲート信号の周波数
を周波数制御部61が制御し、また、無効電力Q
の検出値と出力電圧の設定値ESとに基づいてイン
バータ13のゲート信号を電圧制御部62が制御
し、各電源装置1,2が有効電力Pと無効電力Q
とを1対1で分担して負荷3に供給できるように
構成されている。
On the other hand, control devices 6 and 7, which control the output active power P and output reactive power Q of each device 1 and 2 according to their respective assigned amounts, have an effective-invalid state, as shown in the control device 6 as a representative. Power detection unit 60 (hereinafter referred to as
It is composed of a frequency control section 61, a voltage control section 62, and a gate logic section 63. The active power P and reactive power Q of each power supply device 1, 2 are detected by the PQ detection unit 60 based on the detected load current I O , and the gate logic unit 63 detects the active power P based on the detected value of the active power P.
The frequency control unit 61 controls the frequency of the gate signal given to the inverter 13 from
The voltage control unit 62 controls the gate signal of the inverter 13 based on the detected value and the set value E S of the output voltage, and each power supply device 1, 2 controls the active power P and the reactive power Q.
It is configured such that it can be distributed to the load 3 on a one-to-one basis.

この場合、並列運転開始時には1つの電源装置
1が先に動作を開始し、この装置1の出力電圧位
相に後続の装置2の出力電圧位相が同期した時点
で開閉器4が閉成される。この位相同期のための
制御は、図示しない位相同期回路によつて行なわ
れる。
In this case, at the start of parallel operation, one power supply device 1 starts operating first, and the switch 4 is closed when the output voltage phase of this device 1 is synchronized with the output voltage phase of the subsequent device 2. Control for this phase synchronization is performed by a phase synchronization circuit (not shown).

ところで、この構成において、電源装置2の有
効電力Pの分担量が一方の電源装置1の分担量よ
りも多くなると、その差に相当する有効電力がイ
ンバータ13のトランジスタTRに逆並列接続さ
れたダイオードDを介して直流側に流し込まれて
直流電圧が上昇してしまう。
By the way, in this configuration, when the share of the active power P of the power supply device 2 becomes larger than the share of the active power P of the power supply device 1, the active power corresponding to the difference is transferred to the diode connected in antiparallel to the transistor TR of the inverter 13. It flows into the DC side via D and the DC voltage increases.

そこで、本発明では第2図に詳細に示すよう
に、制御装置6,7内にインバータ13の入力電
圧が所定値より上昇したことを検出する検出回路
64を設け、この検出回路64の検出出力によつ
て有効電力Pを上昇側に制御するように構成して
いる。
Accordingly, in the present invention, as shown in detail in FIG. The configuration is such that the effective power P is controlled to the rising side.

すなわち、インバータ13の直流出力電圧を直
流/直流コンバータ640によつて所定電圧まで
降圧させ、このコンバータ640の出力電圧VD
と設定器641で設定された設定電圧VSとを比
較器642で比較し、VD>VSとなつた場合、比
較器642から周波数制御部61の演算増幅器6
10の入力に所定の電圧Pαを加算する。この演
算増幅器610には有効電力演算部611から有
効電力Pの検出値を表わす電圧POが入力され、
その出力は出力周波数を制御する電圧制御型発振
器612に供給されている。
That is, the DC output voltage of the inverter 13 is stepped down to a predetermined voltage by the DC/DC converter 640, and the output voltage of this converter 640 V D
A comparator 642 compares the set voltage VS set by the setting device 641, and if V D > VS , the comparator 642 outputs the voltage to the operational amplifier 6 of the frequency control section 61.
A predetermined voltage Pα is added to the input of 10. A voltage P O representing a detected value of active power P is inputted to this operational amplifier 610 from an active power calculation section 611.
Its output is fed to a voltage controlled oscillator 612 which controls the output frequency.

従つて、VD>VSとなつた場合、演算増幅器6
10の入力には比較器642の出力電圧Pαが加
算されることになり、電圧制御型発振器612の
出力信号周波数は電圧Pαに相当する分だけ高く
なる。この電圧制御型発振器612の出力信号は
ゲートロジツク部63に供給される。これによ
り、インバータ13の出力周波数は電圧Pαに相
当する分だけ高くなり、有効電力Pも増加する。
Therefore, when V D > V S , the operational amplifier 6
The output voltage Pα of the comparator 642 is added to the input of the voltage control type oscillator 612, and the output signal frequency of the voltage controlled oscillator 612 increases by an amount corresponding to the voltage Pα. The output signal of this voltage controlled oscillator 612 is supplied to a gate logic section 63. As a result, the output frequency of the inverter 13 increases by an amount corresponding to the voltage Pα, and the effective power P also increases.

なお、VD≦VSの条件下では、電圧制御型発振
器612の出力信号周波数は有効電力Pの検出値
に反比例して増減し、予め定められた分担量の有
効電力Pが送出されるように制御される。
Note that under the condition of V D ≦ V S , the output signal frequency of the voltage controlled oscillator 612 increases or decreases in inverse proportion to the detected value of the active power P, so that a predetermined share of the active power P is sent out. controlled by.

一方、電圧制御部62は周波数制御部61の無
効電力演算部613で検出された無効電力Qの検
出値、変圧器8で検出した出力電圧EOおよび出
力電圧の設定値ESを電圧制御用増幅器620で加
減算し、その結果を比較器621に入力し、電圧
制御型発振器612の出力信号周波数に同期して
三角波発生器622から発生される三角波と比較
し、電圧増幅器620の出力電圧が三角波の電圧
値より小さい範囲の間論理“1”の信号をゲート
ロジツク部62に与えることにより、出力電圧
EOを制御するように構成されている。
On the other hand, the voltage control unit 62 uses the detection value of the reactive power Q detected by the reactive power calculation unit 613 of the frequency control unit 61, the output voltage E O detected by the transformer 8, and the set value E S of the output voltage for voltage control. The amplifier 620 performs addition and subtraction, and the result is input to a comparator 621 and compared with a triangular wave generated from a triangular wave generator 622 in synchronization with the output signal frequency of the voltage controlled oscillator 612. By applying a logic "1" signal to the gate logic unit 62 during a range smaller than the voltage value of
Configured to control E O.

従つて、本実施例によれば、有効電力Pの分担
量に不平衡が生じたとしてもこの不平衡は検出回
路64の検出出力によつて補正されるため、2つ
の無停電電源装置1,2の正常な並列運転を継続
することができる。
Therefore, according to this embodiment, even if an unbalance occurs in the shared amount of the active power P, this unbalance is corrected by the detection output of the detection circuit 64, so that the two uninterruptible power supplies 1, Normal parallel operation of the two can be continued.

なお、実施例において並列運転される無停電電
源装置の数は2つとしたが、これ以上でも同様に
制御することができる。さらに、無停電電源装置
に限らず、インバータの並列運転にも適用できる
ことは言うまでもない。
In addition, although the number of uninterruptible power supplies operated in parallel in the embodiment is two, it is possible to control the number of uninterruptible power supplies in the same manner with more than two. Furthermore, it goes without saying that the present invention can be applied not only to uninterruptible power supplies but also to parallel operation of inverters.

〔発明の効果〕〔Effect of the invention〕

以上の説明から明らかなように本発明によれ
ば、インバータや無停電電源装置を並列運転する
際に、有効電力の分担量が不平衡となつても直ち
に平衡関係に制御できるため、正常な並列運転を
継続させることができ、信頼性及び安定性を向上
させることが可能になるという優れた効果があ
る。
As is clear from the above description, according to the present invention, when operating inverters or uninterruptible power supplies in parallel, even if the shared amount of active power becomes unbalanced, it can be immediately controlled to a balanced relationship, so that normal parallel operation can be achieved. This has the excellent effect of allowing continuous operation and improving reliability and stability.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の一実施例を示すブロツク図、
第2図は第1図における制御装置の詳細な構成を
示すブロツク図である。 1,2……無停電電源装置、3……負荷、6,
7……制御装置、60……PQ検出部、61……
周波数制御部、62……電圧制御部、63……ゲ
ートロジツク部、64……検出回路。
FIG. 1 is a block diagram showing one embodiment of the present invention;
FIG. 2 is a block diagram showing the detailed configuration of the control device in FIG. 1. 1, 2... Uninterruptible power supply, 3... Load, 6,
7...Control device, 60...PQ detection section, 61...
Frequency control section, 62... Voltage control section, 63... Gate logic section, 64... Detection circuit.

Claims (1)

【特許請求の範囲】[Claims] 1 並列運転される複数のインバータのそれぞれ
に対応して設けられ、自己に対応したインバータ
から出力される有効電力と無効電力を検出し、有
効電力の検出値によつて出力周波数を制御し、無
効電力の検出値によつて出力電圧値を制御する制
御装置を備え、各インバータ毎に負荷に供給すべ
き有効電力と無効電力とを分担して並列運転する
インバータの並列運転装置において、インバータ
の直流電圧が所定値より上昇したことを検出する
検出手段を各制御装置に設け、この検出手段の検
出出力により出力周波数を上昇側に制御し、有効
電力の分担を平衡に維持して並列運転することを
特徴とするインバータの並列運転装置。
1 It is installed corresponding to each of multiple inverters operated in parallel, detects the active power and reactive power output from the corresponding inverter, controls the output frequency based on the detected value of active power, and controls the reactive power. In an inverter parallel operation device that is equipped with a control device that controls the output voltage value based on the detected power value, and that operates in parallel by sharing the active power and reactive power that each inverter should supply to the load, the inverter's DC Each control device is provided with a detection means for detecting that the voltage has risen above a predetermined value, and the output frequency is controlled to the rising side based on the detection output of this detection means, and the sharing of active power is maintained in balance for parallel operation. An inverter parallel operation device featuring:
JP15036384A 1984-07-19 1984-07-19 Parallel operation device of inverter Granted JPS6130967A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15036384A JPS6130967A (en) 1984-07-19 1984-07-19 Parallel operation device of inverter

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15036384A JPS6130967A (en) 1984-07-19 1984-07-19 Parallel operation device of inverter

Publications (2)

Publication Number Publication Date
JPS6130967A JPS6130967A (en) 1986-02-13
JPH0559671B2 true JPH0559671B2 (en) 1993-08-31

Family

ID=15495354

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15036384A Granted JPS6130967A (en) 1984-07-19 1984-07-19 Parallel operation device of inverter

Country Status (1)

Country Link
JP (1) JPS6130967A (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4693214B2 (en) * 2000-08-31 2011-06-01 東芝コンシューマエレクトロニクス・ホールディングス株式会社 Inverter device
DE10140783A1 (en) * 2001-08-21 2003-04-03 Inst Solare Energieversorgungstechnik Iset Device for the parallel operation of single or three-phase voltage sources

Also Published As

Publication number Publication date
JPS6130967A (en) 1986-02-13

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