JPH0937552A - Pwm converter - Google Patents

Pwm converter

Info

Publication number
JPH0937552A
JPH0937552A JP7182371A JP18237195A JPH0937552A JP H0937552 A JPH0937552 A JP H0937552A JP 7182371 A JP7182371 A JP 7182371A JP 18237195 A JP18237195 A JP 18237195A JP H0937552 A JPH0937552 A JP H0937552A
Authority
JP
Japan
Prior art keywords
current
component
phase
converter main
main circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP7182371A
Other languages
Japanese (ja)
Inventor
Kazuo Hayamizu
一夫 速水
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Meidensha Corp
Meidensha Electric Manufacturing Co Ltd
Original Assignee
Meidensha Corp
Meidensha Electric Manufacturing Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Meidensha Corp, Meidensha Electric Manufacturing Co Ltd filed Critical Meidensha Corp
Priority to JP7182371A priority Critical patent/JPH0937552A/en
Publication of JPH0937552A publication Critical patent/JPH0937552A/en
Pending legal-status Critical Current

Links

Landscapes

  • Supply And Distribution Of Alternating Current (AREA)
  • Rectifiers (AREA)

Abstract

PROBLEM TO BE SOLVED: To dispense with a large-scale transformer in a converter main circuit by forming a current control system in which the current commands of each phase obtained from a voltage control system are respectively compared with the input current detection signals of each phase of a converter main circuit. SOLUTION: In control devices 51 , 52 , as shown in the control device 52 the DC component of the current detection signal IV of a V-phase is adjusted by an offset adjustment value IOSET to pass it through an amplifier 73 , thereby obtaining a current detection signal IV1 in which the DC component is zero, and the current detection signal 1V1 is compared with the current command IV5 of a multiplier 11V. When a lag is generated in the switching time of the semiconductor element of converter main circuits 31 , 32 and a circulating current is generated between the main circuits 31 , 32 , the AC component and the DC component are detected by a Hall transformer connected to each phase and the DC component is controlled so as to be zero together with the AC component. As a result, the circulating current of AC and DC components between the converter main circuits 31 , 32 is suppressed and the DC component becomes zero and for that reason, the AC input side of the main circuit 31 , 32 dispenses with a transformer.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【発明の属する技術分野】本発明は、並列接続したPW
Mコンバータに係り、特に直流循環電流を抑制した制御
装置に関する。
TECHNICAL FIELD The present invention relates to PWs connected in parallel.
The present invention relates to an M converter, and particularly to a control device that suppresses a DC circulating current.

【0002】[0002]

【従来の技術】図2は、直流側を共通として負荷に直流
電力を供給する2台のPWMコンバータの並列装置構成
を示す。
2. Description of the Related Art FIG. 2 shows a parallel device configuration of two PWM converters for supplying DC power to a load with a common DC side.

【0003】3相交流電源1から2台の変圧器21、22
を通してコンバータ主回路31、32に交流電力を供給す
る。コンバータ主回路31、32は、ブリッジ接続の半導
体スイッチSU1〜SZ1、SU2〜SZ2と平滑コン
デンサCD1,CD2を備え、各半導体スイッチがPW
M制御されて電力変換し、共通の負荷4に直流電力を供
給する。
Three-phase AC power supply 1 to two transformers 2 1 and 2 2
AC power is supplied to the converter main circuits 3 1 and 3 2 through. The converter main circuits 3 1 and 3 2 include bridge-connected semiconductor switches SU1 to SZ1 and SU2 to SZ2 and smoothing capacitors CD1 and CD2, and each semiconductor switch is a PW.
The power is converted under M control to supply DC power to the common load 4.

【0004】コンバータ主回路31、32の制御装置
1、52の構成は、制御装置52に代表して示すよう
に、電圧制御系のマイナループに電流制御系を有してP
WMゲート信号を得る。
The control devices 5 1 and 5 2 of the converter main circuits 3 1 and 3 2 have a current control system in a minor loop of a voltage control system, as represented by the control device 5 2.
Obtain the WM gate signal.

【0005】コンバータ主回路32の入力電流IU,IW
をそれぞれホール変流器6U2,6W2により検出し、こ
れら検出信号をオフセット調整値I0SETで直流成分
を零に調整し、アンプ71、72を通して直流成分が零の
電流検出信号IU1,IW1を得る。V相の電流検出信号I
V1は、両検出信号IU1,IW1を加算器8により加算して
得る。
Input currents I U and I W of the converter main circuit 3 2
Are detected by Hall current transformers 6 U2 and 6 W2 , respectively, and the detection signals are adjusted to have a DC component of zero by an offset adjustment value I 0SET , and a current detection signal I U1 having a zero DC component is output through amplifiers 7 1 and 7 2. , I W1 . V-phase current detection signal I
V1 is obtained by adding both detection signals I U1 and I W1 by the adder 8.

【0006】コンバータ主回路31、32の直流出力電圧
は、電圧検出器9により検出し、この検出電圧を直流電
圧設定値VSETと比較し、その差を誤差アンプ10で増
幅する。
The DC output voltages of the converter main circuits 3 1 , 3 2 are detected by the voltage detector 9, the detected voltage is compared with the DC voltage set value V SET, and the difference is amplified by the error amplifier 10.

【0007】乗算器11U,11V,11Wは、検出トラ
ンス12で検出した各相電圧と誤差アンプ10の出力と
を乗算し、各相電圧に同期した(力率1.0)の電流指
令値IUS,IVS,IWSを得る。
The multipliers 11 U , 11 V , and 11 W multiply the respective phase voltages detected by the detection transformer 12 and the output of the error amplifier 10 to generate currents (power factor 1.0) synchronized with the respective phase voltages. Obtain the command values I US , I VS , and I WS .

【0008】各電流指令値IUS,IVS,IWSは、各相の
電流検出値IU1,IV1,IW1とそれぞれ比較し、誤差ア
ンプ13U,13V,13Wにより増幅し、PWM信号生
成部14により各相のPWMゲート信号を生成する。
The respective current command values I US , I VS , I WS are compared with the current detection values I U1 , I V1 , I W1 of the respective phases and amplified by the error amplifiers 13 U , 13 V , 13 W , The PWM signal generator 14 generates a PWM gate signal for each phase.

【0009】[0009]

【発明が解決しようとする課題】従来の構成において、
コンバータ主回路31、32の半導体素子のスイッチング
時間にズレが生じた場合には、コンバータ主回路31
2の間に循環電流が発生する。
SUMMARY OF THE INVENTION In the conventional configuration,
If the switching time of the semiconductor elements of the converter main circuits 3 1 , 3 2 is deviated, the converter main circuit 3 1 ,
A circulating current is generated during 3 2 .

【0010】この循環電流には、交流成分と直流成分が
存在する。交流成分は、交流2相間に接続されたホール
変流器により検出可能であり、制御可能な成分である。
The circulating current has an AC component and a DC component. The AC component is a component that can be detected and controlled by the Hall current transformer connected between the two AC phases.

【0011】しかし、直流成分がホール変流器を接続し
ていないV相を循環してしまうと、その検出ができず、
制御不能となるため、コンバータ主回路31、32の交流
入力側に変圧器21、22を設けている。
However, if the DC component circulates in the V phase to which the Hall current transformer is not connected, it cannot be detected,
Since it becomes uncontrollable, transformers 2 1 and 2 2 are provided on the AC input side of the converter main circuits 3 1 and 3 2 .

【0012】例えば、変圧器21、22を設けない場合、
矢印で示す経路、コンバータ主回路31の交流入力V相
→コンバータ主回路31の直流正極側→コンバータ主回
路32の直流正極側→コンバータ主回路32の直流負極側
→コンバータ主回路32の交流入力V相の経路で直流成
分が流れた場合、コンバータ主回路31からコンバータ
主回路32に電力を供給してしまい、コンバータ主回路
間の入力電力(電流)にアンバランスが発生する。
For example, when the transformers 2 1 and 2 2 are not provided,
Path indicated by the arrow, the converter main circuit 3 1 AC input V phase → the converter main circuit 3 first DC positive-side → converter main circuit 3 second DC positive-side → converter main circuit 3 2 of the DC negative-side → converter main circuit 3 When a DC component flows through the AC input V phase path of 2 , the converter main circuit 3 1 supplies power to the converter main circuit 3 2 and an imbalance occurs in the input power (current) between the converter main circuits. To do.

【0013】このように、交流入力と直流側共通のコン
バータ主回路31、32では直流成分の循環が避けられな
いため、両コンバータ主回路31、32の入力側に変圧器
1、22を設け、直流分をカットしている。
As described above, since the circulation of the DC component is unavoidable in the converter main circuits 3 1 and 3 2 common to the AC input and the DC side, the transformer 2 1 is provided on the input side of both converter main circuits 3 1 and 3 2. 2 2 are provided to cut the direct current component.

【0014】この構成では、各コンバータ主回路には電
力変換容量に相当する大型の変圧器を必要として、装置
の大型化とコストアップになる。
In this configuration, each converter main circuit requires a large transformer corresponding to the power conversion capacity, which leads to an increase in size and cost of the device.

【0015】[0015]

【課題を解決するための手段】本発明は、コンバータの
制御装置は電圧制御系のマイナループに電流制御系を有
してPWMゲート信号を得、該電流制御系は電圧制御系
から得る各相の電流指令とコンバータの主回路の各相入
力電流検出信号をそれぞれ比較する構成を特徴とする。
According to the present invention, a converter control device has a current control system in a minor loop of a voltage control system to obtain a PWM gate signal, and the current control system is provided for each phase obtained from the voltage control system. It is characterized in that the current command and the input current detection signals of the respective phases of the main circuit of the converter are compared with each other.

【0016】電流制御系を各相別に電流検出を行う構成
とし、コンバータ主回路間で交流成分及び直流成分の循
環電流が流れようとするときに、該循環電流を電流制御
系により抑制する。
The current control system is configured to detect the current for each phase, and when the circulating current of the AC component and the DC component is about to flow between the converter main circuits, the circulating current is suppressed by the current control system.

【0017】電流制御系による循環電流の抑制により、
コンバータ主回路の交流入力側に変圧器を不要にする。
By suppressing the circulating current by the current control system,
No transformer is required on the AC input side of the converter main circuit.

【0018】[0018]

【発明の実施の形態】図1は、本発明の一実施形態を示
す回路図である。同図が図2と異なる部分は、主回路か
らは変圧器21、22を省いて電源1から直接にコンバー
タ主回路31、32への交流印加を行い、制御装置51
2ではV相の電流も検出して各相毎にオフセット調整
した電流検出信号を得る点にある。
FIG. 1 is a circuit diagram showing an embodiment of the present invention. 2 is different from FIG. 2 in that the transformers 2 1 and 2 2 are omitted from the main circuit and the alternating current is directly applied from the power source 1 to the converter main circuits 3 1 and 3 2 , and the control device 5 1 ,
5 of 2 the V-phase current is also in view of obtaining a current detection signal offset adjustment for each phase is detected.

【0019】コンバータ主回路31、32の各相の交流入
力電流を検出するため、U,V,W相にそれぞれホール
変流器6U1,6V1,6W1,6U2,6V2,6W2を設ける。
この電流検出器は、直流分も含めた検出ができるもので
あれば良い。
In order to detect the AC input current of each phase of the converter main circuits 3 1 , 3 2 , Hall current transformers 6 U1 , 6 V1 , 6 W1 , 6 U2 , 6 V2 , are added to the U, V, W phases, respectively. Provide 6 W2 .
The current detector may be any detector that can detect the direct current component.

【0020】制御装置51、52では、制御装置52に代
表して示すように、V相の電流検出信号IVをオフセッ
ト調整値I0SETで直流成分を零に調整し、アンプ73
通して直流成分が零の電流検出信号IV1を得る。この電
流検出信号IV1は乗算器11Vの電流指令IVSと比較さ
れる。
In the control devices 5 1 and 5 2 , as represented by the control device 5 2 , the DC component is adjusted to zero by the offset adjustment value I 0SET of the V-phase current detection signal I V , and the amplifier 7 3 To obtain a current detection signal I V1 having a DC component of zero. This current detection signal I V1 is compared with the current command I VS of the multiplier 11 V.

【0021】本実施形態において、コンバータ主回路3
1、32の半導体素子のスイッチング時間にズレが生じ、
コンバータ主回路31、32の間に循環電流が発生しよう
とする場合、その交流成分及び直流成分は、各相に接続
されたホール変流器により検出され、交流成分と共に直
流成分は零に制御される。
In the present embodiment, the converter main circuit 3
1, deviation occurs in the 3 switching time of the second semiconductor element,
If circulating current between the converter main circuit 3 1, 3 2 is about to occur, the AC component and the DC component is detected by the Hall current transformer that is connected to each phase, the DC component with the AC component to zero Controlled.

【0022】これにより、コンバータ主回路31、32
の交流と直流成分の循環電流は抑制され、直流成分が零
になることからコンバータ主回路31、32の交流入力側
には変圧器が不要になる。また、コンバータ主回路間の
入力電力(電流)にアンバランスが発生するのを防止で
きる。
[0022] Thus, the converter main circuit 3 1, 3 circulating current of the AC and DC components of between 2 is suppressed, the converter main circuit 3 1 since the DC component becomes zero, 3 the second AC input side transformer No need for vessels. Further, it is possible to prevent imbalance in the input power (current) between the converter main circuits.

【0023】なお、PWMコンバータを3台以上に並列
接続する場合も同様に構成される。また、単相のPWM
コンバータの並列接続の場合も各相の電流検出により循
環電流(交流、直流成分)を抑制できる。
The same configuration is adopted when three or more PWM converters are connected in parallel. Also, single-phase PWM
Even when the converters are connected in parallel, the circulating current (AC and DC components) can be suppressed by detecting the current of each phase.

【0024】[0024]

【発明の効果】以上のとおり、本発明によれば、コンバ
ータ制御装置の電流制御系は、各相別に電流検出を行う
構成としたため、コンバータ主回路間で交流成分及び直
流成分の循環電流が流れようとするときに、該循環電流
を電流制御系により抑制することができ、コンバータ主
回路の交流入力側に変圧器を不要にする効果がある。
As described above, according to the present invention, since the current control system of the converter control device is configured to detect the current for each phase, the circulating currents of the AC component and the DC component flow between the converter main circuits. In this case, the circulating current can be suppressed by the current control system, which has the effect of eliminating the need for a transformer on the AC input side of the converter main circuit.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の一実施形態を示す回路図。FIG. 1 is a circuit diagram showing one embodiment of the present invention.

【図2】従来例の回路図。FIG. 2 is a circuit diagram of a conventional example.

【符号の説明】[Explanation of symbols]

1、32…コンバータ主回路 4…負荷 51、52…制御装置 6U1、6W2…ホール変流器 71、72、73…アンプ 9…電圧検出器 10…誤差アンプ 11U、11V、11W…乗算器 12…検出トランス 13U、13V、13W…誤差アンプ3 1 3 2 ... Converter main circuit 4 ... Load 5 1 5 2 ... Control device 6 U1 , 6 W2 ... Hall current transformer 7 1 , 7 2 , 7 3 ... Amplifier 9 ... Voltage detector 10 ... Error amplifier 11 U , 11 V , 11 W ... Multiplier 12 ... Detection transformer 13 U , 13 V , 13 W ... Error amplifier

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】 並列接続したPWMコンバータにおい
て、各コンバータの主回路の交流入力側は交流電源に直
接接続し、コンバータの制御装置は電圧制御系のマイナ
ループに電流制御系を有してPWMゲート信号を得、該
電流制御系は電圧制御系から得る各相の電流指令とコン
バータの主回路の各相入力電流検出信号をそれぞれ比較
する構成を特徴とするPWMコンバータ。
1. In a PWM converter connected in parallel, an AC input side of a main circuit of each converter is directly connected to an AC power source, and a converter control device has a current control system in a minor loop of a voltage control system and a PWM gate signal. And a current control system for comparing each phase current command obtained from the voltage control system with each phase input current detection signal of the main circuit of the converter.
JP7182371A 1995-07-19 1995-07-19 Pwm converter Pending JPH0937552A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7182371A JPH0937552A (en) 1995-07-19 1995-07-19 Pwm converter

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7182371A JPH0937552A (en) 1995-07-19 1995-07-19 Pwm converter

Publications (1)

Publication Number Publication Date
JPH0937552A true JPH0937552A (en) 1997-02-07

Family

ID=16117149

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7182371A Pending JPH0937552A (en) 1995-07-19 1995-07-19 Pwm converter

Country Status (1)

Country Link
JP (1) JPH0937552A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007028809A (en) * 2005-07-19 2007-02-01 Meidensha Corp Offset voltage detector of pwm converter
WO2007135730A1 (en) * 2006-05-23 2007-11-29 Mitsubishi Denki Kabushiki Kaisha Power converter
JP2010259298A (en) * 2009-04-28 2010-11-11 Tokyo Electron Ltd Thermal treatment system

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06105556A (en) * 1992-09-17 1994-04-15 Hitachi Ltd Power converter
JPH06153519A (en) * 1992-11-12 1994-05-31 Hitachi Ltd Power converter for parallel operation system

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06105556A (en) * 1992-09-17 1994-04-15 Hitachi Ltd Power converter
JPH06153519A (en) * 1992-11-12 1994-05-31 Hitachi Ltd Power converter for parallel operation system

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007028809A (en) * 2005-07-19 2007-02-01 Meidensha Corp Offset voltage detector of pwm converter
WO2007135730A1 (en) * 2006-05-23 2007-11-29 Mitsubishi Denki Kabushiki Kaisha Power converter
US7835165B2 (en) 2006-05-23 2010-11-16 Mitsubishi Electric Corporation Power converting apparatus
JP2010259298A (en) * 2009-04-28 2010-11-11 Tokyo Electron Ltd Thermal treatment system

Similar Documents

Publication Publication Date Title
US7327588B2 (en) Synchronization of parallel-connected inverter units or frequency converters
JP2526992B2 (en) AC output converter parallel operation system
Jacobina et al. Fault-tolerant reversible AC motor drive system
JPH09224376A (en) Power conversion method and power converter
JP2007300712A (en) Ac power feeding device
JP3588932B2 (en) Power converter, control method therefor, and uninterruptible power supply using this power converter
JP2004254360A (en) Backup device of ac-ac power converter
JPH0937552A (en) Pwm converter
JPH0638538A (en) Three-phase output voltage balanced system for uninterruptible power source
JP2010011613A (en) Pwm converter device
WO2018051433A1 (en) Power supply system
Biel et al. Control strategy for parallel-connected three-phase inverters
JP2009177901A (en) Uninterruptible power supply device
JP2001258258A (en) Pwm cycloconverter
JP3070314B2 (en) Inverter output voltage compensation circuit
JPH0746847A (en) Three-phase rectifier
JP2005348563A (en) Ac power supply apparatus
JPH105189A (en) Power power unit for magnetic resonance imaging device
JP2533646B2 (en) Semiconductor aging equipment
JP2509890B2 (en) Pulse width modulation control method for AC / DC converter
JP2002017088A (en) Controller for power conversion device
KR20040040530A (en) Parallel control system of single-phase inverter
JP3079610B2 (en) Power supply unbalance countermeasure device
JP2003219662A (en) Semiconductor power converter
JPS6130967A (en) Parallel operation device of inverter