JPH0557933U - Clock pulse regeneration circuit - Google Patents

Abstract

(57) [Summary] [Object] To easily reproduce a clock pulse accurately synchronized with an input data signal having a duty cycle other than 50%. A time interval from each pulse of a reproduced clock pulse B generated from a clock generating means 9 to each rising edge and each falling edge of an input data signal A is calculated by using a count clock which is sufficiently faster than the data signal A. The first and second counters 1 and 2 respectively count, and the two count outputs are compared 7
By controlling the phase of the reproduction clock pulse B by giving the output obtained by comparison in step 1 to the clock generation means 9, the reproduction clock pulse B is controlled to be positioned at the center of the 1-bit cycle of the input data signal A. .

Description

[Detailed description of the device]

[0001]

[Industrial application]

 The present invention relates to a clock pulse regeneration circuit used in various digital devices.

[0002]

[Prior Art]

 For example, when the received data signal is sampled and reproduced, it is necessary to create a sampling clock accurately synchronized with the received data signal. In such a case, what has been often used conventionally is to frequency-multiply the above-mentioned data signal to the frequency of the clock pulse, compare the multiplied output with the clock pulse from the VCO (voltage controlled oscillator), and This is a method of obtaining a clock pulse by a so-called PLL circuit that controls the oscillation phase of the VCO according to the comparison output.

[0003]

[Problems to be solved by the device]

 Now, in such a conventional PLL circuit, when the duty cycle of the input data signal is 50% (Fig. 4), as can be seen from the figure, even if the oscillation clock is in the phase shown in the figure, it is output as a multiplied output of the input data signal. It is easily synchronized and locked, but in the case other than 50% (Fig. 5), the oscillation clock does not easily lock to the multiplied output.

Therefore, an object of the present invention is to make it possible to accurately and easily generate a clock pulse synchronized with an input data signal having a duty cycle other than 50%.

[0005]

[Means for Solving the Problems]

 The clock pulse regeneration circuit of the present invention comprises a first counter for counting the time interval from one of the rising edge and the falling edge of the input data signal to the regeneration clock pulse by a count clock which is sufficiently faster than the data signal. A second counter that counts the time interval from the reproduction clock pulse to the other edge of the rising and falling edges and a comparison that compares the outputs of the first and second counters at the timing synchronized with the input data. And a clock generating means whose phase is controlled by the output of the comparator, and the reproduction clock pulse is obtained from the clock generating means.

Further, it is particularly preferable that the clock generating means is composed of a variable frequency dividing circuit in which the frequency dividing ratio of the count clock is changed according to the output of the comparator.

[0007]

[Work]

 According to the above configuration, it is directly detected whether the reproduction clock pulse deviates from the center of the 1-bit period of the input data signal to the front or back, and the phase of the reproduction clock pulse is controlled according to the detected amount. ..

By configuring the clock generating means by the above-mentioned variable frequency dividing circuit, the entire circuit is realized in a pure digital manner.

[0009]

【Example】

 First, FIG. 1 shows a first embodiment of the present invention, and FIG. 2 shows a time chart of the essential parts thereof.

In FIG. 1, reference numeral 1 indicates the count operation of a count clock (not shown) when the rising edge of the input data signal A is applied, and the above count when a reproduction clock pulse B described later is applied. On the contrary, the first counter 2 which stops the operation starts the counting operation of the count clock when the clock pulse B is applied, and the input data signal A is inverted by the inverter 3 to cause the falling edge of the data signal. Is a second counter that stops the above counting operation. Therefore, during the period from t1 to t2 in FIG. 2, the count outputs of the first and second counters 1 and 2 change as shown in C and D of FIG. 2, respectively. (The frequency of the count clock is selected to be sufficiently higher than that of the reproduction clock pulse B.) The outputs C and D of the first and second counters 1 and 2 have the input data signal A as the inverter 6 respectively. It is latched by the first and second latch circuits 4 and 5 which are given as a latch pulse via each of them at each falling timing of the input data signal A. After that, the respective latch outputs are compared by the counting comparator 7.

When the output of the first latch circuit 4 (count output C) is larger than the output of the second latch circuit 5 (count output D), the reproduced clock pulse B is the input data signal A. Since it indicates that the 1-bit period is shifted to the rear (lagging side) from the center, the comparator 7 at this time shifts the deviation amount so as to control the reproduced clock pulse B in the leading direction. Generates a positive signal of a magnitude corresponding to.

On the contrary, when the output of the first latch circuit 4 (count output C) is smaller than the output of the second latch circuit 5 (count output D), the reproduction clock pulse B becomes 1 of the input data signal A. Since it indicates that the bit cycle is shifted forward (advance phase side) from the center of the bit cycle, at this time, the comparator 7 controls the reproduction clock pulse B in the phase lag direction according to the deviation amount. Generate a negative signal of a certain magnitude. Further, when both the latch outputs are equal, the output of the comparator 7 becomes zero.

The output of the comparator 7 is converted into an analog signal by the D / A converter 8 and then applied as a control voltage of a VCO 9 as a clock pulse generating means, and a reproduction clock pulse generated from the VCO 9 is generated. The phase of B is controlled as described above.

Here, when the falling edge of the input data signal A does not arrive between the pulse of the reproduction clock pulse B and the next pulse as in the period of t3 to t4 of FIG. 2, the second counter 2 is Each time the clock pulse B is re-triggered and the counting operation is started from zero (cleared and then started), it changes as shown in the figure. At this time, the second latch circuit 5 does not operate at time t2. The count output of is still latched. Therefore, the output change of the comparator 7 becomes like E, and the phase pull-in operation does not malfunction during this period.

Next, a second embodiment of the present invention in which the entire circuit shown in FIG. 3 is configured in pure digital form will be described.

In the embodiment of FIG. 3, in place of the D / A converter 8 and the VCO 9 of FIG. 1, third, fourth and fifth counters 10 to 12 and an OR gate 13 which constitute a frequency division ratio determining circuit are provided. , A sixth counter 14 that operates as a variable frequency dividing circuit for the count clock is provided, and the output of the sixth counter 14 is taken out as a reproduction clock pulse B, and the first and second counters 1 and 2 are taken out as in the case of FIG. To give to.

More specifically, in the comparator 7, unlike the one shown in FIG. 1, the output (count output C) of the first latch circuit 4 is the output of the second latch circuit 5 (count output D). When it is larger than (see FIG. 2), an H level output is generated at the upper output terminal in the figure, and conversely, when the output of the first latch circuit 4 is smaller than the output of the second latch circuit 5. Produces a similar output at the bottom output terminal of the figure.

Each of the third and fifth counters 10 and 12 is applied with the respective outputs of the comparator 7 as a count enable signal, and counts the falling edge of the data signal A inverted by the inverter 6. A binary (eg N = 2 or 4) counter. On the other hand, the fourth counter 11 is also an M-ary (M> N, for example M = 3 or 5) counter that counts the trailing edge of the data signal A.

Therefore, when an output is generated at the output terminal on the upper side of the comparator 7, the third counter 10 and the fourth counter 11 start counting operation. The 3 counter 10 overflows earlier than the M-ary 4th counter 11 to generate a carrier signal. Then, the carry signal of the N-ary counter is applied to one of the division ratio setting terminals at the upper end of the sixth counter 14 and the third to fifth counters 10 to 12 are reset via the OR gate 13. ..

Here, the sixth counter 14 is provided for dividing the count clock to generate the reproduction clock pulse B. Now, assuming that the speed of the data signal A is 1 Kbps, the frequency of the count clock is Is 1 MHz, if the frequency division ratio K of the sixth counter 14 is slightly changed around K = 1000, the phase of the reproduced clock pulse B can be changed and accurately synchronized with the data signal A.

Therefore, in the above-mentioned case, when an output is generated at the upper terminal of the comparator 7, that is, the reproduced clock pulse B is located behind the center of the 1-bit cycle of the input data signal A (on the delay side). Since it is at the time of deviation, a carry signal is given to the upper frequency division ratio setting terminal of the sixth counter 14 to set the frequency division ratio of this counter 14 to K-1. Then, by this, the reproduced clock pulse B is advanced and synchronized with the data signal A.

Further, when an output is generated at the lower terminal of the comparator 7, that is, when the recovered clock pulse B deviates from the center of the 1-bit cycle of the input data signal A (to the delay side). Similarly, the carry signal from the fifth counter 12 is applied to the frequency division ratio setting terminal at the lower end of the sixth counter 14 to set the frequency division ratio to K + 1, whereby the recovered clock pulse B is delayed. become.

Further, when the reproduced clock pulse B is located exactly in the center of the 1-bit cycle of the input data signal A, an output is generated at the upper output terminal of the comparator 7 or an output is generated at the lower output terminal. Therefore, in this case, the carry signal is generated earlier in the fourth counter than in the third and fifth counters. Therefore, this carry signal is applied to the frequency division ratio setting terminal at the center of the sixth counter 14, the frequency division ratio is set to K, and the synchronization state is maintained.

In the above-described embodiment, the falling edges of the data signal A are directly counted by the third to fifth counters 10 to 12, but this falling edge is used as the count start signal and the reproduced clock pulse B after that is counted. May be counted. In this case, the values of N and M described above may be set to be slightly larger than those described above (for example, N = 8 and M = 10).

Further, the third to fifth counters 10 to 12 are provided to have a kind of low-pass filter function in order to avoid the influence of malfunction of the comparator 7 due to a single noise or the like. Therefore, it is also possible to delete each of these counters when there is no such fear.

[0026]

[Effect of the device]

 According to the clock pulse reproduction circuit of the present invention, the reproduction clock pulse is directly compared with the input data by the comparator, and the reproduction clock pulse is controlled so as to be positioned at the center of the 1-bit cycle of the input data signal. Therefore, even for an input data signal having a duty cycle other than 50%, it is possible to easily obtain a reproduced clock signal accurately synchronized with this data signal.

Further, in particular, if the reproduced clock pulse is created by a variable frequency dividing circuit whose frequency dividing ratio is switched according to the output of the comparator, the entire circuit can be configured in pure digital form, and It can be stabilized and can be realized at low cost.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is a diagram showing an operation time chart thereof.

FIG. 3 is a block diagram showing another embodiment of the present invention.

FIG. 4 is a waveform diagram for explaining the operation of the conventional example.

FIG. 5 is a waveform diagram for explaining another operation of the conventional example.

[Explanation of symbols]

 1 1st counter 2 2nd counter 7 Comparator 9 Clock generation means

Continuation of the front page (51) Int.Cl. ⁵ Identification code Office reference number FI technical display location 9182-5J H03L 7/08 P

Claims (2)

[Scope of utility model registration request] 1. A clock pulse regeneration circuit for obtaining an input data signal and generating a clock pulse synchronized with the data signal, comprising: A first counter which counts a time interval by a count clock sufficiently faster than the data signal; and a second counter which counts a time interval from the reproduction clock pulse to each of the other edges of the rising and falling edges. It comprises a comparator for comparing each count output of the first and second counters at a timing synchronized with the input data, and a clock generating means whose phase is controlled according to the output of the comparator. A clock pulse regeneration circuit designed to obtain pulses. 2. The clock generating means is composed of a variable frequency dividing circuit in which the frequency dividing ratio of the count clock is changed according to the output of the comparator.
The described clock pulse regeneration circuit.