JPH0557119B2 - - Google Patents

Info

Publication number
JPH0557119B2
JPH0557119B2 JP57184566A JP18456682A JPH0557119B2 JP H0557119 B2 JPH0557119 B2 JP H0557119B2 JP 57184566 A JP57184566 A JP 57184566A JP 18456682 A JP18456682 A JP 18456682A JP H0557119 B2 JPH0557119 B2 JP H0557119B2
Authority
JP
Japan
Prior art keywords
integrated circuit
chip
substrate
circuit chip
card
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP57184566A
Other languages
Japanese (ja)
Other versions
JPS5974639A (en
Inventor
Kenzo Masuda
Kenichi Ishibashi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP57184566A priority Critical patent/JPS5974639A/en
Publication of JPS5974639A publication Critical patent/JPS5974639A/en
Publication of JPH0557119B2 publication Critical patent/JPH0557119B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
    • H01L2224/48472—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/8385—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01019—Potassium [K]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01052—Tellurium [Te]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01076—Osmium [Os]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/06—Polymers
    • H01L2924/078—Adhesive characteristics other than chemical
    • H01L2924/07802—Adhesive characteristics other than chemical not being an ohmic electrical conductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/15165—Monolayer substrate

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Credit Cards Or The Like (AREA)
  • Die Bonding (AREA)

Abstract

PURPOSE:To reduce stress applied to an integrated circuit chip, and to prevent the damage of the chip by fitting the chip to a substrate so that the lateral direction of the chip is directed toward the direction in which the bending stress of the substrate is large. CONSTITUTION:A recessed section 2 for incorporating the integrated circuit chip 3 is formed at the central section of the card substrate 1 as an auxiliary card for a cash card, an ID card, etc. The substrate 1 is formed to a plane shape, the size of the longitudinal direction is made to be l1 and the size of the lateral direction to be l2, and the longitudinal direction is made larger than the lateral direction in bending stress to the substrate 1. The recessed section 2 to which the chip 3 is fitted is formed to a plane shape, the size l3 of the lateral direction is made smaller than that l4 of the longitudinal direction, and the direction of fitting of the chip 3 is directed toward the longitudinal direction of the substrate 1 in the lateral direction of the chip. The chip 3 is fitted in the recessed section 2, the bonding pads of the chip 3 are connected by wires 4 between the pad and a conductor layer in the recessed section 2, the wires are drawn out to the outside from a printed wiring by a wiring, and stress applied to the chip 3 is reduced.

Description

【発明の詳細な説明】 本発明は集積回路チツプに加わる曲げ応力を低
減できる薄板状集積回路基板に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a thin integrated circuit board capable of reducing bending stress applied to integrated circuit chips.

近年、集積回路（IC）や大規模集積回路
（LSI）を内蔵したカード類、たとえばキヤツシ
ユカード、クレジツトカード、IDカード、電子
ロツク、コンピユータやPOS端末等の補助記憶
カード等の使用上の便利さが注目され、実用化へ
の要求が高まつている。 In recent years, cards with built-in integrated circuits (ICs) or large-scale integrated circuits (LSIs), such as cash cards, credit cards, ID cards, electronic locks, and auxiliary memory cards for computers and POS terminals, have become more convenient to use. This is attracting attention, and demands for practical application are increasing.

ところで、このようなカード類においては、そ
の取扱中や携帯中等にカードに対して相当大きな
曲げ応力がかかることがあるが、カードの厚さが
薄いので、曲げにより集積回路チツプが破壊され
てしまうという問題がある。この問題は、カード
の薄板化の傾向につれて、ますます大きくなりつ
つある。 By the way, when such cards are handled or carried, considerable bending stress may be applied to the card, but since the card is thin, the integrated circuit chip may be destroyed by bending. There is a problem. This problem is becoming more and more significant as cards tend to become thinner.

本発明の目的は、前記した問題点に鑑み、集積
回路チツプにかかる曲げ応力を低減し、チツプの
破壊を防止することのできる薄板状集積回路基板
を提供することにある。 SUMMARY OF THE INVENTION In view of the above problems, an object of the present invention is to provide a thin integrated circuit board that can reduce the bending stress applied to integrated circuit chips and prevent the chips from breaking.

以下、本発明を図面に示す一実施例にしたがつ
て詳細に説明する。 Hereinafter, the present invention will be explained in detail according to an embodiment shown in the drawings.

第１図は本発明による薄板状集積回路基板の一
実施例における集積回路チツプのカード基板への
取付方向を示す平面図である。 FIG. 1 is a plan view showing the direction in which an integrated circuit chip is attached to a card board in an embodiment of the thin integrated circuit board according to the present invention.

この実施例において、カード基板１はたとえば
ガラス−エポキシ材料よりなる薄板状構造であ
り、キヤツシユカード、クレジツトカード、ID
カード、電子ロツク、コンピユータやPOS端末
等の補助記憶カード等の基板として用いられる。 In this embodiment, the card substrate 1 is a thin plate-like structure made of, for example, glass-epoxy material, and is used for carrying cash cards, credit cards, ID cards, etc.
Used as substrates for cards, electronic locks, auxiliary memory cards for computers, POS terminals, etc.

このカード基板１は中央部に集積回路チツプ内
蔵用の凹部２を有し、その全体的平面形状は長方
形であり、長手方向の寸法l1＞短手方向の寸法l2
となつているので、このカード基板１に対する曲
げ応力は長手方向の方が短手方向よりも大きくな
る。 This card board 1 has a recess 2 in the center for embedding an integrated circuit chip, and its overall planar shape is rectangular, with length l 1 > width l 2
Therefore, the bending stress on the card substrate 1 is greater in the longitudinal direction than in the transverse direction.

前記凹部２内には、集積回路チツプ３が取り付
けられるが、この集積回路チツプ３の平面形状は
短手方向が寸法l3、長手方向が寸法l4（l3＜l4）の
長方形である。 An integrated circuit chip 3 is installed in the recess 2, and the planar shape of the integrated circuit chip 3 is a rectangle with a dimension l 3 in the short direction and a dimension l 4 (l 3 < l 4 ) in the longitudinal direction. .

この集積回路チツプ３の取付方向は、その短手
方向がカード基板１の曲げ応力の大きい方向すな
わち本実施例では該カード基板１の長手方向とな
つている。 The direction in which this integrated circuit chip 3 is attached is such that its short side is the direction in which the bending stress of the card board 1 is greater, that is, in this embodiment, the longitudinal direction of the card board 1.

この集積回路チツプ３はカード基板１の凹部２
内に取り付けた後、第２図に示すように、該集積
回路チツプ３のボンデイングパツドと凹部２内に
形成した導電層との間にワイヤ４をボンデイング
して電気的に接続し、配線５を介してカード基板
１の上面のプリント配線６から外部への電気的導
通を行なう。 This integrated circuit chip 3 is located in the recess 2 of the card substrate 1.
As shown in FIG. 2, a wire 4 is bonded between the bonding pad of the integrated circuit chip 3 and the conductive layer formed in the recess 2 to electrically connect the wire 5. Electrical continuity is established from the printed wiring 6 on the upper surface of the card board 1 to the outside through the wiring.

また、前記凹部２の中には、封止用のレジン７
がポツテイング等で供給され、集積回路チツプ３
およびワイヤ４を凹部２内に封止している。 Further, in the recess 2, a sealing resin 7 is provided.
is supplied by potting etc., and the integrated circuit chip 3
and a wire 4 is sealed within the recess 2.

本実施例においては、前記の如く、集積回路チ
ツプ３はその短手方向がカード基板１の曲げ応力
の大きい方向（長手方向）となるように配置され
ているので、カード基板１が長手方向に曲げられ
ても、集積回路チツプ３に加わる曲げ応力は低減
され、該集積回路チツプ３はその曲げ応力に十分
耐えることができ、チツプ３の破壊を起こすこと
を防止できる。 In this embodiment, as described above, the integrated circuit chip 3 is arranged such that its short side direction is the direction (longitudinal direction) where the bending stress of the card board 1 is large, so that the card board 1 is Even when bent, the bending stress applied to the integrated circuit chip 3 is reduced, the integrated circuit chip 3 can sufficiently withstand the bending stress, and the chip 3 can be prevented from breaking.

したがつて、カード基板１自体に要求される剛
性は緩和され、該カード基板１自体の厚さをより
薄くし、さらに使い易いものにすることができ
る。 Therefore, the rigidity required for the card substrate 1 itself is relaxed, and the thickness of the card substrate 1 itself can be made thinner, making it easier to use.

また、本実施例では、カード基板１は短手方向
には曲がりにくいので、短手方向に大きい曲げ応
力を受けず、集積回路チツプ３が長手方向に大き
く曲げられて破壊されることもない。 Further, in this embodiment, since the card substrate 1 is difficult to bend in the lateral direction, it is not subjected to large bending stress in the lateral direction, and the integrated circuit chip 3 is not bent greatly in the longitudinal direction and destroyed.

なお、本発明は前記実施例に限定されるもので
はない。たとえば、前記実施例では、カード基板
１は長方形状として説明したが、正方形でもよ
く、その場合でも、カード基板１の曲がり易い方
向に集積回路チツプ３の短手方向を配向すれば、
同様に曲げ応力の低減、ひいては集積回路チツプ
３の破壊防止を図ることができる。 Note that the present invention is not limited to the above embodiments. For example, in the above embodiment, the card board 1 is described as having a rectangular shape, but it may be square.Even in that case, if the short side of the integrated circuit chip 3 is oriented in the direction in which the card board 1 is easy to bend,
Similarly, bending stress can be reduced, and the integrated circuit chip 3 can be prevented from being destroyed.

以上説明したように、本発明によれば、集積回
路チツプに加わる曲げ応力を低減し、集積回路チ
ツプの破壊を防止することができる。 As explained above, according to the present invention, it is possible to reduce the bending stress applied to the integrated circuit chip and prevent the integrated circuit chip from being destroyed.

【図面の簡単な説明】[Brief explanation of drawings]

第１図は本発明におけるカード基板に対する集
積回路チツプの取付方向を示す概略的平面図、第
２図は本発明による薄板状集積回路基板の一実施
例を示す断面図である。 １…カード基板、２…凹部、３…集積回路チツ
プ、４…ワイヤ、５…配線、６…プリント配線、
７…封止用のレジン。 FIG. 1 is a schematic plan view showing the mounting direction of an integrated circuit chip on a card board according to the present invention, and FIG. 2 is a sectional view showing an embodiment of the thin integrated circuit board according to the present invention. DESCRIPTION OF SYMBOLS 1...Card board, 2...Recessed part, 3...Integrated circuit chip, 4...Wire, 5...Wiring, 6...Printed wiring,
7...Resin for sealing.

Claims (1)

【特許請求の範囲】 １ 中央部に集積回路チツプ内蔵用の凹部を有
し、全体的平面形状が長方形である薄板状集積回
路基板であつて、該凹部と該薄板状集積回路基板
上面端のプリント配線を接続する導電層を有する
薄板状集積回路基板において、 集積回路チツプの短手方向が該薄板状集積回路
基板の長手方向となるように上記凹部に取り付
け、 該集積回路のボンデイングパツドと凹部内に形
成した上記導電層との間にワイヤをボンデイング
して電気的に接続し、 上記凹部の中にレジンをポリデイングして封止
する薄板状集積回路基板の製法。[Scope of Claims] 1. A thin integrated circuit board having a recess in the center for embedding an integrated circuit chip and having a rectangular overall planar shape, wherein the recess and the upper end of the thin integrated circuit board In a thin integrated circuit board having a conductive layer for connecting printed wiring, the integrated circuit chip is mounted in the recess so that the shorter direction of the integrated circuit chip is the longitudinal direction of the thin integrated circuit board, and the bonding pad of the integrated circuit is connected to the integrated circuit chip. A method for manufacturing a thin integrated circuit board, comprising bonding a wire to the conductive layer formed in the recess for electrical connection, and sealing the recess by polydepositing a resin.
JP57184566A 1982-10-22 1982-10-22 Sheet-shaped integrated circuit substrate Granted JPS5974639A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57184566A JPS5974639A (en) 1982-10-22 1982-10-22 Sheet-shaped integrated circuit substrate

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57184566A JPS5974639A (en) 1982-10-22 1982-10-22 Sheet-shaped integrated circuit substrate

Publications (2)

Publication Number Publication Date
JPS5974639A JPS5974639A (en) 1984-04-27
JPH0557119B2 true JPH0557119B2 (en) 1993-08-23

Family

ID=16155445

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57184566A Granted JPS5974639A (en) 1982-10-22 1982-10-22 Sheet-shaped integrated circuit substrate

Country Status (1)

Country Link
JP (1) JPS5974639A (en)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0517269Y2 (en) * 1986-05-15 1993-05-10
JP2578443B2 (en) * 1987-10-13 1997-02-05 大日本印刷株式会社 IC card and IC module for IC card
JPH0789281A (en) * 1993-11-29 1995-04-04 Ryoden Kasei Co Ltd Ic card

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5329260A (en) * 1976-08-31 1978-03-18 Ishikawajima Harima Heavy Ind Device for penetrating plate of tension bridle
JPS5752977A (en) * 1980-08-07 1982-03-29 Gao Ges Automation Org Identifying card and method of producing same
JPS58125892A (en) * 1981-12-24 1983-07-27 ゲ−ア−オ−・ゲゼルシヤフト・フユ−ル・アウトマチオン・ウント・オルガニザチオン・エム・ベ−・ハ− Identification card and carrier element having integrated circut module

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5819639Y2 (en) * 1978-10-02 1983-04-22 富士通株式会社 memory card

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5329260A (en) * 1976-08-31 1978-03-18 Ishikawajima Harima Heavy Ind Device for penetrating plate of tension bridle
JPS5752977A (en) * 1980-08-07 1982-03-29 Gao Ges Automation Org Identifying card and method of producing same
JPS58125892A (en) * 1981-12-24 1983-07-27 ゲ−ア−オ−・ゲゼルシヤフト・フユ−ル・アウトマチオン・ウント・オルガニザチオン・エム・ベ−・ハ− Identification card and carrier element having integrated circut module

Also Published As

Publication number Publication date
JPS5974639A (en) 1984-04-27

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